Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T1

8

T5

11

T3

29

auto[1]

1142

1

T1

12

T5

9

T3

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T1

6

T5

5

T3

14

from_0to1

548

1

T1

6

T5

5

T3

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T1

13

T5

7

T3

31

auto[1]

1104

1

T1

7

T5

13

T3

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T1

8

T5

10

T3

30

auto[1]

1174

1

T1

12

T5

10

T3

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T1

2

T5

1

T3

2

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T1

1

T3

3

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T5

1

T3

1

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T5

1

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T1

1

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T1

1

T3

4

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T5

1

T3

2

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T3

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T5

2

T3

3

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T1

2

T8

1

T94

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T1

1

T3

1

T358

1

auto[1]

from_1to0

auto[1]

auto[1]

79

1

T3

3

T8

1

T10

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T3

1

T8

1

T12

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T1

2

T3

1

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T1

1

T5

1

T3

4

auto[1]

from_0to1

auto[1]

auto[1]

95

1

T1

1

T5

2

T8

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1168

1

T1

7

T5

11

T3

29

auto[1]

1107

1

T1

13

T5

9

T3

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T1

5

T5

3

T3

16

from_0to1

520

1

T1

5

T5

4

T3

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T1

8

T5

11

T3

34

auto[1]

1114

1

T1

12

T5

9

T3

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T1

11

T5

11

T3

30

auto[1]

1150

1

T1

9

T5

9

T3

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T1

1

T3

2

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T3

3

T8

1

T122

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T5

1

T3

3

T8

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T1

1

T12

2

T122

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T3

3

T10

1

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T3

2

T8

1

T12

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T1

1

T5

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T5

1

T3

2

T122

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T1

1

T3

2

T8

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T5

1

T3

2

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T1

1

T3

2

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T1

1

T5

1

T3

2

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T5

1

T3

1

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T1

1

T5

1

T3

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T1

3

T3

1

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T3

4

T94

3

T33

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T1

7

T5

10

T3

26

auto[1]

1155

1

T1

13

T5

10

T3

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T1

3

T5

6

T3

13

from_0to1

544

1

T1

4

T5

6

T3

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T1

12

T5

12

T3

29

auto[1]

1177

1

T1

8

T5

8

T3

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T1

8

T5

8

T3

30

auto[1]

1146

1

T1

12

T5

12

T3

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

3

T3

2

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T3

1

T122

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T8

1

T10

2

T94

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T5

1

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T1

1

T5

1

T3

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T3

2

T8

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T10

1

T12

1

T94

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T3

1

T10

1

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T1

1

T5

1

T3

3

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T1

1

T5

1

T3

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T3

3

T8

1

T94

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T3

1

T8

2

T12

3

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T1

1

T5

1

T3

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T5

2

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T1

1

T5

1

T3

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T5

1

T3

5

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T1

10

T5

7

T3

28

auto[1]

1157

1

T1

10

T5

13

T3

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T1

5

T5

3

T3

17

from_0to1

508

1

T1

5

T5

3

T3

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T1

11

T5

11

T3

33

auto[1]

1164

1

T1

9

T5

9

T3

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T1

12

T5

7

T3

35

auto[1]

1133

1

T1

8

T5

13

T3

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T1

3

T3

4

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T5

1

T3

1

T10

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T5

1

T3

3

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T1

1

T8

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T1

1

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T3

2

T12

1

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T3

1

T8

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T1

1

T3

2

T10

2

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T3

4

T8

1

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T1

1

T3

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T3

1

T10

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T3

3

T8

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T5

2

T3

2

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T5

1

T3

4

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T1

1

T3

2

T12

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T1

2

T3

2

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1156

1

T1

7

T5

14

T3

31

auto[1]

1119

1

T1

13

T5

6

T3

29

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T1

6

T5

4

T3

14

from_0to1

547

1

T1

7

T5

4

T3

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1164

1

T1

7

T5

9

T3

27

auto[1]

1111

1

T1

13

T5

11

T3

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T1

8

T5

10

T3

28

auto[1]

1112

1

T1

12

T5

10

T3

32

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T5

1

T10

1

T122

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T5

1

T3

2

T94

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T1

2

T5

1

T3

4

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T8

1

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T3

1

T33

1

T144

3

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T5

1

T3

2

T8

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T5

2

T3

2

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T1

2

T5

1

T3

2

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T3

2

T8

1

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

86

1

T1

3

T3

2

T12

4

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

1

T3

2

T33

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T3

2

T8

1

T12

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T8

1

T10

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T1

1

T3

3

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T1

2

T3

1

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T1

2

T3

4

T122

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T1

13

T5

10

T3

20

auto[1]

1194

1

T1

7

T5

10

T3

40

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

553

1

T1

4

T5

7

T3

17

from_0to1

558

1

T1

5

T5

6

T3

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T1

11

T5

9

T3

27

auto[1]

1075

1

T1

9

T5

11

T3

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1189

1

T1

11

T5

12

T3

28

auto[1]

1086

1

T1

9

T5

8

T3

32

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T1

1

T10

1

T359

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T5

2

T3

2

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T5

2

T3

3

T8

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T1

1

T3

1

T10

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T1

1

T3

3

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T1

1

T5

1

T122

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T1

1

T5

2

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T10

1

T359

1

T34

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T5

1

T3

3

T8

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T1

1

T5

1

T3

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T1

1

T5

1

T3

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T3

5

T12

1

T122

1

auto[1]

from_0to1

auto[0]

auto[0]

86

1

T1

1

T3

4

T8

1

auto[1]

from_0to1

auto[0]

auto[1]

89

1

T1

1

T3

6

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T5

3

T3

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T3

1

T10

1

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T1

7

T5

12

T3

26

auto[1]

1127

1

T1

13

T5

8

T3

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T1

4

T5

4

T3

17

from_0to1

536

1

T1

4

T5

4

T3

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T1

13

T5

10

T3

31

auto[1]

1113

1

T1

7

T5

10

T3

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T1

8

T5

12

T3

32

auto[1]

1122

1

T1

12

T5

8

T3

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T5

1

T3

4

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T3

2

T10

1

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T5

2

T3

2

T8

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T1

1

T3

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T3

1

T12

4

T94

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T5

1

T3

2

T8

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T1

1

T5

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T1

1

T3

2

T94

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T1

1

T5

1

T3

3

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T1

2

T8

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T3

2

T122

1

T233

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T3

2

T8

1

T12

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T5

1

T3

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T3

2

T8

2

T37

2

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T1

1

T5

1

T3

5

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T3

3

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T1

10

T5

14

T3

36

auto[1]

1120

1

T1

10

T5

6

T3

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T1

3

T5

4

T3

12

from_0to1

544

1

T1

4

T5

4

T3

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T1

9

T5

9

T3

31

auto[1]

1143

1

T1

11

T5

11

T3

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T1

7

T5

11

T3

31

auto[1]

1124

1

T1

13

T5

9

T3

29

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T3

4

T10

1

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T3

1

T8

1

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

87

1

T5

2

T3

2

T8

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T5

1

T3

1

T8

3

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T5

2

T12

1

T233

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T3

3

T12

1

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T5

1

T3

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T1

2

T3

2

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T3

1

T12

2

T33

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T1

2

T3

1

T12

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T3

1

T12

1

T122

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T1

1

T5

1

T3

1

auto[1]

from_0to1

auto[0]

auto[0]

91

1

T5

1

T3

2

T8

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T1

2

T8

1

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T3

2

T8

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T3

1

T8

1

T233

1