Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	162717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124807

1

T1

241

T4

11

T5

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147220	1			T1	332		T4	8		T5	62
values[0x0]	69533	1			T1	131		T4	6		T5	38
values[0x1]	70771	1			T1	114		T4	2		T5	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155365

1

T1

287

T4

13

T5

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1139	1			T13	1		T2	3		T3	5
valid_sources[0x01]	2527	1			T1	3		T2	10		T15	1
valid_sources[0x02]	2503	1			T1	2		T2	1		T3	7
valid_sources[0x03]	1209	1			T1	1		T2	7		T3	2
valid_sources[0x04]	1141	1			T2	6		T3	7		T6	4
valid_sources[0x05]	921	1			T1	1		T2	10		T3	5
valid_sources[0x06]	2118	1			T13	3		T2	7		T15	1
valid_sources[0x07]	1696	1			T1	1		T2	3		T3	5
valid_sources[0x08]	920	1			T1	2		T2	2		T3	5
valid_sources[0x09]	883	1			T1	1		T13	1		T2	4
valid_sources[0x0a]	794	1			T1	4		T13	1		T2	9
valid_sources[0x0b]	846	1			T1	2		T2	7		T15	1
valid_sources[0x0c]	1299	1			T1	1		T2	4		T3	3
valid_sources[0x0d]	829	1			T1	3		T13	1		T2	10
valid_sources[0x0e]	1131	1			T1	3		T13	1		T2	2
valid_sources[0x0f]	1228	1			T1	1		T2	4		T15	1
valid_sources[0x10]	1466	1			T1	2		T13	2		T2	6
valid_sources[0x11]	1026	1			T2	2		T3	7		T6	1
valid_sources[0x12]	877	1			T1	5		T2	5		T6	1
valid_sources[0x13]	1061	1			T1	2		T2	5		T3	1
valid_sources[0x14]	886	1			T1	1		T2	1		T3	4
valid_sources[0x15]	1913	1			T1	2		T2	6		T16	2
valid_sources[0x16]	1047	1			T1	2		T2	7		T15	1
valid_sources[0x17]	1774	1			T1	8		T13	4		T2	9
valid_sources[0x18]	795	1			T1	1		T2	5		T3	3
valid_sources[0x19]	968	1			T13	1		T2	7		T3	6
valid_sources[0x1a]	1054	1			T1	5		T13	1		T2	6
valid_sources[0x1b]	1160	1			T1	5		T2	7		T3	9
valid_sources[0x1c]	895	1			T1	3		T2	8		T15	1
valid_sources[0x1d]	919	1			T1	5		T13	1		T2	3
valid_sources[0x1e]	855	1			T1	4		T13	1		T2	5
valid_sources[0x1f]	821	1			T1	4		T2	6		T3	5
valid_sources[0x20]	2358	1			T1	2		T4	3		T2	3
valid_sources[0x21]	1115	1			T1	1		T2	7		T15	1
valid_sources[0x22]	1802	1			T1	4		T2	12		T3	5
valid_sources[0x23]	777	1			T1	1		T2	3		T3	3
valid_sources[0x24]	1025	1			T1	4		T2	3		T3	10
valid_sources[0x25]	788	1			T2	3		T16	1		T6	3
valid_sources[0x26]	1567	1			T1	3		T2	5		T3	5
valid_sources[0x27]	1405	1			T2	3		T3	3		T10	6
valid_sources[0x28]	1317	1			T2	4		T3	6		T6	2
valid_sources[0x29]	1028	1			T1	3		T2	7		T3	8
valid_sources[0x2a]	926	1			T1	3		T13	1		T2	5
valid_sources[0x2b]	875	1			T1	1		T2	6		T3	3
valid_sources[0x2c]	915	1			T1	2		T13	1		T2	10
valid_sources[0x2d]	1087	1			T1	1		T2	7		T3	6
valid_sources[0x2e]	958	1			T1	3		T2	6		T3	4
valid_sources[0x2f]	930	1			T1	1		T2	11		T3	11
valid_sources[0x30]	988	1			T1	2		T2	7		T3	4
valid_sources[0x31]	1090	1			T1	2		T2	3		T3	3
valid_sources[0x32]	932	1			T1	1		T2	11		T3	1
valid_sources[0x33]	804	1			T1	2		T2	4		T15	1
valid_sources[0x34]	1084	1			T1	5		T2	4		T3	1
valid_sources[0x35]	1059	1			T1	2		T2	5		T3	11
valid_sources[0x36]	1012	1			T1	3		T2	3		T3	5
valid_sources[0x37]	930	1			T2	5		T3	3		T7	2
valid_sources[0x38]	845	1			T1	3		T13	1		T2	8
valid_sources[0x39]	902	1			T13	2		T2	8		T3	6
valid_sources[0x3a]	882	1			T1	4		T2	5		T15	1
valid_sources[0x3b]	1352	1			T1	3		T13	1		T2	7
valid_sources[0x3c]	1071	1			T1	1		T2	12		T3	7
valid_sources[0x3d]	881	1			T2	6		T3	3		T6	7
valid_sources[0x3e]	1053	1			T1	3		T2	6		T3	6
valid_sources[0x3f]	2680	1			T1	3		T13	2		T2	2
valid_sources[0x40]	1204	1			T1	1		T2	10		T16	1
valid_sources[0x41]	829	1			T2	6		T3	5		T6	5
valid_sources[0x42]	1173	1			T2	6		T3	4		T6	3
valid_sources[0x43]	1540	1			T1	5		T2	19		T16	1
valid_sources[0x44]	829	1			T1	2		T13	1		T2	3
valid_sources[0x45]	866	1			T1	2		T2	3		T3	2
valid_sources[0x46]	833	1			T1	1		T2	7		T3	2
valid_sources[0x47]	801	1			T3	8		T6	14		T8	1
valid_sources[0x48]	780	1			T1	2		T13	1		T2	3
valid_sources[0x49]	1574	1			T1	1		T2	5		T3	4
valid_sources[0x4a]	1450	1			T1	2		T2	5		T7	1
valid_sources[0x4b]	986	1			T1	2		T13	2		T2	3
valid_sources[0x4c]	761	1			T1	1		T2	2		T15	1
valid_sources[0x4d]	1333	1			T2	7		T15	1		T3	2
valid_sources[0x4e]	962	1			T1	2		T2	6		T3	8
valid_sources[0x4f]	1789	1			T2	1		T15	3		T3	7
valid_sources[0x50]	1066	1			T1	1		T2	13		T16	1
valid_sources[0x51]	985	1			T1	3		T13	1		T2	7
valid_sources[0x52]	955	1			T1	1		T13	1		T2	3
valid_sources[0x53]	1915	1			T1	1		T2	8		T3	4
valid_sources[0x54]	764	1			T1	2		T2	3		T15	1
valid_sources[0x55]	1419	1			T1	2		T2	1		T17	1
valid_sources[0x56]	822	1			T1	3		T2	8		T3	5
valid_sources[0x57]	968	1			T1	1		T2	1		T3	1
valid_sources[0x58]	1306	1			T1	2		T2	4		T3	1
valid_sources[0x59]	1006	1			T1	6		T2	6		T16	1
valid_sources[0x5a]	844	1			T1	3		T2	10		T17	1
valid_sources[0x5b]	781	1			T1	2		T13	1		T2	10
valid_sources[0x5c]	926	1			T1	4		T2	3		T15	2
valid_sources[0x5d]	825	1			T1	3		T2	2		T6	3
valid_sources[0x5e]	969	1			T1	2		T2	4		T3	1
valid_sources[0x5f]	938	1			T1	1		T2	3		T3	5
valid_sources[0x60]	975	1			T1	6		T13	1		T2	6
valid_sources[0x61]	990	1			T1	1		T14	2		T2	1
valid_sources[0x62]	913	1			T1	4		T2	3		T3	3
valid_sources[0x63]	1034	1			T1	2		T2	9		T3	2
valid_sources[0x64]	1069	1			T1	1		T2	4		T3	5
valid_sources[0x65]	809	1			T1	6		T2	5		T3	1
valid_sources[0x66]	945	1			T1	3		T2	8		T3	7
valid_sources[0x67]	1130	1			T1	1		T13	2		T2	7
valid_sources[0x68]	865	1			T1	4		T2	4		T15	1
valid_sources[0x69]	987	1			T1	2		T2	8		T3	1
valid_sources[0x6a]	1012	1			T1	3		T2	6		T15	1
valid_sources[0x6b]	1124	1			T2	11		T3	3		T6	4
valid_sources[0x6c]	963	1			T1	1		T2	2		T3	9
valid_sources[0x6d]	753	1			T2	7		T3	4		T6	5
valid_sources[0x6e]	1257	1			T1	5		T2	5		T17	2
valid_sources[0x6f]	1111	1			T1	6		T13	4		T2	1
valid_sources[0x70]	775	1			T1	4		T2	1		T3	2
valid_sources[0x71]	1092	1			T1	1		T13	1		T2	6
valid_sources[0x72]	1740	1			T1	3		T2	4		T3	1
valid_sources[0x73]	1026	1			T1	2		T2	6		T3	1
valid_sources[0x74]	870	1			T1	3		T2	9		T15	1
valid_sources[0x75]	1289	1			T1	1		T2	4		T3	5
valid_sources[0x76]	915	1			T1	2		T2	9		T15	2
valid_sources[0x77]	883	1			T1	2		T2	5		T16	1
valid_sources[0x78]	961	1			T2	11		T3	3		T6	6
valid_sources[0x79]	972	1			T1	2		T2	1		T3	2
valid_sources[0x7a]	881	1			T1	1		T2	8		T3	4
valid_sources[0x7b]	935	1			T1	2		T2	3		T16	2
valid_sources[0x7c]	1122	1			T1	1		T2	8		T3	5
valid_sources[0x7d]	2797	1			T2	5		T3	3		T6	8
valid_sources[0x7e]	1127	1			T1	3		T2	10		T3	2
valid_sources[0x7f]	1062	1			T2	2		T3	2		T6	5
valid_sources[0x80]	890	1			T1	3		T2	10		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66553

1

T1

159

T4

4

T5

38

values[0x0]

all_enables

biggest_size

34028

1

T1

61

T4

5

T5

13

values[0x1]

all_enables

biggest_size

24226

1

T1

21

T4

2

T5

1