Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1430528986	10025	0	0
auto_block_debounce_ctl_rd_A	1430528986	2136	0	0
auto_block_out_ctl_rd_A	1430528986	2583	0	0
com_det_ctl_0_rd_A	1430528986	4627	0	0
com_det_ctl_1_rd_A	1430528986	4800	0	0
com_det_ctl_2_rd_A	1430528986	4806	0	0
com_det_ctl_3_rd_A	1430528986	5080	0	0
com_out_ctl_0_rd_A	1430528986	5075	0	0
com_out_ctl_1_rd_A	1430528986	5137	0	0
com_out_ctl_2_rd_A	1430528986	5224	0	0
com_out_ctl_3_rd_A	1430528986	5183	0	0
com_pre_det_ctl_0_rd_A	1430528986	1723	0	0
com_pre_det_ctl_1_rd_A	1430528986	1719	0	0
com_pre_det_ctl_2_rd_A	1430528986	1719	0	0
com_pre_det_ctl_3_rd_A	1430528986	1776	0	0
com_pre_sel_ctl_0_rd_A	1430528986	5240	0	0
com_pre_sel_ctl_1_rd_A	1430528986	5179	0	0
com_pre_sel_ctl_2_rd_A	1430528986	5223	0	0
com_pre_sel_ctl_3_rd_A	1430528986	5089	0	0
com_sel_ctl_0_rd_A	1430528986	5286	0	0
com_sel_ctl_1_rd_A	1430528986	5062	0	0
com_sel_ctl_2_rd_A	1430528986	5156	0	0
com_sel_ctl_3_rd_A	1430528986	5162	0	0
ec_rst_ctl_rd_A	1430528986	2687	0	0
intr_enable_rd_A	1430528986	1968	0	0
key_intr_ctl_rd_A	1430528986	3595	0	0
key_intr_debounce_ctl_rd_A	1430528986	1676	0	0
key_invert_ctl_rd_A	1430528986	4790	0	0
pin_allowed_ctl_rd_A	1430528986	5181	0	0
pin_out_ctl_rd_A	1430528986	4194	0	0
pin_out_value_rd_A	1430528986	4074	0	0
regwen_rd_A	1430528986	1695	0	0
ulp_ac_debounce_ctl_rd_A	1430528986	1675	0	0
ulp_ctl_rd_A	1430528986	1815	0	0
ulp_lid_debounce_ctl_rd_A	1430528986	1838	0	0
ulp_pwrb_debounce_ctl_rd_A	1430528986	1705	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	10025	0	0
T1	160204	2	0	0
T2	170715	0	0	0
T3	234421	17	0	0
T4	73642	0	0	0
T5	60792	0	0	0
T7	0	5	0	0
T10	0	14	0	0
T11	0	11	0	0
T13	260943	0	0	0
T14	208754	0	0	0
T15	245463	0	0	0
T16	53818	0	0	0
T17	82695	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T37	0	18	0	0
T38	0	7	0	0
T76	0	3	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	2136	0	0
T10	541870	44	0	0
T11	453872	29	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T26	0	13	0	0
T34	0	21	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T95	0	4	0	0
T103	38561	0	0	0
T105	0	13	0	0
T195	0	26	0	0
T274	0	17	0	0
T275	0	7	0	0
T276	0	4	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	2583	0	0
T10	541870	41	0	0
T11	453872	37	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T26	0	3	0	0
T34	0	23	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T95	0	15	0	0
T103	38561	0	0	0
T105	0	9	0	0
T195	0	33	0	0
T274	0	9	0	0
T275	0	4	0	0
T276	0	13	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4627	0	0
T10	541870	24	0	0
T11	453872	23	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	85	0	0
T31	0	84	0	0
T34	0	24	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	58	0	0
T65	0	73	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	38	0	0
T203	0	68	0	0
T206	0	41	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4800	0	0
T10	541870	26	0	0
T11	453872	24	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	75	0	0
T31	0	84	0	0
T34	0	25	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	75	0	0
T65	0	66	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	41	0	0
T203	0	70	0	0
T206	0	61	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4806	0	0
T10	541870	19	0	0
T11	453872	21	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	63	0	0
T31	0	52	0	0
T34	0	22	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	81	0	0
T65	0	55	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	53	0	0
T203	0	85	0	0
T206	0	64	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5080	0	0
T10	541870	34	0	0
T11	453872	35	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	77	0	0
T31	0	59	0	0
T34	0	24	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	78	0	0
T65	0	63	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	51	0	0
T203	0	72	0	0
T206	0	79	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5075	0	0
T10	541870	25	0	0
T11	453872	41	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	74	0	0
T31	0	68	0	0
T34	0	15	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	75	0	0
T65	0	79	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	38	0	0
T203	0	89	0	0
T206	0	58	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5137	0	0
T10	541870	24	0	0
T11	453872	16	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	48	0	0
T31	0	86	0	0
T34	0	13	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	60	0	0
T65	0	85	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	57	0	0
T203	0	78	0	0
T206	0	89	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5224	0	0
T10	541870	22	0	0
T11	453872	15	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	52	0	0
T31	0	82	0	0
T34	0	13	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	79	0	0
T65	0	75	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	54	0	0
T203	0	52	0	0
T206	0	67	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5183	0	0
T10	541870	36	0	0
T11	453872	27	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	69	0	0
T31	0	68	0	0
T34	0	19	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	51	0	0
T65	0	52	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	42	0	0
T203	0	62	0	0
T206	0	73	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1723	0	0
T10	541870	18	0	0
T11	453872	25	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	20	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	11	0	0
T148	0	11	0	0
T153	0	20	0	0
T190	0	19	0	0
T195	0	24	0	0
T265	0	6	0	0
T277	0	21	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1719	0	0
T10	541870	14	0	0
T11	453872	16	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	10	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	13	0	0
T148	0	4	0	0
T153	0	21	0	0
T190	0	34	0	0
T195	0	24	0	0
T265	0	15	0	0
T277	0	10	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1719	0	0
T10	541870	29	0	0
T11	453872	23	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	18	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	12	0	0
T148	0	5	0	0
T153	0	11	0	0
T190	0	37	0	0
T195	0	31	0	0
T265	0	14	0	0
T277	0	9	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1776	0	0
T10	541870	21	0	0
T11	453872	21	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	15	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	9	0	0
T148	0	16	0	0
T153	0	27	0	0
T190	0	19	0	0
T195	0	17	0	0
T265	0	13	0	0
T277	0	24	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5240	0	0
T10	541870	16	0	0
T11	453872	12	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	93	0	0
T31	0	60	0	0
T34	0	13	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	73	0	0
T65	0	47	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	58	0	0
T203	0	86	0	0
T206	0	57	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5179	0	0
T10	541870	31	0	0
T11	453872	25	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	71	0	0
T31	0	83	0	0
T34	0	12	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	51	0	0
T65	0	60	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	22	0	0
T203	0	65	0	0
T206	0	55	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5223	0	0
T10	541870	21	0	0
T11	453872	18	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	75	0	0
T31	0	69	0	0
T34	0	28	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	85	0	0
T65	0	84	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	56	0	0
T203	0	82	0	0
T206	0	79	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5089	0	0
T10	541870	27	0	0
T11	453872	29	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	67	0	0
T31	0	76	0	0
T34	0	12	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	59	0	0
T65	0	63	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	25	0	0
T203	0	58	0	0
T206	0	96	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5286	0	0
T10	541870	22	0	0
T11	453872	38	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	60	0	0
T31	0	80	0	0
T34	0	5	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	78	0	0
T65	0	63	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	30	0	0
T203	0	69	0	0
T206	0	62	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5062	0	0
T10	541870	17	0	0
T11	453872	10	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	40	0	0
T31	0	61	0	0
T34	0	13	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	98	0	0
T65	0	67	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	58	0	0
T203	0	69	0	0
T206	0	67	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5156	0	0
T10	541870	31	0	0
T11	453872	25	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	69	0	0
T31	0	87	0	0
T34	0	7	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	85	0	0
T65	0	82	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	41	0	0
T203	0	77	0	0
T206	0	68	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5162	0	0
T10	541870	21	0	0
T11	453872	40	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T28	0	71	0	0
T31	0	42	0	0
T34	0	7	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T64	0	50	0	0
T65	0	100	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T202	0	35	0	0
T203	0	58	0	0
T206	0	69	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	2687	0	0
T3	234421	0	0	0
T6	372688	0	0	0
T7	200444	0	0	0
T8	233063	0	0	0
T10	0	29	0	0
T11	0	9	0	0
T17	82695	10	0	0
T23	0	3	0	0
T28	0	35	0	0
T31	0	15	0	0
T34	0	22	0	0
T46	209413	0	0	0
T47	34233	0	0	0
T48	259851	0	0	0
T49	210964	0	0	0
T50	293192	0	0	0
T202	0	9	0	0
T203	0	49	0	0
T206	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1968	0	0
T10	541870	49	0	0
T11	453872	39	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	25	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	25	0	0
T153	0	33	0	0
T190	0	21	0	0
T195	0	46	0	0
T277	0	13	0	0
T278	0	10	0	0
T279	0	10	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	3595	0	0
T8	233063	4	0	0
T9	108178	0	0	0
T10	541870	28	0	0
T11	453872	29	0	0
T22	235120	0	0	0
T23	228756	0	0	0
T34	0	26	0	0
T36	0	7	0	0
T51	174548	0	0	0
T52	49088	0	0	0
T68	0	1	0	0
T74	0	7	0	0
T103	38561	0	0	0
T105	0	22	0	0
T140	0	2	0	0
T156	0	2	0	0
T280	100426	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1676	0	0
T10	541870	23	0	0
T11	453872	8	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	14	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	9	0	0
T148	0	14	0	0
T153	0	23	0	0
T190	0	20	0	0
T195	0	12	0	0
T265	0	13	0	0
T277	0	28	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4790	0	0
T10	541870	132	0	0
T11	453872	16	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	68	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T57	0	48	0	0
T59	0	46	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	4	0	0
T188	0	64	0	0
T230	0	64	0	0
T281	0	52	0	0
T282	0	72	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	5181	0	0
T2	170715	0	0	0
T3	234421	0	0	0
T5	60792	75	0	0
T6	372688	0	0	0
T8	0	71	0	0
T10	0	109	0	0
T11	0	27	0	0
T13	260943	0	0	0
T14	208754	0	0	0
T15	245463	0	0	0
T16	53818	0	0	0
T17	82695	0	0	0
T34	0	86	0	0
T46	209413	0	0	0
T95	0	40	0	0
T105	0	104	0	0
T122	0	58	0	0
T144	0	84	0	0
T233	0	39	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4194	0	0
T2	170715	0	0	0
T3	234421	0	0	0
T5	60792	75	0	0
T6	372688	0	0	0
T8	0	67	0	0
T10	0	118	0	0
T11	0	28	0	0
T13	260943	0	0	0
T14	208754	0	0	0
T15	245463	0	0	0
T16	53818	0	0	0
T17	82695	0	0	0
T34	0	76	0	0
T46	209413	0	0	0
T95	0	22	0	0
T105	0	87	0	0
T122	0	63	0	0
T144	0	67	0	0
T233	0	53	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	4074	0	0
T2	170715	0	0	0
T3	234421	0	0	0
T5	60792	64	0	0
T6	372688	0	0	0
T8	0	58	0	0
T10	0	96	0	0
T11	0	13	0	0
T13	260943	0	0	0
T14	208754	0	0	0
T15	245463	0	0	0
T16	53818	0	0	0
T17	82695	0	0	0
T34	0	81	0	0
T46	209413	0	0	0
T95	0	53	0	0
T105	0	75	0	0
T122	0	73	0	0
T144	0	79	0	0
T233	0	43	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1695	0	0
T10	541870	14	0	0
T11	453872	35	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	6	0	0
T39	392570	0	0	0
T53	63939	0	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T148	0	6	0	0
T153	0	20	0	0
T190	0	28	0	0
T195	0	12	0	0
T265	0	16	0	0
T277	0	25	0	0
T283	0	4	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1675	0	0
T10	541870	19	0	0
T11	453872	35	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	29	0	0
T39	392570	0	0	0
T53	63939	7	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T74	0	4	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	8	0	0
T109	0	1	0	0
T110	0	16	0	0
T284	0	1	0	0
T285	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1815	0	0
T10	541870	26	0	0
T11	453872	25	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	9	0	0
T39	392570	0	0	0
T53	63939	22	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T74	0	8	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	21	0	0
T109	0	7	0	0
T110	0	7	0	0
T284	0	3	0	0
T285	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1838	0	0
T10	541870	17	0	0
T11	453872	26	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	14	0	0
T39	392570	0	0	0
T53	63939	11	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T74	0	3	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	18	0	0
T109	0	13	0	0
T110	0	13	0	0
T284	0	4	0	0
T285	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1430528986	1705	0	0
T10	541870	30	0	0
T11	453872	11	0	0
T12	462255	0	0	0
T23	228756	0	0	0
T34	0	16	0	0
T39	392570	0	0	0
T53	63939	13	0	0
T54	205627	0	0	0
T60	250779	0	0	0
T74	0	1	0	0
T94	245962	0	0	0
T103	38561	0	0	0
T105	0	17	0	0
T109	0	12	0	0
T110	0	5	0	0
T284	0	4	0	0
T285	0	2	0	0