Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T3,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T24,T3,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T3,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T3,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T46
0	1	Covered	T84,T34,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T46
0	1	Covered	T24,T3,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T3,T46
1	-	Covered	T24,T3,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T46
DetectSt	168	Covered	T24,T3,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T24,T3,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T3,T46
DebounceSt->IdleSt	163	Covered	T3,T54,T39
DetectSt->IdleSt	186	Covered	T84,T34,T92
DetectSt->StableSt	191	Covered	T24,T3,T46
IdleSt->DebounceSt	148	Covered	T24,T3,T46
StableSt->IdleSt	206	Covered	T24,T3,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T3,T46
0	1	Covered	T24,T3,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T39,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T46
DetectSt	-	-	-	-	1	-	-	Covered	T84,T34,T92
DetectSt	-	-	-	-	0	1	-	Covered	T24,T3,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T3,T46
StableSt	-	-	-	-	-	-	0	Covered	T24,T3,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	279	0	0
CntIncr_A	7461742	142413	0	0
CntNoWrap_A	7461742	6789966	0	0
DetectStDropOut_A	7461742	3	0	0
DetectedOut_A	7461742	843	0	0
DetectedPulseOut_A	7461742	126	0	0
DisabledIdleSt_A	7461742	6641230	0	0
DisabledNoDetection_A	7461742	6643498	0	0
EnterDebounceSt_A	7461742	158	0	0
EnterDetectSt_A	7461742	129	0	0
EnterStableSt_A	7461742	126	0	0
PulseIsPulse_A	7461742	126	0	0
StayInStableSt	7461742	717	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6879	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	279	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	7	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	4	0	0
T39	0	13	0	0
T46	0	4	0	0
T47	0	4	0	0
T48	0	4	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T84	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	142413	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	218	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	87	0	0
T39	0	2912	0	0
T46	0	79	0	0
T47	0	148	0	0
T48	0	82	0	0
T52	0	65	0	0
T53	0	42	0	0
T54	0	8	0	0
T84	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6789966	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	243	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	3	0	0
T34	0	1	0	0
T84	658	1	0	0
T92	0	1	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T102	4766	0	0	0
T103	4970	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T116	526	0	0	0
T117	526	0	0	0
T118	634	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	843	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	17	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	10	0	0
T39	0	31	0	0
T46	0	19	0	0
T47	0	9	0	0
T48	0	13	0	0
T52	0	2	0	0
T53	0	10	0	0
T84	0	8	0	0
T119	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	126	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	3	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6641230	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	75	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6643498	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	76	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	158	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	8	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T84	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	129	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	3	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T84	0	3	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	126	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	3	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	126	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	3	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	717	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	14	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	8	0	0
T39	0	25	0	0
T46	0	17	0	0
T47	0	7	0	0
T48	0	11	0	0
T52	0	1	0	0
T53	0	9	0	0
T84	0	6	0	0
T119	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6879	0	0
T1	15775	30	0	0
T4	492	7	0	0
T5	503	4	0	0
T6	491	7	0	0
T14	422	2	0	0
T15	526	5	0	0
T16	437	2	0	0
T17	0	4	0	0
T22	878	0	0	0
T23	506	4	0	0
T24	648	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	126	0	0
T1	15775	0	0	0
T2	1070	0	0	0
T3	0	3	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T24	648	2	0	0
T39	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T84	0	2	0	0
T119	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T61
0	1	Covered	T34,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T61
0	1	Unreachable
1	0	Covered	T2,T3,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T61
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T61
DebounceSt->IdleSt	163	Covered	T7,T63,T54
DetectSt->IdleSt	186	Covered	T34,T92,T93
DetectSt->StableSt	191	Covered	T2,T3,T61
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T61
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T61
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T63,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T34,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T61
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	170	0	0
CntIncr_A	7461742	232283	0	0
CntNoWrap_A	7461742	6790075	0	0
DetectStDropOut_A	7461742	8	0	0
DetectedOut_A	7461742	590286	0	0
DetectedPulseOut_A	7461742	58	0	0
DisabledIdleSt_A	7461742	5558045	0	0
DisabledNoDetection_A	7461742	5560367	0	0
EnterDebounceSt_A	7461742	104	0	0
EnterDetectSt_A	7461742	66	0	0
EnterStableSt_A	7461742	58	0	0
PulseIsPulse_A	7461742	58	0	0
StayInStableSt	7461742	590228	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6879	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_sticky_sva.StableStDropOut_A	7461742	134083	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	170	0	0
T2	1070	2	0	0
T3	260383	2	0	0
T7	1891	9	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	4	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	232283	0	0
T2	1070	24	0	0
T3	260383	55561	0	0
T7	1891	873	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	155	0	0
T54	0	37	0	0
T60	628	0	0	0
T61	0	58	0	0
T62	0	51	0	0
T63	0	35	0	0
T64	0	63	0	0
T65	0	13	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790075	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	8	0	0
T34	27900	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T123	0	2	0	0
T124	0	2	0	0
T125	489	0	0	0
T126	506	0	0	0
T127	524	0	0	0
T128	19800	0	0	0
T129	758	0	0	0
T130	6960	0	0	0
T131	656	0	0	0
T132	435	0	0	0
T133	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	590286	0	0
T2	1070	126	0	0
T3	260383	175895	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	118	0	0
T39	0	362	0	0
T52	0	400	0	0
T60	628	0	0	0
T61	0	259	0	0
T62	0	162	0	0
T64	0	307	0	0
T65	0	33	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	58	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5558045	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5560367	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	104	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	9	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	66	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	2	0	0
T39	0	2	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	58	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	58	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	590228	0	0
T2	1070	125	0	0
T3	260383	175894	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	117	0	0
T39	0	360	0	0
T52	0	398	0	0
T60	628	0	0	0
T61	0	258	0	0
T62	0	161	0	0
T64	0	306	0	0
T65	0	32	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6879	0	0
T1	15775	30	0	0
T4	492	7	0	0
T5	503	4	0	0
T6	491	7	0	0
T14	422	2	0	0
T15	526	5	0	0
T16	437	2	0	0
T17	0	4	0	0
T22	878	0	0	0
T23	506	4	0	0
T24	648	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	134083	0	0
T2	1070	361	0	0
T3	260383	53	0	0
T7	1891	0	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	267	0	0
T39	0	494	0	0
T52	0	145	0	0
T60	628	0	0	0
T61	0	532	0	0
T62	0	248	0	0
T64	0	400	0	0
T65	0	300	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T87	0	459	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T7,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Unreachable
1	0	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T65,T54
DetectSt->IdleSt	186	Covered	T7,T90,T91
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T65,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	190	0	0
CntIncr_A	7461742	97595	0	0
CntNoWrap_A	7461742	6790055	0	0
DetectStDropOut_A	7461742	16	0	0
DetectedOut_A	7461742	189420	0	0
DetectedPulseOut_A	7461742	56	0	0
DisabledIdleSt_A	7461742	5558045	0	0
DisabledNoDetection_A	7461742	5560367	0	0
EnterDebounceSt_A	7461742	118	0	0
EnterDetectSt_A	7461742	72	0	0
EnterStableSt_A	7461742	56	0	0
PulseIsPulse_A	7461742	56	0	0
StayInStableSt	7461742	189364	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_sticky_sva.StableStDropOut_A	7461742	829803	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	190	0	0
T2	1070	2	0	0
T3	260383	2	0	0
T7	1891	10	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	4	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	3	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	97595	0	0
T2	1070	60	0	0
T3	260383	60	0	0
T7	1891	426	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	95	0	0
T54	0	38	0	0
T60	628	0	0	0
T61	0	100	0	0
T62	0	82	0	0
T63	0	72	0	0
T64	0	52	0	0
T65	0	147	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790055	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	16	0	0
T7	1891	3	0	0
T8	16720	0	0	0
T9	56461	0	0	0
T45	43473	0	0	0
T46	677	0	0	0
T60	628	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T70	493	0	0	0
T75	529	0	0	0
T90	0	4	0	0
T91	0	1	0	0
T123	0	3	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	189420	0	0
T2	1070	366	0	0
T3	260383	132	0	0
T7	1891	216	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	73	0	0
T52	0	230	0	0
T60	628	0	0	0
T61	0	649	0	0
T62	0	299	0	0
T63	0	8	0	0
T64	0	345	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	179732	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	56	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	1	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	1	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5558045	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5560367	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	118	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	6	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	3	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	72	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	4	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	1	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	56	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	1	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	1	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	56	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	1	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	1	0	0
T52	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	189364	0	0
T2	1070	365	0	0
T3	260383	131	0	0
T7	1891	215	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	72	0	0
T52	0	228	0	0
T60	628	0	0	0
T61	0	648	0	0
T62	0	298	0	0
T63	0	7	0	0
T64	0	344	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	179730	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	829803	0	0
T2	1070	92	0	0
T3	260383	231321	0	0
T7	1891	286	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	312	0	0
T52	0	371	0	0
T60	628	0	0	0
T61	0	83	0	0
T62	0	86	0	0
T63	0	30	0	0
T64	0	364	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	149	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T39,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Unreachable
1	0	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T52,T64,T65
DetectSt->IdleSt	186	Covered	T39,T87,T88
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T64,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T39,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	186	0	0
CntIncr_A	7461742	72135	0	0
CntNoWrap_A	7461742	6790059	0	0
DetectStDropOut_A	7461742	15	0	0
DetectedOut_A	7461742	68649	0	0
DetectedPulseOut_A	7461742	50	0	0
DisabledIdleSt_A	7461742	5558045	0	0
DisabledNoDetection_A	7461742	5560367	0	0
EnterDebounceSt_A	7461742	121	0	0
EnterDetectSt_A	7461742	65	0	0
EnterStableSt_A	7461742	50	0	0
PulseIsPulse_A	7461742	50	0	0
StayInStableSt	7461742	68599	0	0
gen_high_event_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_sticky_sva.StableStDropOut_A	7461742	833997	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	186	0	0
T2	1070	2	0	0
T3	260383	2	0	0
T7	1891	4	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	3	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	5	0	0
T65	0	4	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	72135	0	0
T2	1070	57	0	0
T3	260383	55	0	0
T7	1891	90	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	138	0	0
T54	0	38	0	0
T60	628	0	0	0
T61	0	97	0	0
T62	0	29	0	0
T63	0	80	0	0
T64	0	290	0	0
T65	0	216	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790059	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	15	0	0
T37	718	0	0	0
T39	25953	1	0	0
T84	658	0	0	0
T87	0	1	0	0
T88	0	3	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	68649	0	0
T2	1070	233	0	0
T3	260383	183	0	0
T7	1891	528	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	432	0	0
T52	0	418	0	0
T60	628	0	0	0
T61	0	393	0	0
T62	0	107	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	113	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	50	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	2	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T52	0	1	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5558045	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5560367	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	121	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	2	0	0
T8	16720	0	0	0
T21	436	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	5	0	0
T65	0	3	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	65	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	2	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	3	0	0
T52	0	1	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	50	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	2	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T52	0	1	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	50	0	0
T2	1070	1	0	0
T3	260383	1	0	0
T7	1891	2	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T52	0	1	0	0
T60	628	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	68599	0	0
T2	1070	232	0	0
T3	260383	182	0	0
T7	1891	526	0	0
T8	16720	0	0	0
T21	436	0	0	0
T34	0	375	0	0
T39	0	430	0	0
T52	0	417	0	0
T60	628	0	0	0
T61	0	392	0	0
T62	0	106	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T114	0	165	0	0
T121	0	111	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	833997	0	0
T2	1070	237	0	0
T3	260383	231290	0	0
T7	1891	656	0	0
T8	16720	0	0	0
T21	436	0	0	0
T39	0	223	0	0
T52	0	64	0	0
T60	628	0	0	0
T61	0	360	0	0
T62	0	342	0	0
T63	0	40	0	0
T65	0	60	0	0
T66	415	0	0	0
T67	507	0	0	0
T68	427	0	0	0
T69	489	0	0	0
T121	0	271660	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T35,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T54,T35,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T54,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T54,T35,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T43,T44
0	1	Covered	T44
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T43,T44
0	1	Covered	T35,T43,T143
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T43,T44
1	-	Covered	T35,T43,T143

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T54,T35,T43
DetectSt	168	Covered	T35,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T43,T44
DebounceSt->IdleSt	163	Covered	T54
DetectSt->IdleSt	186	Covered	T44
DetectSt->StableSt	191	Covered	T35,T43,T44
IdleSt->DebounceSt	148	Covered	T54,T35,T43
StableSt->IdleSt	206	Covered	T35,T43,T143

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T54,T35,T43
0	1	Covered	T54,T35,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T54,T35,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T43,T44
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T54,T35,T43
DetectSt	-	-	-	-	1	-	-	Covered	T44
DetectSt	-	-	-	-	0	1	-	Covered	T35,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T43,T143
StableSt	-	-	-	-	-	-	0	Covered	T35,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	57	0	0
CntIncr_A	7461742	32808	0	0
CntNoWrap_A	7461742	6790188	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	45711	0	0
DetectedPulseOut_A	7461742	27	0	0
DisabledIdleSt_A	7461742	6212509	0	0
DisabledNoDetection_A	7461742	6214787	0	0
EnterDebounceSt_A	7461742	29	0	0
EnterDetectSt_A	7461742	28	0	0
EnterStableSt_A	7461742	27	0	0
PulseIsPulse_A	7461742	27	0	0
StayInStableSt	7461742	45670	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	57	0	0
T35	0	2	0	0
T39	25953	0	0	0
T43	0	6	0	0
T44	0	4	0	0
T54	6033	1	0	0
T89	0	2	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T143	0	4	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	32808	0	0
T35	0	60	0	0
T39	25953	0	0	0
T43	0	241	0	0
T44	0	22	0	0
T54	6033	17	0	0
T89	0	88	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T143	0	142	0	0
T144	0	17	0	0
T145	0	31232	0	0
T146	0	66	0	0
T147	0	12	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790188	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1	0	0
T44	1754	1	0	0
T143	988	0	0	0
T153	669	0	0	0
T154	891	0	0	0
T155	402	0	0	0
T156	493	0	0	0
T157	33325	0	0	0
T158	822	0	0	0
T159	670	0	0	0
T160	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	45711	0	0
T35	780	99	0	0
T43	20851	382	0	0
T44	0	55	0	0
T89	0	187	0	0
T143	0	42	0	0
T144	0	73	0	0
T145	0	43563	0	0
T146	0	42	0	0
T147	0	121	0	0
T161	0	67	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	27	0	0
T35	780	1	0	0
T43	20851	3	0	0
T44	0	1	0	0
T89	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	2	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6212509	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6214787	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	29	0	0
T35	0	1	0	0
T39	25953	0	0	0
T43	0	3	0	0
T44	0	2	0	0
T54	6033	1	0	0
T89	0	1	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	28	0	0
T35	780	1	0	0
T43	20851	3	0	0
T44	0	2	0	0
T89	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	2	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	27	0	0
T35	780	1	0	0
T43	20851	3	0	0
T44	0	1	0	0
T89	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	2	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	27	0	0
T35	780	1	0	0
T43	20851	3	0	0
T44	0	1	0	0
T89	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T161	0	2	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	45670	0	0
T35	780	98	0	0
T43	20851	377	0	0
T44	0	53	0	0
T89	0	185	0	0
T143	0	40	0	0
T144	0	72	0	0
T145	0	43561	0	0
T146	0	41	0	0
T147	0	119	0	0
T161	0	64	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	12	0	0
T35	780	1	0	0
T43	20851	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T162	639	0	0	0
T163	425	0	0	0
T164	629	0	0	0
T165	507	0	0	0
T166	561	0	0	0
T167	501	0	0	0
T168	522	0	0	0
T169	499	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T42,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T36,T42,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T42,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T42,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T36,T42,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T42,T39
0	1	Covered	T85,T174,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T42,T39
0	1	Covered	T36,T34,T40
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T42,T39
1	-	Covered	T36,T34,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T42,T54
DetectSt	168	Covered	T36,T42,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T42,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T42,T39
DebounceSt->IdleSt	163	Covered	T54,T34,T154
DetectSt->IdleSt	186	Covered	T85,T174,T175
DetectSt->StableSt	191	Covered	T36,T42,T39
IdleSt->DebounceSt	148	Covered	T36,T42,T54
StableSt->IdleSt	206	Covered	T36,T39,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T42,T54
0	1	Covered	T36,T42,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T42,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T42,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T42,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T154,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T42,T54
DetectSt	-	-	-	-	1	-	-	Covered	T85,T174,T175
DetectSt	-	-	-	-	0	1	-	Covered	T36,T42,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T34,T40
StableSt	-	-	-	-	-	-	0	Covered	T36,T42,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	119	0	0
CntIncr_A	7461742	219666	0	0
CntNoWrap_A	7461742	6790126	0	0
DetectStDropOut_A	7461742	3	0	0
DetectedOut_A	7461742	92695	0	0
DetectedPulseOut_A	7461742	53	0	0
DisabledIdleSt_A	7461742	6157990	0	0
DisabledNoDetection_A	7461742	6160262	0	0
EnterDebounceSt_A	7461742	63	0	0
EnterDetectSt_A	7461742	56	0	0
EnterStableSt_A	7461742	53	0	0
PulseIsPulse_A	7461742	53	0	0
StayInStableSt	7461742	92617	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	2771	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	119	0	0
T33	690	0	0	0
T34	0	5	0	0
T35	0	4	0	0
T36	1072	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	490	2	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	2	0	0
T177	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	219666	0	0
T33	690	0	0	0
T34	0	138	0	0
T35	0	120	0	0
T36	1072	158	0	0
T39	0	96	0	0
T40	0	98	0	0
T41	0	68	0	0
T42	490	17	0	0
T54	0	16	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	88	0	0
T177	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790126	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	3	0	0
T85	891	1	0	0
T88	3912	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T178	69136	0	0	0
T179	438	0	0	0
T180	461	0	0	0
T181	13054	0	0	0
T182	502	0	0	0
T183	438	0	0	0
T184	522	0	0	0
T185	498	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	92695	0	0
T33	690	0	0	0
T34	0	256	0	0
T35	0	88	0	0
T36	1072	209	0	0
T39	0	174	0	0
T40	0	199	0	0
T41	0	104	0	0
T42	490	40	0	0
T43	0	73	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	43	0	0
T177	0	217	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T33	690	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1072	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	490	1	0	0
T43	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T177	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6157990	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6160262	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	63	0	0
T33	690	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T36	1072	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	490	1	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T177	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	56	0	0
T33	690	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1072	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	490	1	0	0
T43	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T177	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T33	690	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1072	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	490	1	0	0
T43	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T177	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T33	690	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1072	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	490	1	0	0
T43	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T177	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	92617	0	0
T33	690	0	0	0
T34	0	253	0	0
T35	0	85	0	0
T36	1072	207	0	0
T39	0	172	0	0
T40	0	197	0	0
T41	0	101	0	0
T42	490	38	0	0
T43	0	72	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	41	0	0
T177	0	214	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2771	0	0
T1	15775	0	0	0
T4	492	4	0	0
T5	503	6	0	0
T6	491	4	0	0
T14	422	1	0	0
T15	526	5	0	0
T16	437	2	0	0
T17	0	6	0	0
T21	0	2	0	0
T22	878	0	0	0
T23	506	6	0	0
T24	648	0	0	0
T66	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	27	0	0
T33	690	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	1072	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	490	0	0	0
T43	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T85	0	1	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T154	0	1	0	0
T177	0	1	0	0
T186	0	2	0	0