Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T1,T20,T3
1	1	Covered	T1,T20,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T11,T47,T80
1	0	Covered	T54,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T54,T59,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T3,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T3,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T24,T3,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T3,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T46
0	1	Covered	T84,T34,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T46
0	1	Covered	T24,T3,T46
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T3,T46
1	-	Covered	T24,T3,T46

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T20,T8
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T8,T10,T82
1	0	Covered	T8,T10,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
1	0	Covered	T10,T54,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T8
1	-	Covered	T1,T20,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T39,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Unreachable
1	0	Covered	T2,T3,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T31,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T31,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T31,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T31,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T36
0	1	Covered	T34,T44,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T36
0	1	Covered	T29,T31,T36
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T31,T36
1	-	Covered	T29,T31,T36

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T7,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Unreachable
1	0	Covered	T2,T3,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T61
0	1	Covered	T34,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T61
0	1	Unreachable
1	0	Covered	T2,T3,T61

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T46
DetectSt	168	Covered	T24,T3,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T24,T3,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T3,T46
DebounceSt->IdleSt	163	Covered	T3,T54,T39
DetectSt->IdleSt	186	Covered	T7,T84,T34
DetectSt->StableSt	191	Covered	T24,T3,T46
IdleSt->DebounceSt	148	Covered	T24,T3,T46
StableSt->IdleSt	206	Covered	T24,T3,T46

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T46
0	1	Covered	T24,T3,T46
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T39,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T46
DetectSt	-	-	-	-	1	-	-	Covered	T7,T84,T34
DetectSt	-	-	-	-	0	1	-	Covered	T24,T3,T46
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T24,T3,T46
StableSt	-	-	-	-	-	-	0	Covered	T24,T3,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T20,T2
0	1	Covered	T1,T20,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T64,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T2
DetectSt	-	-	-	-	1	-	-	Covered	T8,T10,T82
DetectSt	-	-	-	-	0	1	-	Covered	T1,T20,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T20,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T20,T2
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	194005292	16311	0	0
CntIncr_A	194005292	3217149	0	0
CntNoWrap_A	194005292	176530059	0	0
DetectStDropOut_A	194005292	1766	0	0
DetectedOut_A	194005292	2633739	0	0
DetectedPulseOut_A	194005292	5477	0	0
DisabledIdleSt_A	194005292	159830346	0	0
DisabledNoDetection_A	194005292	159886679	0	0
EnterDebounceSt_A	194005292	8483	0	0
EnterDetectSt_A	194005292	7852	0	0
EnterStableSt_A	194005292	5477	0	0
PulseIsPulse_A	194005292	5477	0	0
StayInStableSt	194005292	2627544	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	67155678	51590	0	0
gen_high_event_sva.HighLevelEvent_A	37308710	33962835	0	0
gen_high_level_sva.HighLevelEvent_A	126849614	115473639	0	0
gen_low_level_sva.LowLevelEvent_A	67155678	61133103	0	0
gen_not_sticky_sva.StableStDropOut_A	171620066	4527	0	0
gen_sticky_sva.StableStDropOut_A	22385226	1797883	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	16311	0	0
T1	141975	24	0	0
T2	9630	0	0	0
T3	0	9	0	0
T8	0	14	0	0
T9	0	4	0	0
T10	0	12	0	0
T11	0	2	0	0
T12	0	20	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	48	0	0
T21	3488	0	0	0
T24	648	4	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	13	0	0
T42	490	0	0	0
T46	0	4	0	0
T47	0	6	0	0
T48	0	4	0	0
T49	0	72	0	0
T51	0	36	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	6	0	0
T81	475	3	0	0
T84	0	6	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	3217149	0	0
T1	141975	675	0	0
T2	9630	0	0	0
T3	0	243	0	0
T8	0	523	0	0
T9	0	304	0	0
T10	0	384	0	0
T11	0	193	0	0
T12	0	420	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	1224	0	0
T21	3488	0	0	0
T24	648	87	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	2912	0	0
T42	490	0	0	0
T46	0	79	0	0
T47	0	293	0	0
T48	0	82	0	0
T49	0	3252	0	0
T51	0	908	0	0
T52	0	65	0	0
T53	0	42	0	0
T54	0	8	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	309	0	0
T81	475	41	0	0
T84	0	136	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	176530059	0	0
T1	410150	399406	0	0
T4	12792	2366	0	0
T5	13078	2652	0	0
T6	12766	2340	0	0
T14	10972	546	0	0
T15	13676	3250	0	0
T16	11362	936	0	0
T22	22828	12402	0	0
T23	13156	2730	0	0
T24	16848	6418	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	1766	0	0
T8	16720	4	0	0
T9	56461	0	0	0
T10	10206	0	0	0
T34	0	1	0	0
T37	718	0	0	0
T43	0	1	0	0
T45	43473	0	0	0
T46	677	0	0	0
T54	0	1	0	0
T70	493	0	0	0
T75	529	0	0	0
T76	529	0	0	0
T84	1316	1	0	0
T92	0	1	0	0
T98	0	4	0	0
T99	11997	4	0	0
T100	31488	3	0	0
T101	11032	11	0	0
T102	9532	2	0	0
T103	4970	25	0	0
T104	0	6	0	0
T105	0	15	0	0
T106	0	14	0	0
T107	0	1	0	0
T108	0	4	0	0
T109	0	2	0	0
T110	0	6	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	1643	0	0	0
T114	3228	0	0	0
T115	1012	0	0	0
T116	1052	0	0	0
T117	526	0	0	0
T118	634	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	2633739	0	0
T1	141975	1063	0	0
T2	9630	0	0	0
T3	0	20	0	0
T9	0	38	0	0
T10	0	1732	0	0
T11	0	17	0	0
T12	0	354	0	0
T13	0	1229	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	241	0	0
T21	3488	0	0	0
T24	648	10	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	31	0	0
T42	490	0	0	0
T46	0	19	0	0
T47	0	55	0	0
T48	0	13	0	0
T49	0	2354	0	0
T51	0	1125	0	0
T52	0	2	0	0
T53	0	10	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	214	0	0
T81	475	0	0	0
T82	0	3314	0	0
T84	0	8	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	5477	0	0
T1	141975	12	0	0
T2	9630	0	0	0
T3	0	4	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	6	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	36	0	0
T51	0	18	0	0
T52	0	1	0	0
T53	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	0	0	0
T82	0	33	0	0
T84	0	2	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	159830346	0	0
T1	410150	379075	0	0
T4	12792	2366	0	0
T5	13078	2652	0	0
T6	12766	2340	0	0
T14	10972	546	0	0
T15	13676	3250	0	0
T16	11362	936	0	0
T22	22828	12402	0	0
T23	13156	2730	0	0
T24	16848	6250	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	159886679	0	0
T1	410150	379187	0	0
T4	12792	2392	0	0
T5	13078	2678	0	0
T6	12766	2366	0	0
T14	10972	572	0	0
T15	13676	3276	0	0
T16	11362	962	0	0
T22	22828	12428	0	0
T23	13156	2756	0	0
T24	16848	6276	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	8483	0	0
T1	141975	12	0	0
T2	9630	0	0	0
T3	0	5	0	0
T8	0	7	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	0	10	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	8	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	36	0	0
T51	0	18	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	2	0	0
T84	0	3	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	7852	0	0
T1	141975	12	0	0
T2	9630	0	0	0
T3	0	4	0	0
T8	0	7	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	0	10	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	6	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	36	0	0
T51	0	18	0	0
T52	0	1	0	0
T53	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	0	0	0
T82	0	8	0	0
T84	0	3	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	5477	0	0
T1	141975	12	0	0
T2	9630	0	0	0
T3	0	4	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	6	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	36	0	0
T51	0	18	0	0
T52	0	1	0	0
T53	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	0	0	0
T82	0	33	0	0
T84	0	2	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	5477	0	0
T1	141975	12	0	0
T2	9630	0	0	0
T3	0	4	0	0
T9	0	2	0	0
T10	0	6	0	0
T11	0	1	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	6	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	36	0	0
T51	0	18	0	0
T52	0	1	0	0
T53	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	0	0	0
T82	0	33	0	0
T84	0	2	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	194005292	2627544	0	0
T1	141975	1049	0	0
T2	9630	0	0	0
T3	0	16	0	0
T9	0	36	0	0
T10	0	1725	0	0
T11	0	16	0	0
T12	0	344	0	0
T13	0	1208	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	217	0	0
T21	3488	0	0	0
T24	648	8	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	25	0	0
T42	490	0	0	0
T46	0	17	0	0
T47	0	52	0	0
T48	0	11	0	0
T49	0	2310	0	0
T51	0	1105	0	0
T52	0	1	0	0
T53	0	9	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	211	0	0
T81	475	0	0	0
T82	0	3273	0	0
T84	0	6	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67155678	51590	0	0
T1	141975	198	0	0
T4	4428	67	0	0
T5	4527	43	0	0
T6	4419	52	0	0
T14	3798	18	0	0
T15	4734	41	0	0
T16	3933	21	0	0
T17	0	53	0	0
T18	0	4	0	0
T20	0	105	0	0
T21	0	2	0	0
T22	7902	3	0	0
T23	4554	40	0	0
T24	5832	9	0	0
T66	0	1	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37308710	33962835	0	0
T1	78875	76855	0	0
T4	2460	460	0	0
T5	2515	515	0	0
T6	2455	455	0	0
T14	2110	110	0	0
T15	2630	630	0	0
T16	2185	185	0	0
T22	4390	2390	0	0
T23	2530	530	0	0
T24	3240	1240	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126849614	115473639	0	0
T1	268175	261307	0	0
T4	8364	1564	0	0
T5	8551	1751	0	0
T6	8347	1547	0	0
T14	7174	374	0	0
T15	8942	2142	0	0
T16	7429	629	0	0
T22	14926	8126	0	0
T23	8602	1802	0	0
T24	11016	4216	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67155678	61133103	0	0
T1	141975	138339	0	0
T4	4428	828	0	0
T5	4527	927	0	0
T6	4419	819	0	0
T14	3798	198	0	0
T15	4734	1134	0	0
T16	3933	333	0	0
T22	7902	4302	0	0
T23	4554	954	0	0
T24	5832	2232	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171620066	4527	0	0
T1	141975	10	0	0
T2	9630	0	0	0
T3	0	4	0	0
T9	0	2	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	3798	0	0	0
T15	4734	0	0	0
T16	3933	0	0	0
T17	4437	0	0	0
T18	5112	0	0	0
T19	5805	0	0	0
T20	63585	24	0	0
T21	3488	0	0	0
T24	648	2	0	0
T33	690	0	0	0
T36	1072	0	0	0
T39	0	6	0	0
T42	490	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T51	0	16	0	0
T52	0	1	0	0
T53	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T80	0	3	0	0
T81	475	0	0	0
T82	0	25	0	0
T84	0	2	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T119	0	1	0	0
T120	0	22	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22385226	1797883	0	0
T2	3210	690	0	0
T3	781149	462664	0	0
T7	5673	942	0	0
T8	50160	0	0	0
T21	1308	0	0	0
T34	0	267	0	0
T39	0	1029	0	0
T52	0	580	0	0
T60	1884	0	0	0
T61	0	975	0	0
T62	0	676	0	0
T63	0	70	0	0
T64	0	764	0	0
T65	0	360	0	0
T66	1245	0	0	0
T67	1521	0	0	0
T68	1281	0	0	0
T69	1467	0	0	0
T87	0	459	0	0
T121	0	271809	0	0