Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T31,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T31,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T31,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T31,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T36
0	1	Covered	T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T36
0	1	Covered	T31,T36,T34
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T31,T36
1	-	Covered	T31,T36,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T31,T36
DetectSt	168	Covered	T29,T31,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T31,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T31,T36
DebounceSt->IdleSt	163	Covered	T54
DetectSt->IdleSt	186	Covered	T187
DetectSt->StableSt	191	Covered	T29,T31,T36
IdleSt->DebounceSt	148	Covered	T29,T31,T36
StableSt->IdleSt	206	Covered	T31,T36,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T31,T36
0	1	Covered	T29,T31,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T31,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T31,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T31,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T31,T36
DetectSt	-	-	-	-	1	-	-	Covered	T187
DetectSt	-	-	-	-	0	1	-	Covered	T29,T31,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T36,T34
StableSt	-	-	-	-	-	-	0	Covered	T29,T31,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	91	0	0
CntIncr_A	7461742	191678	0	0
CntNoWrap_A	7461742	6790154	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	55649	0	0
DetectedPulseOut_A	7461742	44	0	0
DisabledIdleSt_A	7461742	5724765	0	0
DisabledNoDetection_A	7461742	5727036	0	0
EnterDebounceSt_A	7461742	46	0	0
EnterDetectSt_A	7461742	45	0	0
EnterStableSt_A	7461742	44	0	0
PulseIsPulse_A	7461742	44	0	0
StayInStableSt	7461742	55586	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	91	0	0
T29	992	2	0	0
T31	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	4	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T122	0	2	0	0
T143	0	4	0	0
T186	0	4	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	191678	0	0
T29	992	100	0	0
T31	0	192	0	0
T34	0	31	0	0
T35	0	60	0	0
T36	0	158	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	17	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T122	0	88	0	0
T143	0	142	0	0
T186	0	41374	0	0
T188	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790154	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1	0	0
T187	874	1	0	0
T189	402	0	0	0
T190	408	0	0	0
T191	523	0	0	0
T192	14861	0	0	0
T193	17469	0	0	0
T194	418	0	0	0
T195	806	0	0	0
T196	497	0	0	0
T197	775	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	55649	0	0
T29	992	38	0	0
T31	0	251	0	0
T34	0	1	0	0
T35	0	203	0	0
T36	0	227	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	136	0	0
T122	0	44	0	0
T143	0	156	0	0
T186	0	32866	0	0
T188	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	44	0	0
T29	992	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	2	0	0
T122	0	1	0	0
T143	0	2	0	0
T186	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5724765	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5727036	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	46	0	0
T29	992	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T122	0	1	0	0
T143	0	2	0	0
T186	0	2	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	45	0	0
T29	992	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	2	0	0
T122	0	1	0	0
T143	0	2	0	0
T186	0	2	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	44	0	0
T29	992	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	2	0	0
T122	0	1	0	0
T143	0	2	0	0
T186	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	44	0	0
T29	992	1	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	2	0	0
T122	0	1	0	0
T143	0	2	0	0
T186	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	55586	0	0
T29	992	36	0	0
T31	0	248	0	0
T35	0	201	0	0
T36	0	224	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	134	0	0
T122	0	42	0	0
T143	0	154	0	0
T178	0	80	0	0
T186	0	32864	0	0
T188	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	24	0	0
T31	1348	1	0	0
T34	0	1	0	0
T36	1072	1	0	0
T62	2167	0	0	0
T63	658	0	0	0
T73	493	0	0	0
T74	493	0	0	0
T85	0	2	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	498	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T30,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T30,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T42
0	1	Covered	T29,T41,T38
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T30,T42
1	-	Covered	T29,T41,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T30,T42
DetectSt	168	Covered	T29,T30,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T30,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T30,T42
DebounceSt->IdleSt	163	Covered	T54,T78,T41
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T29,T30,T42
IdleSt->DebounceSt	148	Covered	T29,T30,T42
StableSt->IdleSt	206	Covered	T29,T40,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T30,T42
0	1	Covered	T29,T30,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T30,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T30,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T41,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T30,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T29,T30,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T41,T38
StableSt	-	-	-	-	-	-	0	Covered	T29,T30,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	116	0	0
CntIncr_A	7461742	265327	0	0
CntNoWrap_A	7461742	6790129	0	0
DetectStDropOut_A	7461742	0	0	0
DetectedOut_A	7461742	54047	0	0
DetectedPulseOut_A	7461742	53	0	0
DisabledIdleSt_A	7461742	6080097	0	0
DisabledNoDetection_A	7461742	6082370	0	0
EnterDebounceSt_A	7461742	63	0	0
EnterDetectSt_A	7461742	53	0	0
EnterStableSt_A	7461742	53	0	0
PulseIsPulse_A	7461742	53	0	0
StayInStableSt	7461742	53967	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	3175	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	116	0	0
T29	992	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T38	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	265327	0	0
T29	992	100	0	0
T30	0	54786	0	0
T33	0	49	0	0
T38	0	38856	0	0
T40	0	49	0	0
T41	0	102	0	0
T42	0	17	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	16	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	79	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790129	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	54047	0	0
T29	992	63	0	0
T30	0	38	0	0
T33	0	181	0	0
T38	0	13386	0	0
T40	0	111	0	0
T41	0	59	0	0
T42	0	63	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	39	0	0
T202	0	43	0	0
T203	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T29	992	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6080097	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6082370	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	63	0	0
T29	992	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T29	992	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T29	992	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53	0	0
T29	992	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	53967	0	0
T29	992	62	0	0
T30	0	36	0	0
T33	0	179	0	0
T38	0	13384	0	0
T40	0	109	0	0
T41	0	56	0	0
T42	0	61	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T201	0	37	0	0
T202	0	42	0	0
T203	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	3175	0	0
T1	15775	0	0	0
T4	492	7	0	0
T5	503	7	0	0
T6	491	4	0	0
T14	422	2	0	0
T15	526	4	0	0
T16	437	4	0	0
T17	0	5	0	0
T18	0	4	0	0
T22	878	3	0	0
T23	506	3	0	0
T24	648	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	25	0	0
T29	992	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T144	0	1	0	0
T146	0	1	0	0
T154	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T202	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T33,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T33,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T33,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T33,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T33,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T33,T39
0	1	Covered	T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T33,T39
0	1	Covered	T29,T33,T201
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T33,T39
1	-	Covered	T29,T33,T201

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T33,T54
DetectSt	168	Covered	T29,T33,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T33,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T33,T39
DebounceSt->IdleSt	163	Covered	T54,T205
DetectSt->IdleSt	186	Covered	T89
DetectSt->StableSt	191	Covered	T29,T33,T39
IdleSt->DebounceSt	148	Covered	T29,T33,T54
StableSt->IdleSt	206	Covered	T29,T33,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T33,T54
0	1	Covered	T29,T33,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T33,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T33,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T33,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T205
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T33,T54
DetectSt	-	-	-	-	1	-	-	Covered	T89
DetectSt	-	-	-	-	0	1	-	Covered	T29,T33,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T33,T201
StableSt	-	-	-	-	-	-	0	Covered	T29,T33,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	132	0	0
CntIncr_A	7461742	206392	0	0
CntNoWrap_A	7461742	6790113	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	319266	0	0
DetectedPulseOut_A	7461742	64	0	0
DisabledIdleSt_A	7461742	6087116	0	0
DisabledNoDetection_A	7461742	6089386	0	0
EnterDebounceSt_A	7461742	67	0	0
EnterDetectSt_A	7461742	65	0	0
EnterStableSt_A	7461742	64	0	0
PulseIsPulse_A	7461742	64	0	0
StayInStableSt	7461742	319176	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	132	0	0
T29	992	2	0	0
T33	0	4	0	0
T39	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	2	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	4	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	2	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	206392	0	0
T29	992	100	0	0
T33	0	98	0	0
T39	0	96	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	16	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	79	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	160	0	0
T201	0	72	0	0
T202	0	39	0	0
T203	0	63226	0	0
T206	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790113	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1	0	0
T89	54054	1	0	0
T198	9374	0	0	0
T199	21334	0	0	0
T207	442	0	0	0
T208	403	0	0	0
T209	411	0	0	0
T210	5721	0	0	0
T211	687	0	0	0
T212	12725	0	0	0
T213	7494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	319266	0	0
T29	992	61	0	0
T33	0	82	0	0
T39	0	41	0	0
T43	0	25	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	45	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	144	0	0
T201	0	81	0	0
T202	0	120	0	0
T203	0	191072	0	0
T206	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	64	0	0
T29	992	1	0	0
T33	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6087116	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6089386	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	67	0	0
T29	992	1	0	0
T33	0	2	0	0
T39	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	65	0	0
T29	992	1	0	0
T33	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	64	0	0
T29	992	1	0	0
T33	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	64	0	0
T29	992	1	0	0
T33	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	1	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	319176	0	0
T29	992	60	0	0
T33	0	79	0	0
T39	0	39	0	0
T43	0	24	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T78	0	43	0	0
T79	433	0	0	0
T80	13277	0	0	0
T177	0	142	0	0
T201	0	79	0	0
T202	0	119	0	0
T203	0	191070	0	0
T206	0	58	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	37	0	0
T29	992	1	0	0
T33	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T85	0	1	0	0
T143	0	1	0	0
T177	0	2	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T36,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T36,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T36,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T36,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T40,T41
0	1	Covered	T214
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T40,T41
0	1	Covered	T40,T201,T186
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T40,T41
1	-	Covered	T40,T201,T186

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T36,T54
DetectSt	168	Covered	T29,T40,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T40,T41
DebounceSt->IdleSt	163	Covered	T36,T54,T144
DetectSt->IdleSt	186	Covered	T214
DetectSt->StableSt	191	Covered	T29,T40,T41
IdleSt->DebounceSt	148	Covered	T29,T36,T54
StableSt->IdleSt	206	Covered	T40,T41,T201

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T36,T54
0	1	Covered	T29,T36,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T40,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T36,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T144,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T36,T54
DetectSt	-	-	-	-	1	-	-	Covered	T214
DetectSt	-	-	-	-	0	1	-	Covered	T29,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T201,T186
StableSt	-	-	-	-	-	-	0	Covered	T29,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	73	0	0
CntIncr_A	7461742	88635	0	0
CntNoWrap_A	7461742	6790172	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	50521	0	0
DetectedPulseOut_A	7461742	33	0	0
DisabledIdleSt_A	7461742	6257305	0	0
DisabledNoDetection_A	7461742	6259577	0	0
EnterDebounceSt_A	7461742	39	0	0
EnterDetectSt_A	7461742	34	0	0
EnterStableSt_A	7461742	33	0	0
PulseIsPulse_A	7461742	33	0	0
StayInStableSt	7461742	50470	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6545	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	73	0	0
T29	992	2	0	0
T36	0	1	0	0
T40	0	4	0	0
T41	0	2	0	0
T43	0	2	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T186	0	4	0	0
T201	0	4	0	0
T202	0	2	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	88635	0	0
T29	992	100	0	0
T36	0	79	0	0
T40	0	98	0	0
T41	0	34	0	0
T43	0	29	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	17	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T186	0	41374	0	0
T201	0	72	0	0
T202	0	39	0	0
T206	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790172	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1	0	0
T214	8156	1	0	0
T216	501	0	0	0
T217	783	0	0	0
T218	808	0	0	0
T219	422	0	0	0
T220	4158	0	0	0
T221	920	0	0	0
T222	504	0	0	0
T223	858	0	0	0
T224	1051	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	50521	0	0
T29	992	39	0	0
T40	0	53	0	0
T41	0	82	0	0
T43	0	48	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	39	0	0
T178	0	64	0	0
T186	0	48611	0	0
T201	0	123	0	0
T202	0	102	0	0
T206	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	33	0	0
T29	992	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6257305	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6259577	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	39	0	0
T29	992	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T54	0	1	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	34	0	0
T29	992	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	33	0	0
T29	992	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	33	0	0
T29	992	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	1	0	0
T178	0	1	0	0
T186	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	50470	0	0
T29	992	37	0	0
T40	0	50	0	0
T41	0	80	0	0
T43	0	46	0	0
T48	732	0	0	0
T49	25159	0	0	0
T50	13220	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T57	803	0	0	0
T58	897	0	0	0
T79	433	0	0	0
T80	13277	0	0	0
T89	0	38	0	0
T178	0	63	0	0
T186	0	48608	0	0
T201	0	120	0	0
T202	0	100	0	0
T206	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6545	0	0
T1	15775	27	0	0
T4	492	8	0	0
T5	503	4	0	0
T6	491	7	0	0
T14	422	3	0	0
T15	526	3	0	0
T16	437	3	0	0
T17	0	10	0	0
T20	0	28	0	0
T22	878	0	0	0
T23	506	4	0	0
T24	648	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	14	0	0
T40	15839	1	0	0
T41	56843	0	0	0
T87	1779	0	0	0
T89	0	1	0	0
T107	22412	0	0	0
T170	0	1	0	0
T178	0	1	0	0
T186	0	1	0	0
T201	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	34898	0	0	0
T230	490	0	0	0
T231	505	0	0	0
T232	2326	0	0	0
T233	417	0	0	0
T234	429	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T39,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T54,T39,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T39,T34,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T54,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T54,T39,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T34,T41
0	1	Covered	T89,T235
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T34,T41
0	1	Covered	T39,T34,T41
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T34,T41
1	-	Covered	T39,T34,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T54,T39,T34
DetectSt	168	Covered	T39,T34,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T39,T34,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T34,T41
DebounceSt->IdleSt	163	Covered	T54,T44,T236
DetectSt->IdleSt	186	Covered	T89,T235
DetectSt->StableSt	191	Covered	T39,T34,T41
IdleSt->DebounceSt	148	Covered	T54,T39,T34
StableSt->IdleSt	206	Covered	T39,T34,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T54,T39,T34
0	1	Covered	T54,T39,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T34,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T54,T39,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T34,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T54,T39,T34
DetectSt	-	-	-	-	1	-	-	Covered	T89,T235
DetectSt	-	-	-	-	0	1	-	Covered	T39,T34,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T34,T41
StableSt	-	-	-	-	-	-	0	Covered	T39,T34,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	117	0	0
CntIncr_A	7461742	338607	0	0
CntNoWrap_A	7461742	6790128	0	0
DetectStDropOut_A	7461742	2	0	0
DetectedOut_A	7461742	85822	0	0
DetectedPulseOut_A	7461742	55	0	0
DisabledIdleSt_A	7461742	5671491	0	0
DisabledNoDetection_A	7461742	5673764	0	0
EnterDebounceSt_A	7461742	61	0	0
EnterDetectSt_A	7461742	57	0	0
EnterStableSt_A	7461742	55	0	0
PulseIsPulse_A	7461742	55	0	0
StayInStableSt	7461742	85745	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	117	0	0
T34	0	4	0	0
T38	0	2	0	0
T39	25953	2	0	0
T41	0	4	0	0
T43	0	2	0	0
T44	0	3	0	0
T54	6033	1	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T122	0	4	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0
T201	0	4	0	0
T203	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	338607	0	0
T34	0	62	0	0
T38	0	12952	0	0
T39	25953	96	0	0
T41	0	68	0	0
T43	0	29	0	0
T44	0	22	0	0
T54	6033	16	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T122	0	176	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0
T201	0	72	0	0
T203	0	126452	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790128	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2	0	0
T89	54054	1	0	0
T198	9374	0	0	0
T199	21334	0	0	0
T207	442	0	0	0
T208	403	0	0	0
T209	411	0	0	0
T210	5721	0	0	0
T211	687	0	0	0
T212	12725	0	0	0
T213	7494	0	0	0
T235	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	85822	0	0
T34	0	84	0	0
T37	718	0	0	0
T38	0	6036	0	0
T39	25953	35	0	0
T41	0	54	0	0
T43	0	102	0	0
T44	0	55	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	84	0	0
T154	0	151	0	0
T201	0	227	0	0
T203	0	1189	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	55	0	0
T34	0	2	0	0
T37	718	0	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	2	0	0
T154	0	1	0	0
T201	0	2	0	0
T203	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5671491	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	5673764	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	61	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T54	6033	1	0	0
T99	11997	0	0	0
T113	1643	0	0	0
T121	544288	0	0	0
T122	0	2	0	0
T148	665	0	0	0
T149	508	0	0	0
T150	37579	0	0	0
T151	563	0	0	0
T152	490	0	0	0
T201	0	2	0	0
T203	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	57	0	0
T34	0	2	0	0
T37	718	0	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	2	0	0
T154	0	1	0	0
T201	0	2	0	0
T203	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	55	0	0
T34	0	2	0	0
T37	718	0	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	2	0	0
T154	0	1	0	0
T201	0	2	0	0
T203	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	55	0	0
T34	0	2	0	0
T37	718	0	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	2	0	0
T154	0	1	0	0
T201	0	2	0	0
T203	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	85745	0	0
T34	0	81	0	0
T37	718	0	0	0
T38	0	6035	0	0
T39	25953	34	0	0
T41	0	52	0	0
T43	0	100	0	0
T44	0	53	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	81	0	0
T154	0	150	0	0
T201	0	224	0	0
T203	0	1186	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	32	0	0
T34	0	1	0	0
T37	718	0	0	0
T38	0	1	0	0
T39	25953	1	0	0
T41	0	2	0	0
T84	658	0	0	0
T99	11997	0	0	0
T100	15744	0	0	0
T101	5516	0	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T121	544288	0	0	0
T122	0	1	0	0
T143	0	1	0	0
T154	0	1	0	0
T186	0	1	0	0
T201	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T54,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T36,T54,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T39,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T54,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T36,T54,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T39,T34
0	1	Covered	T226
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T39,T34
0	1	Covered	T34,T201,T203
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T39,T34
1	-	Covered	T34,T201,T203

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T54,T39
DetectSt	168	Covered	T36,T39,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T39,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T39,T34
DebounceSt->IdleSt	163	Covered	T54,T37,T122
DetectSt->IdleSt	186	Covered	T226
DetectSt->StableSt	191	Covered	T36,T39,T34
IdleSt->DebounceSt	148	Covered	T36,T54,T39
StableSt->IdleSt	206	Covered	T39,T34,T201

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T54,T39
0	1	Covered	T36,T54,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T39,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T54,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T39,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T122,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T54,T39
DetectSt	-	-	-	-	1	-	-	Covered	T226
DetectSt	-	-	-	-	0	1	-	Covered	T36,T39,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T201,T203
StableSt	-	-	-	-	-	-	0	Covered	T36,T39,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	60	0	0
CntIncr_A	7461742	132727	0	0
CntNoWrap_A	7461742	6790185	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	84443	0	0
DetectedPulseOut_A	7461742	26	0	0
DisabledIdleSt_A	7461742	6074243	0	0
DisabledNoDetection_A	7461742	6076518	0	0
EnterDebounceSt_A	7461742	33	0	0
EnterDetectSt_A	7461742	27	0	0
EnterStableSt_A	7461742	26	0	0
PulseIsPulse_A	7461742	26	0	0
StayInStableSt	7461742	84404	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6057	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	60	0	0
T33	690	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1072	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	490	0	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T201	0	2	0	0
T203	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	132727	0	0
T33	690	0	0	0
T34	0	76	0	0
T35	0	120	0	0
T36	1072	79	0	0
T37	0	26	0	0
T38	0	12952	0	0
T39	0	96	0	0
T42	490	0	0	0
T54	0	17	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	88	0	0
T201	0	36	0	0
T203	0	63226	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6790185	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1	0	0
T136	324518	0	0	0
T226	939	1	0	0
T238	503	0	0	0
T239	8444	0	0	0
T240	527	0	0	0
T241	427	0	0	0
T242	23205	0	0	0
T243	523	0	0	0
T244	418	0	0	0
T245	735	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	84443	0	0
T33	690	0	0	0
T34	0	159	0	0
T36	1072	190	0	0
T38	0	19104	0	0
T39	0	42	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	52	0	0
T170	0	96	0	0
T201	0	14	0	0
T203	0	63429	0	0
T235	0	42	0	0
T246	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	26	0	0
T33	690	0	0	0
T34	0	1	0	0
T36	1072	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	1	0	0
T170	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6074243	0	0
T1	15775	15366	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6076518	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	33	0	0
T33	690	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	1072	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	490	0	0	0
T54	0	1	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T122	0	1	0	0
T201	0	1	0	0
T203	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	27	0	0
T33	690	0	0	0
T34	0	1	0	0
T36	1072	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	1	0	0
T201	0	1	0	0
T203	0	1	0	0
T226	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	26	0	0
T33	690	0	0	0
T34	0	1	0	0
T36	1072	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	1	0	0
T170	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	26	0	0
T33	690	0	0	0
T34	0	1	0	0
T36	1072	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	1	0	0
T170	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	84404	0	0
T33	690	0	0	0
T34	0	158	0	0
T36	1072	188	0	0
T38	0	19102	0	0
T39	0	40	0	0
T42	490	0	0	0
T63	658	0	0	0
T64	10608	0	0	0
T81	475	0	0	0
T94	422	0	0	0
T95	505	0	0	0
T96	1339	0	0	0
T97	422	0	0	0
T146	0	50	0	0
T170	0	94	0	0
T201	0	13	0	0
T203	0	63428	0	0
T235	0	40	0	0
T246	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6057	0	0
T1	15775	26	0	0
T4	492	8	0	0
T5	503	4	0	0
T6	491	6	0	0
T14	422	3	0	0
T15	526	5	0	0
T16	437	2	0	0
T17	0	8	0	0
T20	0	25	0	0
T22	878	0	0	0
T23	506	5	0	0
T24	648	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	12	0	0
T34	27900	1	0	0
T125	489	0	0	0
T126	506	0	0	0
T127	524	0	0	0
T128	19800	0	0	0
T129	758	0	0	0
T130	6960	0	0	0
T131	656	0	0	0
T132	435	0	0	0
T133	426	0	0	0
T170	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T205	0	2	0	0
T214	0	1	0	0
T237	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0