Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T36,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T31,T36,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T36,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T36,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T36,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T36,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T36,T42
0	1	Covered	T31,T33,T39
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T36,T42
1	-	Covered	T31,T33,T39

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T36,T42
DetectSt	168	Covered	T31,T36,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T31,T36,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T36,T42
DebounceSt->IdleSt	163	Covered	T54,T78,T44
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T36,T42
IdleSt->DebounceSt	148	Covered	T31,T36,T42
StableSt->IdleSt	206	Covered	T31,T33,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T36,T42
0	1	Covered	T31,T36,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T31,T36,T42
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T36,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T36,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T44,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T36,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T36,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T33,T39
StableSt	-	-	-	-	-	-	0	Covered	T31,T36,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	112	0	0
CntIncr_A	7461742	120386	0	0
CntNoWrap_A	7461742	6790133	0	0
DetectStDropOut_A	7461742	0	0	0
DetectedOut_A	7461742	12520	0	0
DetectedPulseOut_A	7461742	54	0	0
DisabledIdleSt_A	7461742	6514528	0	0
DisabledNoDetection_A	7461742	6516795	0	0
EnterDebounceSt_A	7461742	60	0	0
EnterDetectSt_A	7461742	54	0	0
EnterStableSt_A	7461742	54	0	0
PulseIsPulse_A	7461742	54	0	0
StayInStableSt	7461742	12443	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	30	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	112
T31	1348	2
T33	0	2
T34	0	2
T36	1072	2
T39	0	2
T40	0	4
T42	0	2
T54	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T188	0	2
T200	498	0

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	120386
T31	1348	96
T33	0	49
T34	0	31
T36	1072	79
T39	0	96
T40	0	98
T42	0	17
T54	0	17
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	79
T94	422	0
T95	505	0
T96	1339	0
T188	0	75
T200	498	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790133
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	12520
T31	1348	43
T33	0	93
T34	0	90
T36	1072	456
T38	0	6035
T39	0	34
T40	0	195
T42	0	41
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	40
T188	0	159
T200	498	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	54
T31	1348	1
T33	0	1
T34	0	1
T36	1072	1
T38	0	1
T39	0	1
T40	0	2
T42	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	1
T188	0	1
T200	498	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	6514528
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	6516795
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	60
T31	1348	1
T33	0	1
T34	0	1
T36	1072	1
T39	0	1
T40	0	2
T42	0	1
T54	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T188	0	1
T200	498	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	54
T31	1348	1
T33	0	1
T34	0	1
T36	1072	1
T38	0	1
T39	0	1
T40	0	2
T42	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	1
T188	0	1
T200	498	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	54
T31	1348	1
T33	0	1
T34	0	1
T36	1072	1
T38	0	1
T39	0	1
T40	0	2
T42	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	1
T188	0	1
T200	498	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	54
T31	1348	1
T33	0	1
T34	0	1
T36	1072	1
T38	0	1
T39	0	1
T40	0	2
T42	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	1
T188	0	1
T200	498	0

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	12443
T31	1348	42
T33	0	92
T34	0	89
T36	1072	454
T38	0	6034
T39	0	33
T40	0	192
T42	0	39
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T177	0	39
T188	0	157
T200	498	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	30
T31	1348	1
T33	0	1
T34	0	1
T36	1072	0
T38	0	1
T39	0	1
T40	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T122	0	1
T154	0	1
T177	0	1
T200	498	0
T202	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T54,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T33,T54,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T39,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T33,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T33,T54,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T39,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T39,T37
0	1	Covered	T37,T40,T41
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T39,T37
1	-	Covered	T37,T40,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T54,T39
DetectSt	168	Covered	T33,T39,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T33,T39,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T39,T37
DebounceSt->IdleSt	163	Covered	T54,T147,T250
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T33,T39,T37
IdleSt->DebounceSt	148	Covered	T33,T54,T39
StableSt->IdleSt	206	Covered	T39,T37,T34

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T54,T39
0	1	Covered	T33,T54,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T39,T37
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T54,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T39,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T54,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T33,T39,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T40,T41
StableSt	-	-	-	-	-	-	0	Covered	T33,T39,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	83	0	0
CntIncr_A	7461742	22922	0	0
CntNoWrap_A	7461742	6790162	0	0
DetectStDropOut_A	7461742	0	0	0
DetectedOut_A	7461742	56449	0	0
DetectedPulseOut_A	7461742	40	0	0
DisabledIdleSt_A	7461742	6599348	0	0
DisabledNoDetection_A	7461742	6601619	0	0
EnterDebounceSt_A	7461742	43	0	0
EnterDetectSt_A	7461742	40	0	0
EnterStableSt_A	7461742	40	0	0
PulseIsPulse_A	7461742	40	0	0
StayInStableSt	7461742	56386	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6138	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	16	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	83
T33	690	2
T34	0	2
T37	0	4
T39	0	2
T40	0	2
T41	0	2
T44	0	2
T53	670	0
T54	0	1
T81	475	0
T82	24441	0
T120	14213	0
T143	0	4
T202	0	2
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	22922
T33	690	49
T34	0	31
T37	0	52
T39	0	96
T40	0	49
T41	0	34
T44	0	11
T53	670	0
T54	0	16
T81	475	0
T82	24441	0
T120	14213	0
T143	0	142
T202	0	39
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790162
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	56449
T33	690	39
T34	0	42
T37	0	92
T39	0	42
T40	0	106
T41	0	41
T44	0	174
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	83
T186	0	53557
T202	0	44
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	40
T33	690	1
T34	0	1
T37	0	2
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	2
T186	0	1
T202	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	6599348
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	6601619
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	43
T33	690	1
T34	0	1
T37	0	2
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T53	670	0
T54	0	1
T81	475	0
T82	24441	0
T120	14213	0
T143	0	2
T202	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	40
T33	690	1
T34	0	1
T37	0	2
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	2
T186	0	1
T202	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	40
T33	690	1
T34	0	1
T37	0	2
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	2
T186	0	1
T202	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	40
T33	690	1
T34	0	1
T37	0	2
T39	0	1
T40	0	1
T41	0	1
T44	0	1
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	2
T186	0	1
T202	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	56386
T33	690	37
T34	0	40
T37	0	89
T39	0	40
T40	0	105
T41	0	40
T44	0	172
T53	670	0
T81	475	0
T82	24441	0
T120	14213	0
T143	0	81
T186	0	53555
T202	0	42
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7461742	6138
T1	15775	27
T4	492	8
T5	503	5
T6	491	5
T14	422	1
T15	526	5
T16	437	2
T17	0	6
T20	0	25
T22	878	0
T23	506	6
T24	648	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	16
T37	718	1
T40	0	1
T41	0	1
T84	658	0
T100	15744	0
T101	5516	0
T102	4766	0
T114	1614	0
T115	506	0
T116	526	0
T117	526	0
T118	634	0
T123	0	1
T143	0	2
T176	0	1
T204	0	1
T227	0	1
T256	0	1
T257	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T29,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T29,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T4,T5,T6
1	1	Covered	T29,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T258
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T31,T34,T40
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T30,T31
1	-	Covered	T31,T34,T40

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T30,T31
DetectSt	168	Covered	T29,T30,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T29,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T30,T31
DebounceSt->IdleSt	163	Covered	T54,T236,T173
DetectSt->IdleSt	186	Covered	T258
DetectSt->StableSt	191	Covered	T29,T30,T31
IdleSt->DebounceSt	148	Covered	T29,T30,T31
StableSt->IdleSt	206	Covered	T31,T39,T34

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T30,T31
0	1	Covered	T29,T30,T31
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T173
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T258
DetectSt	-	-	-	-	0	1	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T34,T40
StableSt	-	-	-	-	-	-	0	Covered	T29,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	138	0	0
CntIncr_A	7461742	215293	0	0
CntNoWrap_A	7461742	6790107	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	346513	0	0
DetectedPulseOut_A	7461742	67	0	0
DisabledIdleSt_A	7461742	5988236	0	0
DisabledNoDetection_A	7461742	5990504	0	0
EnterDebounceSt_A	7461742	71	0	0
EnterDetectSt_A	7461742	68	0	0
EnterStableSt_A	7461742	67	0	0
PulseIsPulse_A	7461742	67	0	0
StayInStableSt	7461742	346420	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	40	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	138
T29	992	2
T30	0	2
T31	0	2
T34	0	2
T38	0	4
T39	0	2
T40	0	2
T48	732	0
T49	25159	0
T50	13220	0
T54	0	1
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	2
T201	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	215293
T29	992	100
T30	0	54786
T31	0	96
T34	0	31
T38	0	25904
T39	0	96
T40	0	49
T48	732	0
T49	25159	0
T50	13220	0
T54	0	17
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	80
T201	0	36

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790107
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7461742	1
T246	27241	0
T258	868	1
T259	5314	0
T260	489	0
T261	66661	0
T262	502	0
T263	600	0
T264	684	0
T265	402	0
T266	21332	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	346513
T29	992	39
T30	0	60340
T31	0	96
T34	0	43
T38	0	12145
T39	0	173
T40	0	192
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	43
T201	0	238
T206	0	59

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	67
T29	992	1
T30	0	1
T31	0	1
T34	0	1
T38	0	2
T39	0	1
T40	0	1
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	1
T201	0	1
T206	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	5988236
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	5990504
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	71
T29	992	1
T30	0	1
T31	0	1
T34	0	1
T38	0	2
T39	0	1
T40	0	1
T48	732	0
T49	25159	0
T50	13220	0
T54	0	1
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	1
T201	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	68
T29	992	1
T30	0	1
T31	0	1
T34	0	1
T38	0	2
T39	0	1
T40	0	1
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	1
T201	0	1
T206	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	67
T29	992	1
T30	0	1
T31	0	1
T34	0	1
T38	0	2
T39	0	1
T40	0	1
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	1
T201	0	1
T206	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	67
T29	992	1
T30	0	1
T31	0	1
T34	0	1
T38	0	2
T39	0	1
T40	0	1
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	1
T201	0	1
T206	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	346420
T29	992	37
T30	0	60338
T31	0	95
T34	0	42
T38	0	12143
T39	0	171
T40	0	191
T48	732	0
T49	25159	0
T50	13220	0
T55	524	0
T56	426	0
T57	803	0
T58	897	0
T79	433	0
T80	13277	0
T177	0	42
T201	0	237
T206	0	58

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	40
T31	1348	1
T34	0	1
T36	1072	0
T38	0	2
T40	0	1
T43	0	1
T44	0	2
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T94	422	0
T95	505	0
T96	1339	0
T154	0	2
T177	0	1
T200	498	0
T201	0	1
T206	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T54,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T36,T54,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T36,T33
1	0	Covered	T4,T5,T6
1	1	Covered	T36,T54,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T257
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T37,T38,T85
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T38
1	-	Covered	T37,T38,T85

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T54,T37
DetectSt	168	Covered	T36,T37,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T37,T38
DebounceSt->IdleSt	163	Covered	T54,T37,T267
DetectSt->IdleSt	186	Covered	T257
DetectSt->StableSt	191	Covered	T36,T37,T38
IdleSt->DebounceSt	148	Covered	T36,T54,T37
StableSt->IdleSt	206	Covered	T37,T38,T206

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T54,T37
0	1	Covered	T36,T54,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T54,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T267
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T54,T37
DetectSt	-	-	-	-	1	-	-	Covered	T257
DetectSt	-	-	-	-	0	1	-	Covered	T36,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T38,T85
StableSt	-	-	-	-	-	-	0	Covered	T36,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	65	0	0
CntIncr_A	7461742	59328	0	0
CntNoWrap_A	7461742	6790180	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	2163	0	0
DetectedPulseOut_A	7461742	30	0	0
DisabledIdleSt_A	7461742	5852466	0	0
DisabledNoDetection_A	7461742	5854736	0	0
EnterDebounceSt_A	7461742	34	0	0
EnterDetectSt_A	7461742	31	0	0
EnterStableSt_A	7461742	30	0	0
PulseIsPulse_A	7461742	30	0	0
StayInStableSt	7461742	2117	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6267	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	13	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	65
T33	690	0
T36	1072	2
T37	0	3
T38	0	4
T42	490	0
T54	0	1
T63	658	0
T64	10608	0
T81	475	0
T85	0	4
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	2
T145	0	2
T206	0	2
T246	0	2
T258	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	59328
T33	690	0
T36	1072	79
T37	0	52
T38	0	25904
T42	490	0
T54	0	16
T63	658	0
T64	10608	0
T81	475	0
T85	0	106
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	17
T145	0	31232
T206	0	99
T246	0	46
T258	0	47

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790180
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7461742	1
T141	795	0
T257	3133	1
T268	4403	0
T269	522	0
T270	503	0
T271	29286	0
T272	34764	0
T273	443	0
T274	813	0
T275	2068	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	2163
T33	690	0
T36	1072	191
T37	0	20
T38	0	82
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	136
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	65
T145	0	42
T206	0	41
T246	0	87
T250	0	40
T258	0	363

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	30
T33	690	0
T36	1072	1
T37	0	1
T38	0	2
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	2
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	1
T145	0	1
T206	0	1
T246	0	1
T250	0	1
T258	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	5852466
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	5854736
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	34
T33	690	0
T36	1072	1
T37	0	2
T38	0	2
T42	490	0
T54	0	1
T63	658	0
T64	10608	0
T81	475	0
T85	0	2
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	1
T145	0	1
T206	0	1
T246	0	1
T258	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	31
T33	690	0
T36	1072	1
T37	0	1
T38	0	2
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	2
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	1
T145	0	1
T206	0	1
T246	0	1
T250	0	1
T258	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	30
T33	690	0
T36	1072	1
T37	0	1
T38	0	2
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	2
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	1
T145	0	1
T206	0	1
T246	0	1
T250	0	1
T258	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	30
T33	690	0
T36	1072	1
T37	0	1
T38	0	2
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	2
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	1
T145	0	1
T206	0	1
T246	0	1
T250	0	1
T258	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	2117
T33	690	0
T36	1072	189
T37	0	19
T38	0	79
T42	490	0
T63	658	0
T64	10608	0
T81	475	0
T85	0	133
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T144	0	64
T145	0	40
T206	0	39
T246	0	85
T250	0	38
T258	0	361

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7461742	6267
T1	15775	28
T4	492	11
T5	503	5
T6	491	5
T14	422	2
T15	526	4
T16	437	2
T17	0	6
T20	0	27
T22	878	0
T23	506	4
T24	648	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	13
T37	718	1
T38	0	1
T84	658	0
T85	0	1
T100	15744	0
T101	5516	0
T102	4766	0
T114	1614	0
T115	506	0
T116	526	0
T117	526	0
T118	634	0
T144	0	1
T161	0	1
T214	0	1
T223	0	1
T227	0	1
T228	0	1
T247	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T36,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T31,T36,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T36,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T36,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T31,T36,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T36,T39
0	1	Covered	T34,T89,T215
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T36,T39
0	1	Covered	T36,T40,T41
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T36,T39
1	-	Covered	T36,T40,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T36,T54
DetectSt	168	Covered	T31,T36,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T31,T36,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T36,T39
DebounceSt->IdleSt	163	Covered	T54,T41,T44
DetectSt->IdleSt	186	Covered	T34,T89,T215
DetectSt->StableSt	191	Covered	T31,T36,T39
IdleSt->DebounceSt	148	Covered	T31,T36,T54
StableSt->IdleSt	206	Covered	T36,T39,T40

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T36,T54
0	1	Covered	T31,T36,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T31,T36,T39
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T36,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T36,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T44,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T36,T54
DetectSt	-	-	-	-	1	-	-	Covered	T34,T89,T215
DetectSt	-	-	-	-	0	1	-	Covered	T31,T36,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T40,T41
StableSt	-	-	-	-	-	-	0	Covered	T31,T36,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	144	0	0
CntIncr_A	7461742	217937	0	0
CntNoWrap_A	7461742	6790101	0	0
DetectStDropOut_A	7461742	3	0	0
DetectedOut_A	7461742	241741	0	0
DetectedPulseOut_A	7461742	65	0	0
DisabledIdleSt_A	7461742	5871600	0	0
DisabledNoDetection_A	7461742	5873864	0	0
EnterDebounceSt_A	7461742	76	0	0
EnterDetectSt_A	7461742	68	0	0
EnterStableSt_A	7461742	65	0	0
PulseIsPulse_A	7461742	65	0	0
StayInStableSt	7461742	241643	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	31	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	144
T31	1348	2
T34	0	2
T36	1072	4
T37	0	2
T38	0	2
T39	0	2
T40	0	2
T41	0	5
T54	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	2
T94	422	0
T95	505	0
T96	1339	0
T200	498	0

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	217937
T31	1348	96
T34	0	31
T36	1072	158
T37	0	26
T38	0	12952
T39	0	96
T40	0	49
T41	0	102
T54	0	17
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	79
T94	422	0
T95	505	0
T96	1339	0
T200	498	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790101
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7461742	3
T34	27900	1
T89	0	1
T125	489	0
T126	506	0
T127	524	0
T128	19800	0
T129	758	0
T130	6960	0
T131	656	0
T132	435	0
T133	426	0
T215	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	241741
T31	1348	678
T36	1072	81
T37	0	141
T38	0	51085
T39	0	173
T40	0	7
T41	0	58
T43	0	342
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	46
T94	422	0
T95	505	0
T96	1339	0
T122	0	126
T200	498	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	65
T31	1348	1
T36	1072	2
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T43	0	3
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T122	0	1
T200	498	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	5871600
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	5873864
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	76
T31	1348	1
T34	0	1
T36	1072	2
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	3
T54	0	1
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T200	498	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	68
T31	1348	1
T34	0	1
T36	1072	2
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T122	0	1
T200	498	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	65
T31	1348	1
T36	1072	2
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T43	0	3
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T122	0	1
T200	498	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	65
T31	1348	1
T36	1072	2
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T43	0	3
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	1
T94	422	0
T95	505	0
T96	1339	0
T122	0	1
T200	498	0

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	241643
T31	1348	676
T36	1072	78
T37	0	139
T38	0	51083
T39	0	171
T40	0	6
T41	0	55
T43	0	337
T62	2167	0
T63	658	0
T73	493	0
T74	493	0
T78	0	44
T94	422	0
T95	505	0
T96	1339	0
T122	0	124
T200	498	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	31
T33	690	0
T36	1072	1
T40	0	1
T41	0	1
T42	490	0
T43	0	1
T44	0	1
T63	658	0
T64	10608	0
T81	475	0
T94	422	0
T95	505	0
T96	1339	0
T97	422	0
T143	0	1
T144	0	2
T145	0	1
T154	0	1
T199	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T54,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T33,T54,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T33,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T33,T54,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T35,T44,T143
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T35,T44,T143

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T54,T34
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T54,T170,T276
DetectSt->IdleSt	186	Covered	T187
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T33,T54,T34
StableSt->IdleSt	206	Covered	T34,T35,T43

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T54,T34
0	1	Covered	T33,T54,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T54,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T170,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T54,T34
DetectSt	-	-	-	-	1	-	-	Covered	T187
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T44,T143
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	81	0	0
CntIncr_A	7461742	2338	0	0
CntNoWrap_A	7461742	6790164	0	0
DetectStDropOut_A	7461742	1	0	0
DetectedOut_A	7461742	2722	0	0
DetectedPulseOut_A	7461742	38	0	0
DisabledIdleSt_A	7461742	6314215	0	0
DisabledNoDetection_A	7461742	6316483	0	0
EnterDebounceSt_A	7461742	42	0	0
EnterDetectSt_A	7461742	39	0	0
EnterStableSt_A	7461742	38	0	0
PulseIsPulse_A	7461742	38	0	0
StayInStableSt	7461742	2663	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7461742	6879	0	0
gen_low_level_sva.LowLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	16	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7461742	81
T33	690	2
T34	0	4
T35	0	4
T43	0	2
T44	0	4
T53	670	0
T54	0	1
T81	475	0
T82	24441	0
T85	0	4
T89	0	2
T120	14213	0
T143	0	2
T154	0	2
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

CntIncr_A

Name	Attempts	Real Successes
Total	7461742	2338
T33	690	49
T34	0	107
T35	0	120
T43	0	81
T44	0	22
T53	670	0
T54	0	16
T81	475	0
T82	24441	0
T85	0	106
T89	0	88
T120	14213	0
T143	0	71
T154	0	64
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7461742	6790164
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7461742	1
T187	874	1
T189	402	0
T190	408	0
T191	523	0
T192	14861	0
T193	17469	0
T194	418	0
T195	806	0
T196	497	0
T197	775	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7461742	2722
T33	690	39
T34	0	203
T35	0	83
T43	0	53
T44	0	82
T53	670	0
T81	475	0
T82	24441	0
T85	0	200
T89	0	184
T120	14213	0
T143	0	20
T154	0	89
T198	0	189
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7461742	38
T33	690	1
T34	0	2
T35	0	2
T43	0	1
T44	0	2
T53	670	0
T81	475	0
T82	24441	0
T85	0	2
T89	0	1
T120	14213	0
T143	0	1
T154	0	1
T198	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7461742	6314215
T1	15775	15366
T4	492	91
T5	503	102
T6	491	90
T14	422	21
T15	526	125
T16	437	36
T22	878	477
T23	506	105
T24	648	247

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7461742	6316483
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7461742	42
T33	690	1
T34	0	2
T35	0	2
T43	0	1
T44	0	2
T53	670	0
T54	0	1
T81	475	0
T82	24441	0
T85	0	2
T89	0	1
T120	14213	0
T143	0	1
T154	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7461742	39
T33	690	1
T34	0	2
T35	0	2
T43	0	1
T44	0	2
T53	670	0
T81	475	0
T82	24441	0
T85	0	2
T89	0	1
T120	14213	0
T143	0	1
T154	0	1
T198	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7461742	38
T33	690	1
T34	0	2
T35	0	2
T43	0	1
T44	0	2
T53	670	0
T81	475	0
T82	24441	0
T85	0	2
T89	0	1
T120	14213	0
T143	0	1
T154	0	1
T198	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7461742	38
T33	690	1
T34	0	2
T35	0	2
T43	0	1
T44	0	2
T53	670	0
T81	475	0
T82	24441	0
T85	0	2
T89	0	1
T120	14213	0
T143	0	1
T154	0	1
T198	0	1
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

StayInStableSt

Name	Attempts	Real Successes
Total	7461742	2663
T33	690	37
T34	0	199
T35	0	81
T43	0	51
T44	0	79
T53	670	0
T81	475	0
T82	24441	0
T85	0	197
T89	0	183
T120	14213	0
T143	0	19
T154	0	87
T198	0	187
T251	439	0
T252	1061	0
T253	503	0
T254	525	0
T255	422	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7461742	6879
T1	15775	30
T4	492	7
T5	503	4
T6	491	7
T14	422	2
T15	526	5
T16	437	2
T17	0	4
T22	878	0
T23	506	4
T24	648	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7461742	6792567
T1	15775	15371
T4	492	92
T5	503	103
T6	491	91
T14	422	22
T15	526	126
T16	437	37
T22	878	478
T23	506	106
T24	648	248

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7461742	16
T35	780	2
T43	20851	0
T44	0	1
T85	0	1
T89	0	1
T143	0	1
T161	0	1
T162	639	0
T163	425	0
T164	629	0
T165	507	0
T166	561	0
T167	501	0
T168	522	0
T169	499	0
T187	0	1
T199	0	1
T250	0	1
T258	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr