Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T20,T8
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T8,T98,T54
1	0	Covered	T8,T54,T106

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T10
0	1	Covered	T1,T20,T10
1	0	Covered	T54,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T10
1	-	Covered	T1,T20,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T8
DetectSt	168	Covered	T1,T20,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T20,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T20,T8
DebounceSt->IdleSt	163	Covered	T54,T102,T277
DetectSt->IdleSt	186	Covered	T8,T98,T54
DetectSt->StableSt	191	Covered	T1,T20,T10
IdleSt->DebounceSt	148	Covered	T1,T20,T8
StableSt->IdleSt	206	Covered	T1,T20,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T20,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T102,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T98,T54
DetectSt	-	-	-	-	0	1	-	Covered	T1,T20,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T20,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T20,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	2970	0	0
CntIncr_A	7461742	100265	0	0
CntNoWrap_A	7461742	6787275	0	0
DetectStDropOut_A	7461742	412	0	0
DetectedOut_A	7461742	73160	0	0
DetectedPulseOut_A	7461742	893	0	0
DisabledIdleSt_A	7461742	6344268	0	0
DisabledNoDetection_A	7461742	6346412	0	0
EnterDebounceSt_A	7461742	1503	0	0
EnterDetectSt_A	7461742	1469	0	0
EnterStableSt_A	7461742	893	0	0
PulseIsPulse_A	7461742	893	0	0
StayInStableSt	7461742	72176	0	0
gen_high_event_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	800	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2970	0	0
T1	15775	22	0	0
T2	1070	0	0	0
T8	0	14	0	0
T10	0	10	0	0
T12	0	20	0	0
T13	0	42	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	48	0	0
T21	436	0	0	0
T49	0	64	0	0
T50	0	28	0	0
T51	0	32	0	0
T81	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	100265	0	0
T1	15775	616	0	0
T2	1070	0	0	0
T8	0	523	0	0
T10	0	310	0	0
T12	0	420	0	0
T13	0	1428	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1224	0	0
T21	436	0	0	0
T49	0	2944	0	0
T50	0	868	0	0
T51	0	784	0	0
T81	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6787275	0	0
T1	15775	15344	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	412	0	0
T8	16720	4	0	0
T9	56461	0	0	0
T10	10206	0	0	0
T11	19774	0	0	0
T45	43473	0	0	0
T46	677	0	0	0
T54	0	1	0	0
T70	493	0	0	0
T71	496	0	0	0
T75	529	0	0	0
T76	529	0	0	0
T98	0	4	0	0
T101	0	11	0	0
T102	0	2	0	0
T103	0	25	0	0
T105	0	15	0	0
T106	0	14	0	0
T278	0	5	0	0
T279	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	73160	0	0
T1	15775	1022	0	0
T2	1070	0	0	0
T10	0	1473	0	0
T12	0	354	0	0
T13	0	1229	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	241	0	0
T21	436	0	0	0
T49	0	2207	0	0
T50	0	845	0	0
T51	0	1068	0	0
T81	0	49	0	0
T82	0	2729	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	11	0	0
T2	1070	0	0	0
T10	0	5	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	32	0	0
T50	0	14	0	0
T51	0	16	0	0
T81	0	1	0	0
T82	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6344268	0	0
T1	15775	10770	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6346412	0	0
T1	15775	10772	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1503	0	0
T1	15775	11	0	0
T2	1070	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	32	0	0
T50	0	14	0	0
T51	0	16	0	0
T81	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1469	0	0
T1	15775	11	0	0
T2	1070	0	0	0
T8	0	7	0	0
T10	0	5	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	32	0	0
T50	0	14	0	0
T51	0	16	0	0
T81	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	11	0	0
T2	1070	0	0	0
T10	0	5	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	32	0	0
T50	0	14	0	0
T51	0	16	0	0
T81	0	1	0	0
T82	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	11	0	0
T2	1070	0	0	0
T10	0	5	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	32	0	0
T50	0	14	0	0
T51	0	16	0	0
T81	0	1	0	0
T82	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	72176	0	0
T1	15775	1009	0	0
T2	1070	0	0	0
T10	0	1467	0	0
T12	0	344	0	0
T13	0	1208	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	217	0	0
T21	436	0	0	0
T49	0	2171	0	0
T50	0	831	0	0
T51	0	1050	0	0
T81	0	47	0	0
T82	0	2696	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	800	0	0
T1	15775	9	0	0
T2	1070	0	0	0
T10	0	4	0	0
T12	0	10	0	0
T13	0	21	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	28	0	0
T50	0	14	0	0
T51	0	14	0	0
T82	0	17	0	0
T120	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T1,T20,T3
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T99,T100,T104
1	0	Covered	T54,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T54,T280

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T81,T54,T150
DetectSt->IdleSt	186	Covered	T54,T99,T100
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T150,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T54,T99,T100
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	876	0	0
CntIncr_A	7461742	45789	0	0
CntNoWrap_A	7461742	6789369	0	0
DetectStDropOut_A	7461742	51	0	0
DetectedOut_A	7461742	16168	0	0
DetectedPulseOut_A	7461742	346	0	0
DisabledIdleSt_A	7461742	6429503	0	0
DisabledNoDetection_A	7461742	6431131	0	0
EnterDebounceSt_A	7461742	478	0	0
EnterDetectSt_A	7461742	400	0	0
EnterStableSt_A	7461742	346	0	0
PulseIsPulse_A	7461742	346	0	0
StayInStableSt	7461742	15800	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	876	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T3	0	2	0	0
T9	0	4	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	2	0	0
T49	0	8	0	0
T51	0	4	0	0
T80	0	6	0	0
T81	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	45789	0	0
T1	15775	59	0	0
T2	1070	0	0	0
T3	0	25	0	0
T9	0	304	0	0
T10	0	74	0	0
T11	0	193	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	145	0	0
T49	0	308	0	0
T51	0	124	0	0
T80	0	309	0	0
T81	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6789369	0	0
T1	15775	15364	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	51	0	0
T37	718	0	0	0
T43	0	1	0	0
T84	658	0	0	0
T99	11997	4	0	0
T100	15744	3	0	0
T101	5516	0	0	0
T102	4766	0	0	0
T104	0	6	0	0
T107	0	1	0	0
T108	0	4	0	0
T109	0	2	0	0
T110	0	6	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	1643	0	0	0
T114	1614	0	0	0
T115	506	0	0	0
T116	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	16168	0	0
T1	15775	41	0	0
T2	1070	0	0	0
T3	0	3	0	0
T9	0	38	0	0
T10	0	259	0	0
T11	0	17	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	46	0	0
T49	0	147	0	0
T51	0	57	0	0
T80	0	214	0	0
T82	0	585	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	346	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T80	0	3	0	0
T82	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6429503	0	0
T1	15775	14346	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6431131	0	0
T1	15775	14349	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	478	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T80	0	3	0	0
T81	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	400	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T80	0	3	0	0
T82	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	346	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T80	0	3	0	0
T82	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	346	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	2	0	0
T80	0	3	0	0
T82	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	15800	0	0
T1	15775	40	0	0
T2	1070	0	0	0
T3	0	2	0	0
T9	0	36	0	0
T10	0	258	0	0
T11	0	16	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	45	0	0
T49	0	139	0	0
T51	0	55	0	0
T80	0	211	0	0
T82	0	577	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	320	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T51	0	2	0	0
T80	0	3	0	0
T82	0	8	0	0
T120	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T20,T8
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T10,T98,T101
1	0	Covered	T10,T82,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
1	0	Covered	T54,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T8
1	-	Covered	T1,T20,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T8
DetectSt	168	Covered	T1,T20,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T20,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T20,T8
DebounceSt->IdleSt	163	Covered	T54,T102,T277
DetectSt->IdleSt	186	Covered	T10,T82,T98
DetectSt->StableSt	191	Covered	T1,T20,T8
IdleSt->DebounceSt	148	Covered	T1,T20,T8
StableSt->IdleSt	206	Covered	T1,T20,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T20,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T102,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T10,T82,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T20,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	2686	0	0
CntIncr_A	7461742	93514	0	0
CntNoWrap_A	7461742	6787559	0	0
DetectStDropOut_A	7461742	309	0	0
DetectedOut_A	7461742	75279	0	0
DetectedPulseOut_A	7461742	893	0	0
DisabledIdleSt_A	7461742	6341890	0	0
DisabledNoDetection_A	7461742	6344036	0	0
EnterDebounceSt_A	7461742	1367	0	0
EnterDetectSt_A	7461742	1321	0	0
EnterStableSt_A	7461742	893	0	0
PulseIsPulse_A	7461742	893	0	0
StayInStableSt	7461742	74298	0	0
gen_high_event_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	802	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2686	0	0
T1	15775	16	0	0
T2	1070	0	0	0
T8	0	22	0	0
T10	0	38	0	0
T12	0	50	0	0
T13	0	8	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	48	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	52	0	0
T51	0	44	0	0
T82	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	93514	0	0
T1	15775	312	0	0
T2	1070	0	0	0
T8	0	715	0	0
T10	0	1603	0	0
T12	0	900	0	0
T13	0	296	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1224	0	0
T21	436	0	0	0
T49	0	390	0	0
T50	0	1846	0	0
T51	0	1254	0	0
T82	0	1501	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6787559	0	0
T1	15775	15350	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	309	0	0
T10	10206	14	0	0
T11	19774	0	0	0
T12	10728	0	0	0
T13	10074	0	0	0
T29	992	0	0	0
T47	7563	0	0	0
T71	496	0	0	0
T76	529	0	0	0
T98	0	24	0	0
T101	0	9	0	0
T102	0	2	0	0
T103	0	9	0	0
T105	0	18	0	0
T279	0	13	0	0
T281	0	2	0	0
T282	0	9	0	0
T283	0	20	0	0
T284	404	0	0	0
T285	908	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	75279	0	0
T1	15775	595	0	0
T2	1070	0	0	0
T8	0	2179	0	0
T12	0	1541	0	0
T13	0	1384	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	241	0	0
T21	436	0	0	0
T49	0	375	0	0
T50	0	1925	0	0
T51	0	1285	0	0
T54	0	315	0	0
T120	0	1010	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	11	0	0
T12	0	25	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	0	22	0	0
T54	0	5	0	0
T120	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6341890	0	0
T1	15775	11306	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6344036	0	0
T1	15775	11309	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1367	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	11	0	0
T10	0	19	0	0
T12	0	25	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	0	22	0	0
T82	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1321	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	11	0	0
T10	0	19	0	0
T12	0	25	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	0	22	0	0
T82	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	11	0	0
T12	0	25	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	0	22	0	0
T54	0	5	0	0
T120	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	893	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	11	0	0
T12	0	25	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	0	22	0	0
T54	0	5	0	0
T120	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	74298	0	0
T1	15775	586	0	0
T2	1070	0	0	0
T8	0	2165	0	0
T12	0	1515	0	0
T13	0	1380	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	217	0	0
T21	436	0	0	0
T49	0	369	0	0
T50	0	1898	0	0
T51	0	1263	0	0
T54	0	310	0	0
T120	0	987	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	802	0	0
T1	15775	7	0	0
T2	1070	0	0	0
T8	0	8	0	0
T12	0	24	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	24	0	0
T21	436	0	0	0
T49	0	6	0	0
T50	0	25	0	0
T51	0	22	0	0
T54	0	4	0	0
T120	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T1,T20,T3
1	1	Covered	T1,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T11,T47,T109
1	0	Covered	T54,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T59,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T8
DetectSt	168	Covered	T1,T3,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T8
DebounceSt->IdleSt	163	Covered	T54,T150,T99
DetectSt->IdleSt	186	Covered	T11,T47,T54
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T3,T8
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T99,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T11,T47,T54
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	837	0	0
CntIncr_A	7461742	49725	0	0
CntNoWrap_A	7461742	6789408	0	0
DetectStDropOut_A	7461742	34	0	0
DetectedOut_A	7461742	13238	0	0
DetectedPulseOut_A	7461742	357	0	0
DisabledIdleSt_A	7461742	6424253	0	0
DisabledNoDetection_A	7461742	6425936	0	0
EnterDebounceSt_A	7461742	443	0	0
EnterDetectSt_A	7461742	395	0	0
EnterStableSt_A	7461742	357	0	0
PulseIsPulse_A	7461742	357	0	0
StayInStableSt	7461742	12863	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	837	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T3	0	2	0	0
T8	0	12	0	0
T9	0	28	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	2	0	0
T50	0	2	0	0
T80	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	49725	0	0
T1	15775	48	0	0
T2	1070	0	0	0
T3	0	85	0	0
T8	0	480	0	0
T9	0	1960	0	0
T11	0	420	0	0
T12	0	39	0	0
T13	0	112	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	191	0	0
T50	0	54	0	0
T80	0	468	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6789408	0	0
T1	15775	15364	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	34	0	0
T11	19774	2	0	0
T12	10728	0	0	0
T13	10074	0	0	0
T29	992	0	0	0
T47	7563	1	0	0
T48	732	0	0	0
T55	524	0	0	0
T56	426	0	0	0
T109	0	2	0	0
T111	0	1	0	0
T112	0	4	0	0
T206	0	1	0	0
T220	0	5	0	0
T271	0	6	0	0
T284	404	0	0	0
T285	908	0	0	0
T286	0	1	0	0
T287	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	13238	0	0
T1	15775	52	0	0
T2	1070	0	0	0
T3	0	8	0	0
T8	0	437	0	0
T9	0	439	0	0
T12	0	57	0	0
T13	0	637	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	34	0	0
T54	0	76	0	0
T80	0	55	0	0
T120	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	357	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T80	0	3	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6424253	0	0
T1	15775	14772	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6425936	0	0
T1	15775	14776	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	443	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T80	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	395	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T80	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	357	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T80	0	3	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	357	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T80	0	3	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	12863	0	0
T1	15775	51	0	0
T2	1070	0	0	0
T3	0	7	0	0
T8	0	431	0	0
T9	0	425	0	0
T12	0	56	0	0
T13	0	635	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	33	0	0
T54	0	75	0	0
T80	0	52	0	0
T120	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	336	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T3	0	1	0	0
T8	0	6	0	0
T9	0	14	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T80	0	3	0	0
T120	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T20,T8
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T10,T82,T98
1	0	Covered	T10,T82,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
1	0	Covered	T54,T86,T288

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T8
1	-	Covered	T1,T20,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T8
DetectSt	168	Covered	T1,T20,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T20,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T20,T8
DebounceSt->IdleSt	163	Covered	T54,T102,T277
DetectSt->IdleSt	186	Covered	T10,T82,T98
DetectSt->StableSt	191	Covered	T1,T20,T8
IdleSt->DebounceSt	148	Covered	T1,T20,T8
StableSt->IdleSt	206	Covered	T1,T20,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T20,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T102,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T10,T82,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T20,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	2757	0	0
CntIncr_A	7461742	93864	0	0
CntNoWrap_A	7461742	6787488	0	0
DetectStDropOut_A	7461742	394	0	0
DetectedOut_A	7461742	71281	0	0
DetectedPulseOut_A	7461742	824	0	0
DisabledIdleSt_A	7461742	6351071	0	0
DisabledNoDetection_A	7461742	6353223	0	0
EnterDebounceSt_A	7461742	1406	0	0
EnterDetectSt_A	7461742	1352	0	0
EnterStableSt_A	7461742	824	0	0
PulseIsPulse_A	7461742	824	0	0
StayInStableSt	7461742	70374	0	0
gen_high_event_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	707	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2757	0	0
T1	15775	46	0	0
T2	1070	0	0	0
T8	0	36	0	0
T10	0	24	0	0
T12	0	42	0	0
T13	0	4	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	54	0	0
T21	436	0	0	0
T49	0	50	0	0
T50	0	34	0	0
T51	0	24	0	0
T82	0	64	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	93864	0	0
T1	15775	1380	0	0
T2	1070	0	0	0
T8	0	1134	0	0
T10	0	1011	0	0
T12	0	945	0	0
T13	0	150	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1458	0	0
T21	436	0	0	0
T49	0	2425	0	0
T50	0	986	0	0
T51	0	552	0	0
T82	0	1905	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6787488	0	0
T1	15775	15320	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	394	0	0
T10	10206	7	0	0
T11	19774	0	0	0
T12	10728	0	0	0
T13	10074	0	0	0
T29	992	0	0	0
T47	7563	0	0	0
T54	0	1	0	0
T71	496	0	0	0
T76	529	0	0	0
T82	0	17	0	0
T98	0	15	0	0
T101	0	5	0	0
T102	0	6	0	0
T103	0	7	0	0
T105	0	16	0	0
T279	0	13	0	0
T281	0	9	0	0
T284	404	0	0	0
T285	908	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	71281	0	0
T1	15775	1034	0	0
T2	1070	0	0	0
T8	0	2153	0	0
T12	0	677	0	0
T13	0	86	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1600	0	0
T21	436	0	0	0
T49	0	1482	0	0
T50	0	1141	0	0
T51	0	577	0	0
T54	0	283	0	0
T120	0	1144	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	824	0	0
T1	15775	23	0	0
T2	1070	0	0	0
T8	0	18	0	0
T12	0	21	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	25	0	0
T50	0	17	0	0
T51	0	12	0	0
T54	0	5	0	0
T120	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6351071	0	0
T1	15775	10839	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6353223	0	0
T1	15775	10840	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1406	0	0
T1	15775	23	0	0
T2	1070	0	0	0
T8	0	18	0	0
T10	0	12	0	0
T12	0	21	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	25	0	0
T50	0	17	0	0
T51	0	12	0	0
T82	0	32	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1352	0	0
T1	15775	23	0	0
T2	1070	0	0	0
T8	0	18	0	0
T10	0	12	0	0
T12	0	21	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	25	0	0
T50	0	17	0	0
T51	0	12	0	0
T82	0	32	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	824	0	0
T1	15775	23	0	0
T2	1070	0	0	0
T8	0	18	0	0
T12	0	21	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	25	0	0
T50	0	17	0	0
T51	0	12	0	0
T54	0	5	0	0
T120	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	824	0	0
T1	15775	23	0	0
T2	1070	0	0	0
T8	0	18	0	0
T12	0	21	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	25	0	0
T50	0	17	0	0
T51	0	12	0	0
T54	0	5	0	0
T120	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	70374	0	0
T1	15775	1008	0	0
T2	1070	0	0	0
T8	0	2131	0	0
T12	0	655	0	0
T13	0	84	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1573	0	0
T21	436	0	0	0
T49	0	1455	0	0
T50	0	1123	0	0
T51	0	564	0	0
T54	0	278	0	0
T120	0	1120	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	707	0	0
T1	15775	20	0	0
T2	1070	0	0	0
T8	0	14	0	0
T12	0	20	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	27	0	0
T21	436	0	0	0
T49	0	23	0	0
T50	0	16	0	0
T51	0	11	0	0
T54	0	4	0	0
T120	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T1,T20,T3
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T80,T100,T289
1	0	Covered	T54,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T54,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T8
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T20,T11,T54
DetectSt->IdleSt	186	Covered	T80,T54,T100
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T20,T8
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T11,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T80,T54,T100
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	699	0	0
CntIncr_A	7461742	42156	0	0
CntNoWrap_A	7461742	6789546	0	0
DetectStDropOut_A	7461742	38	0	0
DetectedOut_A	7461742	12552	0	0
DetectedPulseOut_A	7461742	284	0	0
DisabledIdleSt_A	7461742	6423163	0	0
DisabledNoDetection_A	7461742	6424847	0	0
EnterDebounceSt_A	7461742	374	0	0
EnterDetectSt_A	7461742	327	0	0
EnterStableSt_A	7461742	284	0	0
PulseIsPulse_A	7461742	284	0	0
StayInStableSt	7461742	12238	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	251	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	699	0	0
T1	15775	4	0	0
T2	1070	0	0	0
T8	0	8	0	0
T9	0	4	0	0
T11	0	5	0	0
T12	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1	0	0
T21	436	0	0	0
T47	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T80	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	42156	0	0
T1	15775	110	0	0
T2	1070	0	0	0
T8	0	392	0	0
T9	0	244	0	0
T11	0	451	0	0
T12	0	50	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	36	0	0
T21	436	0	0	0
T47	0	185	0	0
T49	0	164	0	0
T50	0	59	0	0
T80	0	348	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6789546	0	0
T1	15775	15362	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	38	0	0
T51	12069	0	0	0
T52	5695	0	0	0
T61	2476	0	0	0
T72	492	0	0	0
T77	3203	0	0	0
T80	13277	2	0	0
T100	0	1	0	0
T171	0	5	0	0
T220	0	5	0	0
T237	0	2	0	0
T289	0	2	0	0
T290	0	2	0	0
T291	0	10	0	0
T292	0	5	0	0
T293	0	4	0	0
T294	522	0	0	0
T295	679	0	0	0
T296	431	0	0	0
T297	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	12552	0	0
T1	15775	88	0	0
T2	1070	0	0	0
T8	0	218	0	0
T9	0	42	0	0
T11	0	68	0	0
T12	0	46	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	6	0	0
T49	0	63	0	0
T50	0	28	0	0
T51	0	20	0	0
T120	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	284	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6423163	0	0
T1	15775	14335	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6424847	0	0
T1	15775	14337	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	374	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	3	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	1	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T80	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	327	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T80	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	284	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	284	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	12238	0	0
T1	15775	86	0	0
T2	1070	0	0	0
T8	0	214	0	0
T9	0	40	0	0
T11	0	66	0	0
T12	0	45	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	5	0	0
T49	0	59	0	0
T50	0	26	0	0
T51	0	19	0	0
T120	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	251	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T47	0	1	0	0
T51	0	1	0	0
T99	0	4	0	0
T150	0	3	0	0