Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T8
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T20,T8
1	1	Covered	T1,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T8
0	1	Covered	T8,T10,T82
1	0	Covered	T20,T8,T10

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T13
0	1	Covered	T1,T12,T13
1	0	Covered	T10,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T12
1	-	Covered	T1,T12,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T8
DetectSt	168	Covered	T1,T20,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T20,T8
DebounceSt->IdleSt	163	Covered	T54,T102,T277
DetectSt->IdleSt	186	Covered	T20,T8,T10
DetectSt->StableSt	191	Covered	T1,T10,T12
IdleSt->DebounceSt	148	Covered	T1,T20,T8
StableSt->IdleSt	206	Covered	T1,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T20,T8
0	1	Covered	T1,T20,T8
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T20,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T102,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T20,T8,T10
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T13
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	2528	0	0
CntIncr_A	7461742	89113	0	0
CntNoWrap_A	7461742	6787717	0	0
DetectStDropOut_A	7461742	396	0	0
DetectedOut_A	7461742	59184	0	0
DetectedPulseOut_A	7461742	671	0	0
DisabledIdleSt_A	7461742	6359826	0	0
DisabledNoDetection_A	7461742	6361995	0	0
EnterDebounceSt_A	7461742	1286	0	0
EnterDetectSt_A	7461742	1243	0	0
EnterStableSt_A	7461742	671	0	0
PulseIsPulse_A	7461742	671	0	0
StayInStableSt	7461742	58448	0	0
gen_high_event_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	603	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	2528	0	0
T1	15775	16	0	0
T2	1070	0	0	0
T8	0	56	0	0
T10	0	32	0	0
T12	0	18	0	0
T13	0	48	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	12	0	0
T21	436	0	0	0
T49	0	24	0	0
T50	0	28	0	0
T51	0	22	0	0
T82	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	89113	0	0
T1	15775	352	0	0
T2	1070	0	0	0
T8	0	2106	0	0
T10	0	1341	0	0
T12	0	387	0	0
T13	0	1680	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	353	0	0
T21	436	0	0	0
T49	0	804	0	0
T50	0	868	0	0
T51	0	920	0	0
T82	0	1553	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6787717	0	0
T1	15775	15350	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	396	0	0
T8	16720	21	0	0
T9	56461	0	0	0
T10	10206	13	0	0
T11	19774	0	0	0
T45	43473	0	0	0
T46	677	0	0	0
T54	0	1	0	0
T70	493	0	0	0
T71	496	0	0	0
T75	529	0	0	0
T76	529	0	0	0
T82	0	10	0	0
T98	0	8	0	0
T101	0	26	0	0
T103	0	3	0	0
T105	0	8	0	0
T106	0	14	0	0
T278	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	59184	0	0
T1	15775	555	0	0
T2	1070	0	0	0
T10	0	1	0	0
T12	0	136	0	0
T13	0	1335	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	967	0	0
T50	0	763	0	0
T54	0	259	0	0
T120	0	36	0	0
T229	0	502	0	0
T298	0	1285	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	671	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T10	0	1	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	14	0	0
T54	0	5	0	0
T120	0	3	0	0
T229	0	5	0	0
T298	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6359826	0	0
T1	15775	11307	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6361995	0	0
T1	15775	11310	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1286	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	28	0	0
T10	0	16	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	6	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	14	0	0
T51	0	11	0	0
T82	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	1243	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T8	0	28	0	0
T10	0	16	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	6	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	14	0	0
T51	0	11	0	0
T82	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	671	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T10	0	1	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	14	0	0
T54	0	5	0	0
T120	0	3	0	0
T229	0	5	0	0
T298	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	671	0	0
T1	15775	8	0	0
T2	1070	0	0	0
T10	0	1	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	12	0	0
T50	0	14	0	0
T54	0	5	0	0
T120	0	3	0	0
T229	0	5	0	0
T298	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	58448	0	0
T1	15775	546	0	0
T2	1070	0	0	0
T12	0	127	0	0
T13	0	1311	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	954	0	0
T50	0	749	0	0
T54	0	254	0	0
T120	0	33	0	0
T229	0	497	0	0
T298	0	1264	0	0
T299	0	66	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	603	0	0
T1	15775	7	0	0
T2	1070	0	0	0
T12	0	9	0	0
T13	0	24	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T49	0	11	0	0
T50	0	14	0	0
T54	0	5	0	0
T120	0	3	0	0
T229	0	5	0	0
T298	0	19	0	0
T299	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T20,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T20,T3
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T9,T80,T104
1	0	Covered	T54,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T54,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T9,T54,T150
DetectSt->IdleSt	186	Covered	T9,T80,T54
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T54,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T150,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T9,T80,T54
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7461742	745	0	0
CntIncr_A	7461742	44253	0	0
CntNoWrap_A	7461742	6789500	0	0
DetectStDropOut_A	7461742	74	0	0
DetectedOut_A	7461742	13417	0	0
DetectedPulseOut_A	7461742	270	0	0
DisabledIdleSt_A	7461742	6435098	0	0
DisabledNoDetection_A	7461742	6436799	0	0
EnterDebounceSt_A	7461742	398	0	0
EnterDetectSt_A	7461742	348	0	0
EnterStableSt_A	7461742	270	0	0
PulseIsPulse_A	7461742	270	0	0
StayInStableSt	7461742	13132	0	0
gen_high_level_sva.HighLevelEvent_A	7461742	6792567	0	0
gen_not_sticky_sva.StableStDropOut_A	7461742	253	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	745	0	0
T1	15775	2	0	0
T2	1070	0	0	0
T9	0	28	0	0
T11	0	10	0	0
T13	0	2	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T54	0	8	0	0
T80	0	10	0	0
T150	0	27	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	44253	0	0
T1	15775	42	0	0
T2	1070	0	0	0
T9	0	2333	0	0
T11	0	620	0	0
T13	0	90	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	146	0	0
T49	0	83	0	0
T50	0	54	0	0
T54	0	114	0	0
T80	0	872	0	0
T150	0	1648	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6789500	0	0
T1	15775	15364	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	74	0	0
T9	56461	3	0	0
T10	10206	0	0	0
T11	19774	0	0	0
T12	10728	0	0	0
T13	10074	0	0	0
T41	0	2	0	0
T47	7563	0	0	0
T71	496	0	0	0
T76	529	0	0	0
T80	0	5	0	0
T104	0	6	0	0
T109	0	10	0	0
T193	0	2	0	0
T242	0	7	0	0
T271	0	5	0	0
T284	404	0	0	0
T285	908	0	0	0
T300	0	7	0	0
T301	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	13417	0	0
T1	15775	58	0	0
T2	1070	0	0	0
T9	0	298	0	0
T11	0	431	0	0
T13	0	60	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	15	0	0
T47	0	45	0	0
T49	0	32	0	0
T50	0	34	0	0
T54	0	77	0	0
T150	0	720	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	270	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	10	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T150	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6435098	0	0
T1	15775	14812	0	0
T4	492	91	0	0
T5	503	102	0	0
T6	491	90	0	0
T14	422	21	0	0
T15	526	125	0	0
T16	437	36	0	0
T22	878	477	0	0
T23	506	105	0	0
T24	648	247	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6436799	0	0
T1	15775	14816	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	398	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	15	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	5	0	0
T80	0	5	0	0
T150	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	348	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	13	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	3	0	0
T80	0	5	0	0
T150	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	270	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	10	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T150	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	270	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	10	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T150	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	13132	0	0
T1	15775	57	0	0
T2	1070	0	0	0
T9	0	288	0	0
T11	0	426	0	0
T13	0	59	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	13	0	0
T47	0	44	0	0
T49	0	31	0	0
T50	0	33	0	0
T54	0	76	0	0
T150	0	707	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	6792567	0	0
T1	15775	15371	0	0
T4	492	92	0	0
T5	503	103	0	0
T6	491	91	0	0
T14	422	22	0	0
T15	526	126	0	0
T16	437	37	0	0
T22	878	478	0	0
T23	506	106	0	0
T24	648	248	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7461742	253	0	0
T1	15775	1	0	0
T2	1070	0	0	0
T9	0	10	0	0
T11	0	5	0	0
T13	0	1	0	0
T14	422	0	0	0
T15	526	0	0	0
T16	437	0	0	0
T17	493	0	0	0
T18	568	0	0	0
T19	645	0	0	0
T20	7065	0	0	0
T21	436	0	0	0
T39	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T99	0	4	0	0
T150	0	13	0	0