SYSRST_CTRL Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.260s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.070s	2.462ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.300s	2.400ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.170s	2.517ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.290s	6.032ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.510s	2.048ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.095m	59.239ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	14.020s	3.345ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	5.920s	2.038ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.510s	2.048ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	14.020s	3.345ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.412m	166.625ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	10.451m	256.777ms	88	100	88.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	9.941m	232.773ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	28.687m	1.274s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.690s	2.514ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.510s	2.261ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	20.259m	457.968ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.500s	2.608ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.632m	2.721s	47	50	94.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	28.840s	41.791ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	26.170m	1.020s	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	6.000s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.930s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.250s	2.080ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.250s	2.080ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.290s	6.032ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.510s	2.048ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	14.020s	3.345ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	36.130s	9.389ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.290s	6.032ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.510s	2.048ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	14.020s	3.345ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	36.130s	9.389ms	20	20	100.00
V2		TOTAL			675	692	97.54
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.843m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.807m	42.494ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.807m	42.494ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.202m	70.324ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			910	932	97.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.07	99.40	96.83	100.00	98.08	98.85	99.71	93.62

Failure Buckets

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 7 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 7 failures.

1.sysrst_ctrl_combo_detect_with_pre_cond.89439393843869880754739463972217771771084502450900421399329587132136697093738
Line 609, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 47518598249 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 47518598249 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 47518598249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.sysrst_ctrl_combo_detect_with_pre_cond.1509561910503594893629392403443830382076904495430038162185964957907568086711
Line 613, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 53238634162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 53238634162 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 53238634162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

4.sysrst_ctrl_ultra_low_pwr.36082758261263874295029782240903347120821852301314035658296405832531204492887
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2171624521 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2194124521 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_ERROR @ 3571624521 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3571624521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.sysrst_ctrl_ultra_low_pwr.31116600993477744052823472724115045295235014239729317979345494217764386117358
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2160819252 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2178319252 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 4878319252 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 7428319252 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7442033256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 1 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

15.sysrst_ctrl_stress_all_with_rand_reset.91600127026631360556828628976958806807135536193704455184440519992055838402225
Line 563, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6733564731 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 1067766064731 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1067766064731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.sysrst_ctrl_stress_all_with_rand_reset.65021312470155653076099579569215986659795596558686261574847692189198626703127
Line 754, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 145932668071 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 304835168071 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 1099350168071 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 1099384202218 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
  UVM_INFO @ 1101380222178 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 3 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 14.sysrst_ctrl_stress_all.89571067024967755422472210633624049143912264553781101695513191584867314038279
    Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 4308379409 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4308379409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
  - 41.sysrst_ctrl_stress_all_with_rand_reset.79694590905515850829738688362354109529896349659297530952836512644195469715747
    Line 597, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15869590180 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 15869590180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.sysrst_ctrl_stress_all_with_rand_reset.113177393620706506425566701681226898542168337250533360606831251534352368516220
    Line 561, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4214156866 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4214156866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

24.sysrst_ctrl_combo_detect_with_pre_cond.28074057771574145616748545078606840869723757906813527084023372377591865705367
Line 570, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16968317321 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 18113463289 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 18113463289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

87.sysrst_ctrl_combo_detect_with_pre_cond.77583837128799752138021915510613076612072649967484158642320684497199502387836
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13580281943 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13675281943 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 13695281943 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 13750510219 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13750510219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all has 1 failures.

25.sysrst_ctrl_stress_all.3213838098518284347054147453265272971548656481643216590866755685240090290081
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4181781661 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 4402352869 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_vseq
  UVM_INFO @ 6401303251 ps: (sysrst_ctrl_combo_detect_vseq.sv:112) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Starting the body from combo detect
  UVM_INFO @ 16461721762 ps: (sysrst_ctrl_combo_detect_vseq.sv:94) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Write data of ec_rst_ctl register:0x4d
  UVM_INFO @ 16462340809 ps: (sysrst_ctrl_combo_detect_vseq.sv:99) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Write data of key_intr_debounce_ctl register:0x45

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

39.sysrst_ctrl_combo_detect_with_pre_cond.35947473758598951522453109421718431079659907376422056935944096188628700686577
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 17017452421 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
  UVM_ERROR @ 17017452421 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 17017452421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

46.sysrst_ctrl_stress_all_with_rand_reset.49645320614227862123626942035451497949103327587050251389028630948890548820267
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9090629225 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9094291972 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/10
  UVM_INFO @ 9095156472 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 9097526472 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/10

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

64.sysrst_ctrl_combo_detect_with_pre_cond.37879688124917180903075478641850548991788722041743752013454242585072738931939
Line 570, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13512376751 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 23789965903 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 23791165903 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1b
  UVM_INFO @ 24702376751 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 24706165903 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

81.sysrst_ctrl_combo_detect_with_pre_cond.85363248794165364681478153978263934085360062124522898537795579111424102476625
Line 629, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 90826425921 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 90826425921 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 90826425921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---