Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1716

1

T6

32

T2

7

T7

8

auto[1]

608

1

T2

14

T3

1

T7

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1740

1

T6

32

T2

10

T3

1

auto[1]

584

1

T2

11

T7

11

T13

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1720

1

T6

20

T2

21

T7

15

auto[1]

604

1

T6

12

T3

1

T7

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1814

1

T6

25

T2

4

T7

10

auto[1]

510

1

T6

7

T2

17

T3

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2146

1

T6

25

T2

21

T3

1

auto[1]

178

1

T6

7

T43

10

T60

9

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2116

1

T6

20

T2

21

T3

1

auto[1]

208

1

T6

12

T43

4

T49

8

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2155

1

T6

32

T2

21

T3

1

auto[1]

169

1

T43

4

T49

21

T50

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2127

1

T6

27

T2

21

T3

1

auto[1]

197

1

T6

5

T13

1

T43

24

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2172

1

T6

27

T2

21

T3

1

auto[1]

152

1

T6

5

T33

6

T60

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1813

1

T6

32

T2

10

T3

1

auto[1]

511

1

T2

11

T7

2

T48

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	824	1			T2	21		T3	1		T7	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	60	1			T43	6		T60	9		T35	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	51	1			T33	6		T60	8		T35	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T330	4		T326	2		T332	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	67	1			T13	1		T43	16		T35	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	26	1			T213	3		T214	2		T333	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	28	1			T69	1		T330	6		T233	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	59	1			T49	13		T50	4		T214	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T214	2		T215	12		T321	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T333	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T88	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T331	2		T334	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T319	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	77	1			T62	2		T213	2		T84	15
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T6	7		T319	8		T335	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T333	3		T319	11		T336	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T215	1		T326	2		T337	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	21	1			T83	6		T84	8		T333	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T6	5		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	31	1			T49	8		T319	8		T338	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T339	1		T340	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T60	1		T232	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T43	4		T341	1		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

132

1

T223

11

T84

15

T65

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

125

1

T43

12

T34

11

T213

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

48

1

T48

1

T83

6

T85

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T48

1

T60

1

T215

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

52

1

T2

10

T7

5

T49

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T223

4

T214

2

T209

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T138

1

T86

2

T270

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T6

5

T67

8

T224

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

82

1

T60

8

T35

5

T223

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T36

5

T60

9

T62

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T217

4

T338

7

T229

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

84

1

T6

7

T33

6

T270

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T3

1

T82

2

T333

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T315

1

T326

3

T219

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T213

1

T320

1

T125

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

84

1

T7

8

T36

11

T43

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

42

1

T49

13

T65

3

T319

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T67

2

T215

6

T342

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T2

4

T7

2

T35

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T50

4

T215

6

T333

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T36

3

T216

2

T138

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T2

7

T35

2

T343

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T34

2

T315

1

T142

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T43

8

T213

3

T214

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T13

1

T34

3

T65

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T82

3

T214

6

T333

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T344

2

T325

1

T345

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T223

2

T213

1

T176

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T7

1

T346

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T86

1

T328

4

T327

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T125

1

T235

1

T230

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded