Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.33 96.78 100.00 96.79 98.82 99.52 92.61


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.97 67.97 84.77 84.77 75.10 75.10 86.99 86.99 39.74 39.74 86.10 86.10 78.61 78.61 24.44 24.44 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2803903
76.78 8.81 92.16 7.39 84.73 9.63 91.55 4.57 55.13 15.38 92.13 6.03 88.54 9.92 33.21 8.77 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3955381768
81.43 4.65 95.32 3.15 89.00 4.27 93.72 2.17 63.46 8.33 95.16 3.03 92.68 4.14 40.65 7.44 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.977336176
83.98 2.56 95.61 0.30 89.43 0.43 94.18 0.46 67.31 3.85 95.49 0.33 93.83 1.16 52.02 11.37 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1130236178
86.46 2.48 96.73 1.12 91.03 1.59 94.18 0.00 80.77 13.46 96.67 1.18 93.83 0.00 52.02 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3911066001
88.40 1.94 97.69 0.95 92.11 1.09 94.18 0.00 85.90 5.13 97.38 0.70 96.15 2.31 55.42 3.40 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1663631768
89.86 1.46 97.89 0.21 92.52 0.40 94.18 0.00 85.90 0.00 97.38 0.00 96.15 0.00 65.04 9.62 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1505348682
91.14 1.28 97.97 0.07 93.71 1.19 94.86 0.68 85.90 0.00 97.49 0.11 96.24 0.10 71.84 6.80 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1495651479
92.05 0.91 98.15 0.19 93.86 0.15 98.17 3.31 87.18 1.28 97.56 0.07 96.34 0.10 73.11 1.28 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.267086665
92.81 0.76 98.26 0.11 93.93 0.08 98.17 0.00 87.82 0.64 97.63 0.07 96.53 0.19 77.31 4.20 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1828604373
93.37 0.56 98.36 0.09 94.08 0.15 98.17 0.00 88.46 0.64 97.67 0.04 96.72 0.19 80.13 2.82 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1190207099
93.84 0.47 98.41 0.06 94.11 0.03 98.17 0.00 89.10 0.64 97.74 0.07 96.82 0.10 82.52 2.39 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2984313414
94.20 0.36 98.53 0.11 94.19 0.08 98.17 0.00 91.03 1.92 97.86 0.11 97.11 0.29 82.52 0.00 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2285146531
94.52 0.32 98.56 0.04 94.24 0.05 98.17 0.00 91.67 0.64 97.89 0.04 97.21 0.10 83.90 1.38 /workspace/coverage/default/36.sysrst_ctrl_stress_all.96456623
94.80 0.28 98.64 0.07 94.31 0.08 98.17 0.00 92.31 0.64 97.93 0.04 97.78 0.58 84.48 0.58 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3737647063
95.05 0.25 98.73 0.09 94.36 0.05 98.17 0.00 93.59 1.28 98.04 0.11 97.98 0.19 84.48 0.00 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1678508763
95.29 0.24 98.73 0.00 94.39 0.03 98.17 0.00 93.59 0.00 98.04 0.00 97.98 0.00 86.13 1.65 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1657989351
95.53 0.24 98.79 0.06 94.46 0.08 99.54 1.37 93.59 0.00 98.04 0.00 97.98 0.00 86.29 0.16 /workspace/coverage/default/16.sysrst_ctrl_alert_test.2713824472
95.75 0.22 98.84 0.06 94.46 0.00 99.54 0.00 94.23 0.64 98.08 0.04 97.98 0.00 87.09 0.80 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2432807849
95.92 0.17 98.90 0.06 94.79 0.33 99.54 0.00 94.87 0.64 98.15 0.07 98.07 0.10 87.09 0.00 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.926036891
96.06 0.15 98.90 0.00 94.82 0.03 99.54 0.00 94.87 0.00 98.15 0.00 98.17 0.10 87.99 0.90 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.192534125
96.19 0.13 98.90 0.00 94.92 0.10 99.54 0.00 94.87 0.00 98.15 0.00 98.75 0.58 88.20 0.21 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.397079635
96.32 0.13 98.94 0.04 94.94 0.03 99.54 0.00 95.51 0.64 98.19 0.04 98.84 0.10 88.26 0.05 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1425780916
96.45 0.13 98.94 0.00 95.73 0.78 99.54 0.00 95.51 0.00 98.19 0.00 98.84 0.00 88.36 0.11 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1972045899
96.56 0.12 98.97 0.04 95.75 0.03 99.54 0.00 96.15 0.64 98.23 0.04 98.94 0.10 88.36 0.00 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2129468468
96.68 0.12 99.01 0.04 95.78 0.03 99.54 0.00 96.79 0.64 98.26 0.04 99.04 0.10 88.36 0.00 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4057682777
96.79 0.10 99.03 0.02 95.78 0.00 99.54 0.00 96.79 0.00 98.26 0.00 99.04 0.00 89.05 0.69 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2024737622
96.88 0.10 99.03 0.00 95.80 0.03 100.00 0.46 96.79 0.00 98.26 0.00 99.13 0.10 89.16 0.11 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3027390410
96.96 0.07 99.10 0.07 95.90 0.10 100.00 0.00 96.79 0.00 98.41 0.15 99.33 0.19 89.16 0.00 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.572860546
97.03 0.07 99.10 0.00 95.90 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 89.64 0.48 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3651746937
97.09 0.07 99.10 0.00 95.90 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 90.12 0.48 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1441507068
97.16 0.06 99.10 0.00 96.33 0.43 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 90.12 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3274674353
97.21 0.05 99.14 0.04 96.49 0.15 100.00 0.00 96.79 0.00 98.48 0.07 99.42 0.10 90.12 0.00 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1397251031
97.25 0.04 99.14 0.00 96.51 0.03 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 90.38 0.27 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.860814895
97.29 0.04 99.14 0.00 96.51 0.00 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 90.65 0.27 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1114664992
97.32 0.03 99.14 0.00 96.51 0.00 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 90.86 0.21 /workspace/coverage/default/2.sysrst_ctrl_stress_all.1311828270
97.35 0.03 99.14 0.00 96.51 0.00 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 91.07 0.21 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.4212189276
97.38 0.03 99.14 0.00 96.51 0.00 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 91.29 0.21 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2598973589
97.41 0.03 99.14 0.00 96.71 0.20 100.00 0.00 96.79 0.00 98.48 0.00 99.42 0.00 91.29 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1224922666
97.43 0.02 99.18 0.04 96.71 0.00 100.00 0.00 96.79 0.00 98.56 0.07 99.42 0.00 91.34 0.05 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4059600711
97.45 0.02 99.18 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.42 0.00 91.50 0.16 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2634407954
97.47 0.02 99.20 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.42 0.00 91.60 0.11 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1688880613
97.49 0.02 99.23 0.04 96.71 0.00 100.00 0.00 96.79 0.00 98.63 0.07 99.42 0.00 91.60 0.00 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2733761188
97.50 0.02 99.27 0.04 96.71 0.00 100.00 0.00 96.79 0.00 98.71 0.07 99.42 0.00 91.60 0.00 /workspace/coverage/default/29.sysrst_ctrl_stress_all.2942721992
97.52 0.02 99.31 0.04 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.07 99.42 0.00 91.60 0.00 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2995672392
97.53 0.02 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.00 99.42 0.00 91.71 0.11 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1483943269
97.55 0.02 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.00 99.42 0.00 91.82 0.11 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2004411327
97.56 0.02 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.00 99.42 0.00 91.92 0.11 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3120450038
97.58 0.02 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.00 99.42 0.00 92.03 0.11 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3918682218
97.59 0.01 99.31 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.78 0.00 99.52 0.10 92.03 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2109860570
97.60 0.01 99.33 0.02 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.04 99.52 0.00 92.03 0.00 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.776697004
97.61 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.08 0.05 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2733894276
97.62 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.14 0.05 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.326574997
97.62 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.19 0.05 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3745608680
97.63 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.24 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.598754954
97.64 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.30 0.05 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3516146666
97.65 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.35 0.05 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1422641982
97.65 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.40 0.05 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3932238078
97.66 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.45 0.05 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3140584026
97.67 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.51 0.05 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1593716145
97.68 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.56 0.05 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1168376804
97.68 0.01 99.33 0.00 96.71 0.00 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.61 0.05 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2408609073
97.69 0.01 99.33 0.00 96.74 0.03 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.61 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.67317634
97.69 0.01 99.33 0.00 96.76 0.03 100.00 0.00 96.79 0.00 98.82 0.00 99.52 0.00 92.61 0.00 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1153838456

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3419586688
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3011055312
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1189739751
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.870777711
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3844117457
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3777765999
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.595418955
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1395814395
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1835001769
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4004335871
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1006580087
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3282451613
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1894180595
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1523315676
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1027252611
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3541755488
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3984755697
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1571166414
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1964840145
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1890452181
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3767934875
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3291602693
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2780148856
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1707213334
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3690753962
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1921016375
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4247579002
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2651837785
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.967966386
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4260422624
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.149195966
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3314973758
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2666513823
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2913155670
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2377236706
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1909341425
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2082644288
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1224256528
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1554789938
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3562038018
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4158184597
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3632271963
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1045556393
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2789457187
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2587679282
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2526986637
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2771767190
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.86607943
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2521283059
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3265719656
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2141829331
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3701437597
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.945725675
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3873221194
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2608451536
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4162098534
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2593944850
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2770275839
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1343840920
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.39041917
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.882629339
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.4198761035
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3262766265
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3581617951
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2137519233
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1575737427
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3582784346
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4117194927
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2490194201
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.84482344
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2518066721
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.170897922
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.491568045
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2853593545
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.899750641
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.295697614
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3124940422
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.379975508
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4126067315
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1251333535
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.797526594
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2761120956
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2508369824
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1555193484
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2165660236
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2270590729
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1573117778
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.297368876
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3429473607
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.108258918
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1852556859
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/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3976092314
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1038070498
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4219913450
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3343105127
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3329911831
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3302612448
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1152655097
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3713727960
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2572435277
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.594920537
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1256589089
/workspace/coverage/default/42.sysrst_ctrl_smoke.3165083645
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1066014888
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1781261781
/workspace/coverage/default/43.sysrst_ctrl_alert_test.703793524
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.188393302
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3236077598
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3672009332
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.524616746
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1448601040
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.973511612
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1895974580
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.4170567193
/workspace/coverage/default/43.sysrst_ctrl_smoke.2119185259
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2166898268
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1000560405
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1918527537
/workspace/coverage/default/44.sysrst_ctrl_alert_test.866462600
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2061667514
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.714000316
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2415633324
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2127918068
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4386014
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2269689247
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1924379687
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3945958444
/workspace/coverage/default/44.sysrst_ctrl_smoke.95126659
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3657765308
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3741037708
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3117409076
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3342002261
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1331696253
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1942377508
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1289549225
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.466196954
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1411920773
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4157714739
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1137220680
/workspace/coverage/default/45.sysrst_ctrl_smoke.2878013695
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4110786903
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.949419861
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.74454529
/workspace/coverage/default/46.sysrst_ctrl_alert_test.236563758
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1378257940
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2823561173
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2487198168
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3132254413
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.902008256
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.660631324
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.517933675
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3871326872
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.153950868
/workspace/coverage/default/46.sysrst_ctrl_smoke.706773640
/workspace/coverage/default/46.sysrst_ctrl_stress_all.4004858451
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3158219394
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1941041544
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.908078069
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3616393747
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2981966957
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1362659290
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3010682055
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3738190185
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3029016376
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3322910579
/workspace/coverage/default/47.sysrst_ctrl_smoke.1008281691
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3063105179
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1831321821
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.398565009
/workspace/coverage/default/48.sysrst_ctrl_alert_test.37171311
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1792639001
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3511491638
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2735033432
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3422391172
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2222658699
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.244061605
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3896390234
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2845809204
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1555281048
/workspace/coverage/default/48.sysrst_ctrl_smoke.3492262485
/workspace/coverage/default/48.sysrst_ctrl_stress_all.4134707809
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1231670585
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1793585025
/workspace/coverage/default/49.sysrst_ctrl_alert_test.404070021
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2738710765
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.96225263
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.801278989
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1596447650
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.944413532
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3561309159
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2708637535
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.659780040
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.421047254
/workspace/coverage/default/49.sysrst_ctrl_smoke.2805372989
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2740800512
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2692390888
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2312246912
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1414140059
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2524781275
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.576435800
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.422087731
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.834687783
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2811058054
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3035016838
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3300246278
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3675154671
/workspace/coverage/default/5.sysrst_ctrl_smoke.2624590620
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3321351665
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2152199535
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.41913326
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.339124799
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.617826442
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1104528335
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2582668757
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.640272742
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3040025537
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1391290298
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1959691420
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.4085321064
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1007069115
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1037582322
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3809402933
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.4130770528
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1319644616
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2824920450
/workspace/coverage/default/6.sysrst_ctrl_smoke.1547632504
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3361156617
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.975865250
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.995503013
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.134892231
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1378221717
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.963856563
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2701124319
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2871736701
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2954734555
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.4140953016
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.61328009
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2702189554
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.354305149
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3103246851
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1418917587
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2336580918
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3987677261
/workspace/coverage/default/7.sysrst_ctrl_smoke.3243620308
/workspace/coverage/default/7.sysrst_ctrl_stress_all.814888362
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3886234446
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.680261265
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2823007602
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1230717142
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1565027914
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2210357824
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2368023179
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.837537379
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2530650462
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2882489994
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4261014176
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1054880450
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1759590979
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1703417439
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3075971552
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2392714663
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3372302540
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3631550266
/workspace/coverage/default/8.sysrst_ctrl_smoke.1752133244
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1230163588
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3003400864
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3825976717
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.301323401
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1197967138
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3799493151
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3666939350
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3313447343
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3576831948
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1442766642
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2684541053
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2829006142
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.246335794
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3624983296
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2156706979
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.72385365
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1421821720
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3788651974
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1795000367
/workspace/coverage/default/9.sysrst_ctrl_smoke.3307046191
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3409121917
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2342629388
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3601657347
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1270182406
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3380793467
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1593235514
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.226681931
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.285985779
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3735674515
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1258163454



Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3422391172 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:03 PM PDT 24 2899528339 ps
T5 /workspace/coverage/default/38.sysrst_ctrl_stress_all.1623993886 Jul 26 04:56:30 PM PDT 24 Jul 26 05:00:27 PM PDT 24 188996766325 ps
T6 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3737647063 Jul 26 04:56:48 PM PDT 24 Jul 26 05:01:03 PM PDT 24 93601410710 ps
T20 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.306906143 Jul 26 04:55:59 PM PDT 24 Jul 26 04:56:03 PM PDT 24 2517706688 ps
T21 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.201684235 Jul 26 04:56:30 PM PDT 24 Jul 26 04:56:38 PM PDT 24 2613960767 ps
T1 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.926036891 Jul 26 04:55:56 PM PDT 24 Jul 26 04:56:21 PM PDT 24 97412915707 ps
T14 /workspace/coverage/default/46.sysrst_ctrl_stress_all.4004858451 Jul 26 04:56:46 PM PDT 24 Jul 26 04:56:52 PM PDT 24 11769183366 ps
T2 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.4261014176 Jul 26 04:55:25 PM PDT 24 Jul 26 04:57:44 PM PDT 24 115106262699 ps
T15 /workspace/coverage/default/7.sysrst_ctrl_alert_test.2871736701 Jul 26 04:55:26 PM PDT 24 Jul 26 04:55:29 PM PDT 24 2039361695 ps
T3 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2803903 Jul 26 04:55:27 PM PDT 24 Jul 26 04:55:52 PM PDT 24 69102511696 ps
T16 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2368023179 Jul 26 04:56:51 PM PDT 24 Jul 26 04:58:32 PM PDT 24 40327984475 ps
T17 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1795000367 Jul 26 04:55:39 PM PDT 24 Jul 26 04:55:45 PM PDT 24 2513774270 ps
T18 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.517933675 Jul 26 04:56:40 PM PDT 24 Jul 26 04:56:47 PM PDT 24 2460586401 ps
T7 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1505348682 Jul 26 04:55:39 PM PDT 24 Jul 26 04:57:30 PM PDT 24 232365995645 ps
T19 /workspace/coverage/default/27.sysrst_ctrl_smoke.2748563263 Jul 26 04:56:04 PM PDT 24 Jul 26 04:56:06 PM PDT 24 2133949185 ps
T44 /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.499040672 Jul 26 04:56:23 PM PDT 24 Jul 26 04:56:32 PM PDT 24 3115846012 ps
T28 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2392714663 Jul 26 04:55:27 PM PDT 24 Jul 26 04:55:29 PM PDT 24 2516673929 ps
T8 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4057682777 Jul 26 04:56:19 PM PDT 24 Jul 26 04:56:24 PM PDT 24 3082702516 ps
T9 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.39307590 Jul 26 04:56:30 PM PDT 24 Jul 26 04:56:32 PM PDT 24 4064663141 ps
T10 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.944413532 Jul 26 04:56:56 PM PDT 24 Jul 26 04:57:08 PM PDT 24 6291835553 ps
T51 /workspace/coverage/default/33.sysrst_ctrl_stress_all.1201644316 Jul 26 04:56:16 PM PDT 24 Jul 26 04:56:47 PM PDT 24 11288000522 ps
T45 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1015160732 Jul 26 04:56:36 PM PDT 24 Jul 26 04:57:38 PM PDT 24 24763466541 ps
T11 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2397629558 Jul 26 04:56:44 PM PDT 24 Jul 26 04:56:52 PM PDT 24 3090201038 ps
T12 /workspace/coverage/default/11.sysrst_ctrl_stress_all.437614244 Jul 26 04:55:45 PM PDT 24 Jul 26 04:56:03 PM PDT 24 14604891832 ps
T13 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1442766642 Jul 26 04:57:10 PM PDT 24 Jul 26 04:59:28 PM PDT 24 50057129752 ps
T139 /workspace/coverage/default/25.sysrst_ctrl_alert_test.2187225034 Jul 26 04:56:08 PM PDT 24 Jul 26 04:56:11 PM PDT 24 2016194049 ps
T140 /workspace/coverage/default/41.sysrst_ctrl_alert_test.2207422690 Jul 26 04:56:31 PM PDT 24 Jul 26 04:56:37 PM PDT 24 2014921136 ps
T46 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.4148381709 Jul 26 04:55:13 PM PDT 24 Jul 26 04:55:20 PM PDT 24 2428865414 ps
T47 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1792639001 Jul 26 04:57:01 PM PDT 24 Jul 26 04:57:04 PM PDT 24 3420908093 ps
T48 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1828604373 Jul 26 04:55:54 PM PDT 24 Jul 26 04:57:46 PM PDT 24 88243623337 ps
T26 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.840730497 Jul 26 04:55:42 PM PDT 24 Jul 26 04:55:50 PM PDT 24 6154019173 ps
T98 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1645316563 Jul 26 04:55:50 PM PDT 24 Jul 26 04:55:55 PM PDT 24 2613013846 ps
T99 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2244796423 Jul 26 04:56:30 PM PDT 24 Jul 26 04:56:37 PM PDT 24 2208086549 ps
T36 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.669716376 Jul 26 04:55:42 PM PDT 24 Jul 26 04:57:35 PM PDT 24 170696451863 ps
T43 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1168376804 Jul 26 04:56:52 PM PDT 24 Jul 26 04:57:40 PM PDT 24 83991569691 ps
T100 /workspace/coverage/default/14.sysrst_ctrl_smoke.2420071815 Jul 26 04:55:42 PM PDT 24 Jul 26 04:55:45 PM PDT 24 2126649060 ps
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T371 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3809402933 Jul 26 04:55:27 PM PDT 24 Jul 26 04:55:35 PM PDT 24 2610071048 ps
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T134 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.733230025 Jul 26 04:56:00 PM PDT 24 Jul 26 04:56:52 PM PDT 24 815963906556 ps
T373 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.935750620 Jul 26 04:55:54 PM PDT 24 Jul 26 04:56:07 PM PDT 24 4821597862 ps
T275 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3626062044 Jul 26 04:55:39 PM PDT 24 Jul 26 04:55:42 PM PDT 24 2465987071 ps
T374 /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.660631324 Jul 26 04:56:53 PM PDT 24 Jul 26 04:56:56 PM PDT 24 2636244938 ps
T213 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2351812327 Jul 26 04:55:13 PM PDT 24 Jul 26 04:56:18 PM PDT 24 94842499249 ps
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T376 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2334636962 Jul 26 04:55:38 PM PDT 24 Jul 26 04:55:40 PM PDT 24 2691148171 ps
T377 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3871326872 Jul 26 04:56:54 PM PDT 24 Jul 26 04:56:59 PM PDT 24 2018200067 ps
T136 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.615471581 Jul 26 04:55:43 PM PDT 24 Jul 26 04:55:51 PM PDT 24 3422667160 ps
T364 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3631550266 Jul 26 04:55:26 PM PDT 24 Jul 26 04:55:28 PM PDT 24 2532157936 ps
T363 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3984012591 Jul 26 04:55:59 PM PDT 24 Jul 26 04:56:02 PM PDT 24 2525403626 ps
T64 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1062965480 Jul 26 04:56:28 PM PDT 24 Jul 26 04:56:35 PM PDT 24 5449885595 ps
T378 /workspace/coverage/default/25.sysrst_ctrl_stress_all.3163257872 Jul 26 04:56:01 PM PDT 24 Jul 26 04:56:26 PM PDT 24 9300904114 ps
T224 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.576435800 Jul 26 04:55:38 PM PDT 24 Jul 26 04:57:24 PM PDT 24 167208940495 ps
T379 /workspace/coverage/default/19.sysrst_ctrl_alert_test.1005219357 Jul 26 04:55:54 PM PDT 24 Jul 26 04:55:55 PM PDT 24 2067202498 ps
T380 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.4123402601 Jul 26 04:56:10 PM PDT 24 Jul 26 04:56:16 PM PDT 24 2205335322 ps
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T382 /workspace/coverage/default/26.sysrst_ctrl_alert_test.3117439305 Jul 26 04:56:03 PM PDT 24 Jul 26 04:56:05 PM PDT 24 2041222833 ps
T147 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2358058725 Jul 26 04:56:23 PM PDT 24 Jul 26 04:56:51 PM PDT 24 11897693215 ps
T383 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3112583269 Jul 26 04:55:58 PM PDT 24 Jul 26 04:56:02 PM PDT 24 2615005309 ps
T384 /workspace/coverage/default/20.sysrst_ctrl_stress_all.1629451030 Jul 26 04:56:06 PM PDT 24 Jul 26 04:56:12 PM PDT 24 8722611851 ps
T385 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3561309159 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:07 PM PDT 24 2726387092 ps
T386 /workspace/coverage/default/49.sysrst_ctrl_alert_test.404070021 Jul 26 04:56:53 PM PDT 24 Jul 26 04:56:58 PM PDT 24 2010708237 ps
T276 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2233276842 Jul 26 04:56:07 PM PDT 24 Jul 26 04:56:10 PM PDT 24 2461827438 ps
T137 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2968805856 Jul 26 04:56:07 PM PDT 24 Jul 26 04:56:16 PM PDT 24 5752018846 ps
T82 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.4085321064 Jul 26 04:55:27 PM PDT 24 Jul 26 04:56:37 PM PDT 24 122944577981 ps
T387 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3082241029 Jul 26 04:56:15 PM PDT 24 Jul 26 04:56:23 PM PDT 24 2761582397 ps
T277 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.973511612 Jul 26 04:56:31 PM PDT 24 Jul 26 04:56:34 PM PDT 24 2483611405 ps
T388 /workspace/coverage/default/36.sysrst_ctrl_smoke.761326413 Jul 26 04:56:24 PM PDT 24 Jul 26 04:56:25 PM PDT 24 2155756930 ps
T269 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3863416161 Jul 26 04:55:16 PM PDT 24 Jul 26 04:55:19 PM PDT 24 3316128381 ps
T174 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2986612407 Jul 26 04:55:15 PM PDT 24 Jul 26 04:57:22 PM PDT 24 53507992503 ps
T83 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2529241862 Jul 26 04:55:53 PM PDT 24 Jul 26 04:57:26 PM PDT 24 99428237966 ps
T84 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1190207099 Jul 26 04:56:59 PM PDT 24 Jul 26 05:05:31 PM PDT 24 210736565953 ps
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T290 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2091663311 Jul 26 04:55:06 PM PDT 24 Jul 26 04:55:10 PM PDT 24 2515280931 ps
T291 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3419523488 Jul 26 04:56:30 PM PDT 24 Jul 26 04:56:41 PM PDT 24 3966918418 ps
T138 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1663631768 Jul 26 04:55:22 PM PDT 24 Jul 26 04:55:52 PM PDT 24 76303444740 ps
T292 /workspace/coverage/default/16.sysrst_ctrl_alert_test.2713824472 Jul 26 04:55:57 PM PDT 24 Jul 26 04:56:04 PM PDT 24 2013167173 ps
T280 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1549286681 Jul 26 04:56:02 PM PDT 24 Jul 26 04:56:57 PM PDT 24 22370038956 ps
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T284 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3075971552 Jul 26 04:55:27 PM PDT 24 Jul 26 04:55:34 PM PDT 24 2608877375 ps
T285 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2593327980 Jul 26 04:56:19 PM PDT 24 Jul 26 04:57:03 PM PDT 24 17444984056 ps
T286 /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.4007120572 Jul 26 04:55:16 PM PDT 24 Jul 26 04:55:24 PM PDT 24 2611883604 ps
T287 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3400334795 Jul 26 04:56:03 PM PDT 24 Jul 26 04:56:05 PM PDT 24 2673854617 ps
T288 /workspace/coverage/default/4.sysrst_ctrl_alert_test.450127608 Jul 26 04:55:19 PM PDT 24 Jul 26 04:55:24 PM PDT 24 2010417694 ps
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T65 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1173649040 Jul 26 04:56:00 PM PDT 24 Jul 26 04:56:38 PM PDT 24 114863782140 ps
T151 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3651746937 Jul 26 04:55:26 PM PDT 24 Jul 26 04:55:42 PM PDT 24 88697486543 ps
T237 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.146144039 Jul 26 04:56:46 PM PDT 24 Jul 26 04:56:55 PM PDT 24 3626584009 ps
T238 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.4232776350 Jul 26 04:55:39 PM PDT 24 Jul 26 04:55:45 PM PDT 24 2060235648 ps
T239 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.4093619545 Jul 26 04:55:58 PM PDT 24 Jul 26 04:56:04 PM PDT 24 2046928412 ps
T85 /workspace/coverage/default/26.sysrst_ctrl_stress_all.4273908785 Jul 26 04:56:11 PM PDT 24 Jul 26 04:57:38 PM PDT 24 132917531342 ps
T240 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.167868990 Jul 26 04:56:01 PM PDT 24 Jul 26 04:56:04 PM PDT 24 4054278950 ps
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T242 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1362659290 Jul 26 04:56:45 PM PDT 24 Jul 26 04:56:54 PM PDT 24 3237200632 ps
T243 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.590709947 Jul 26 04:55:20 PM PDT 24 Jul 26 04:55:23 PM PDT 24 5091501299 ps
T214 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2024737622 Jul 26 04:56:49 PM PDT 24 Jul 26 05:00:30 PM PDT 24 84394317832 ps
T66 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2337658218 Jul 26 04:55:14 PM PDT 24 Jul 26 04:55:18 PM PDT 24 8137484873 ps
T389 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2524781275 Jul 26 04:55:17 PM PDT 24 Jul 26 04:55:25 PM PDT 24 3319261731 ps
T390 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3609014895 Jul 26 04:56:13 PM PDT 24 Jul 26 04:56:20 PM PDT 24 2447093994 ps
T273 /workspace/coverage/default/23.sysrst_ctrl_stress_all.3159686328 Jul 26 04:56:08 PM PDT 24 Jul 26 04:56:14 PM PDT 24 8792256876 ps
T352 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3799493151 Jul 26 04:57:02 PM PDT 24 Jul 26 04:57:16 PM PDT 24 35321150407 ps
T208 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.121050760 Jul 26 04:56:26 PM PDT 24 Jul 26 04:57:13 PM PDT 24 19078395236 ps
T77 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.680261265 Jul 26 04:55:31 PM PDT 24 Jul 26 04:55:33 PM PDT 24 4135576710 ps
T217 /workspace/coverage/default/6.sysrst_ctrl_stress_all.3361156617 Jul 26 04:55:29 PM PDT 24 Jul 26 04:59:14 PM PDT 24 95352515595 ps
T391 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2419764289 Jul 26 04:55:42 PM PDT 24 Jul 26 04:55:48 PM PDT 24 5797339589 ps
T392 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.884346512 Jul 26 04:56:16 PM PDT 24 Jul 26 04:56:23 PM PDT 24 2609711049 ps
T148 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2995672392 Jul 26 04:56:33 PM PDT 24 Jul 26 04:56:35 PM PDT 24 5466405594 ps
T393 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2477792431 Jul 26 04:55:39 PM PDT 24 Jul 26 04:55:47 PM PDT 24 2609935772 ps
T394 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1263973450 Jul 26 04:56:39 PM PDT 24 Jul 26 04:56:41 PM PDT 24 3423913253 ps
T395 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3403612449 Jul 26 04:56:13 PM PDT 24 Jul 26 04:56:15 PM PDT 24 2637407810 ps
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T181 /workspace/coverage/default/43.sysrst_ctrl_stress_all.2166898268 Jul 26 04:56:51 PM PDT 24 Jul 26 04:56:58 PM PDT 24 8072268465 ps
T396 /workspace/coverage/default/16.sysrst_ctrl_smoke.4181837184 Jul 26 04:55:54 PM PDT 24 Jul 26 04:55:56 PM PDT 24 2138438242 ps
T160 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.4045658720 Jul 26 04:56:34 PM PDT 24 Jul 26 04:56:36 PM PDT 24 3553108759 ps
T397 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3923867855 Jul 26 04:55:15 PM PDT 24 Jul 26 04:55:17 PM PDT 24 2271072666 ps
T343 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1054495011 Jul 26 04:55:49 PM PDT 24 Jul 26 05:01:55 PM PDT 24 148753390767 ps
T398 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3195958969 Jul 26 04:56:35 PM PDT 24 Jul 26 04:56:44 PM PDT 24 3039141719 ps
T399 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.78893134 Jul 26 04:55:15 PM PDT 24 Jul 26 04:55:22 PM PDT 24 2508753460 ps
T279 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3831833715 Jul 26 04:55:16 PM PDT 24 Jul 26 04:55:23 PM PDT 24 2515354364 ps
T359 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.668193137 Jul 26 04:56:26 PM PDT 24 Jul 26 04:57:11 PM PDT 24 36669149111 ps
T400 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2799198751 Jul 26 04:55:55 PM PDT 24 Jul 26 04:55:56 PM PDT 24 3837225921 ps
T215 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.860814895 Jul 26 04:56:52 PM PDT 24 Jul 26 04:57:52 PM PDT 24 91592428941 ps
T401 /workspace/coverage/default/44.sysrst_ctrl_stress_all.3657765308 Jul 26 04:56:43 PM PDT 24 Jul 26 04:57:02 PM PDT 24 7022232516 ps
T333 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1688880613 Jul 26 04:56:37 PM PDT 24 Jul 26 04:57:11 PM PDT 24 53812204622 ps
T402 /workspace/coverage/default/15.sysrst_ctrl_alert_test.2974904325 Jul 26 04:55:53 PM PDT 24 Jul 26 04:55:57 PM PDT 24 2018828960 ps
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T103 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2882489994 Jul 26 04:55:26 PM PDT 24 Jul 26 04:55:35 PM PDT 24 3209054934 ps
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T109 /workspace/coverage/default/49.sysrst_ctrl_stress_all.2740800512 Jul 26 04:56:58 PM PDT 24 Jul 26 04:57:20 PM PDT 24 9066407821 ps
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T114 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3334903476 Jul 26 04:58:08 PM PDT 24 Jul 26 04:58:12 PM PDT 24 4429608872 ps
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T184 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3741037708 Jul 26 04:57:03 PM PDT 24 Jul 26 04:57:40 PM PDT 24 754326399354 ps
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T410 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3402702922 Jul 26 04:56:18 PM PDT 24 Jul 26 04:56:24 PM PDT 24 3501049648 ps
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T271 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2558920449 Jul 26 04:55:58 PM PDT 24 Jul 26 04:56:48 PM PDT 24 20302436827 ps
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T75 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.131403187 Jul 26 04:56:00 PM PDT 24 Jul 26 04:56:03 PM PDT 24 4603786428 ps
T419 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1558436018 Jul 26 04:56:01 PM PDT 24 Jul 26 04:56:09 PM PDT 24 2856678996 ps
T420 /workspace/coverage/default/11.sysrst_ctrl_alert_test.415190435 Jul 26 04:55:39 PM PDT 24 Jul 26 04:55:41 PM PDT 24 2030450529 ps
T421 /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1331696253 Jul 26 04:57:11 PM PDT 24 Jul 26 04:57:17 PM PDT 24 3496111486 ps
T186 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3870298367 Jul 26 04:56:01 PM PDT 24 Jul 26 04:57:08 PM PDT 24 53463208518 ps
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T423 /workspace/coverage/default/9.sysrst_ctrl_alert_test.2684541053 Jul 26 04:55:34 PM PDT 24 Jul 26 04:55:39 PM PDT 24 2013107573 ps
T424 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3010682055 Jul 26 04:57:06 PM PDT 24 Jul 26 04:57:10 PM PDT 24 2621273692 ps
T425 /workspace/coverage/default/34.sysrst_ctrl_smoke.514218601 Jul 26 04:56:30 PM PDT 24 Jul 26 04:56:36 PM PDT 24 2112353724 ps
T426 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2960286664 Jul 26 04:56:08 PM PDT 24 Jul 26 04:56:09 PM PDT 24 2695012536 ps
T427 /workspace/coverage/default/17.sysrst_ctrl_alert_test.4225265000 Jul 26 04:55:49 PM PDT 24 Jul 26 04:55:51 PM PDT 24 2035728023 ps
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