Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T5

21

T20

6

T3

9

auto[1]

1112

1

T5

19

T20

14

T3

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T5

9

T20

3

T3

3

from_0to1

501

1

T5

9

T20

4

T3

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T5

22

T20

12

T3

16

auto[1]

1032

1

T5

18

T20

8

T3

4

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T5

17

T20

8

T3

10

auto[1]

1061

1

T5

23

T20

12

T3

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

2

T3

1

T7

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T5

3

T3

2

T7

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T5

1

T20

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T48

1

T41

1

T363

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T3

1

T45

2

T48

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

2

T3

1

T7

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T20

1

T17

1

T7

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T5

3

T7

1

T278

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T5

1

T17

1

T48

3

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T17

1

T45

2

T48

5

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T20

1

T147

2

T174

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T5

2

T20

1

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T5

1

T20

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T5

1

T20

1

T3

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T20

1

T45

1

T48

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T5

2

T17

1

T48

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T5

15

T20

14

T3

8

auto[1]

1112

1

T5

25

T20

6

T3

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

509

1

T5

10

T20

3

T3

6

from_0to1

516

1

T5

10

T20

3

T3

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T5

14

T20

10

T3

8

auto[1]

1073

1

T5

26

T20

10

T3

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T5

15

T20

14

T3

9

auto[1]

1071

1

T5

25

T20

6

T3

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T20

1

T17

1

T45

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T48

4

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T20

1

T17

1

T27

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T5

1

T17

2

T7

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T3

1

T17

1

T7

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T5

1

T3

1

T45

2

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T5

2

T20

2

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T5

1

T3

1

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T20

1

T3

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T3

1

T17

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T5

2

T3

2

T48

2

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T5

6

T3

2

T7

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T5

1

T20

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T5

3

T7

1

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T17

2

T48

3

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T5

1

T3

1

T17

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T5

18

T20

10

T3

9

auto[1]

1105

1

T5

22

T20

10

T3

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T5

13

T20

4

T3

4

from_0to1

525

1

T5

12

T20

3

T3

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T5

14

T20

11

T3

9

auto[1]

1066

1

T5

26

T20

9

T3

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T5

23

T20

13

T3

8

auto[1]

1010

1

T5

17

T20

7

T3

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T3

1

T17

2

T7

3

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T5

2

T3

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T5

3

T20

2

T48

3

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T5

1

T20

1

T45

3

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T5

1

T27

1

T41

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T5

1

T7

1

T278

2

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T5

3

T20

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T5

1

T3

3

T17

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T5

1

T20

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T3

1

T200

2

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T5

4

T3

1

T17

1

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T5

2

T17

1

T7

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T5

2

T3

1

T7

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T7

2

T45

1

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T5

3

T7

1

T48

4

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T5

1

T20

2

T17

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T5

20

T20

9

T3

7

auto[1]

1068

1

T5

20

T20

11

T3

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T5

9

T20

7

T3

5

from_0to1

490

1

T5

10

T20

6

T3

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T5

21

T20

10

T3

7

auto[1]

1067

1

T5

19

T20

10

T3

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T5

22

T20

11

T3

12

auto[1]

981

1

T5

18

T20

9

T3

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T5

2

T20

2

T17

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T5

1

T20

2

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T3

1

T27

2

T200

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T5

1

T48

3

T278

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T5

1

T20

1

T3

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T48

2

T278

1

T364

2

auto[0]

from_0to1

auto[1]

auto[0]

84

1

T5

2

T3

2

T7

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T5

2

T3

1

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T5

2

T20

1

T48

3

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T5

1

T3

1

T7

4

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T5

1

T20

1

T3

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T5

1

T20

1

T3

2

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T20

1

T3

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T5

2

T7

1

T48

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T5

2

T48

1

T42

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T5

1

T20

4

T3

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T5

16

T20

6

T3

12

auto[1]

1089

1

T5

24

T20

14

T3

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T5

10

T20

5

T3

5

from_0to1

507

1

T5

10

T20

5

T3

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T5

20

T20

11

T3

7

auto[1]

1070

1

T5

20

T20

9

T3

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T5

24

T20

10

T3

10

auto[1]

1046

1

T5

16

T20

10

T3

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T20

1

T3

1

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T5

1

T48

2

T27

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T5

2

T7

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T3

2

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T5

4

T7

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T5

2

T20

1

T3

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T20

1

T3

1

T48

5

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T3

1

T17

1

T7

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T5

2

T20

1

T3

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T20

1

T45

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T5

1

T20

1

T3

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T5

3

T20

1

T7

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T5

2

T42

1

T147

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T3

1

T48

3

T27

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T5

1

T20

1

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T5

1

T20

2

T3

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

18

T20

10

T3

6

auto[1]

1064

1

T5

22

T20

10

T3

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T5

11

T20

4

T3

4

from_0to1

492

1

T5

12

T20

4

T3

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T5

22

T20

7

T3

11

auto[1]

1016

1

T5

18

T20

13

T3

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T5

27

T20

12

T3

10

auto[1]

1048

1

T5

13

T20

8

T3

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T5

4

T20

1

T17

2

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T5

2

T17

1

T7

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T3

1

T17

1

T7

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T20

1

T3

1

T7

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T5

1

T3

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T5

1

T17

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T5

2

T200

1

T278

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T20

1

T3

1

T17

2

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T5

1

T7

1

T48

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T48

1

T42

2

T27

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T5

3

T20

1

T3

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T5

1

T20

1

T3

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T5

2

T20

1

T3

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T5

4

T7

2

T48

4

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T5

2

T20

1

T48

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T20

1

T3

1

T17

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T5

26

T20

12

T3

12

auto[1]

1056

1

T5

14

T20

8

T3

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T5

9

T20

6

T3

5

from_0to1

491

1

T5

9

T20

5

T3

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T5

24

T20

9

T3

10

auto[1]

1055

1

T5

16

T20

11

T3

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T5

25

T20

6

T3

12

auto[1]

1091

1

T5

15

T20

14

T3

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

3

T3

1

T48

4

auto[0]

from_1to0

auto[0]

auto[1]

84

1

T5

2

T20

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T5

2

T20

1

T3

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T20

1

T17

1

T7

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T20

1

T48

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T20

1

T3

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T5

3

T20

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

81

1

T5

1

T20

2

T3

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T3

1

T17

1

T45

2

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T5

2

T20

1

T3

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T20

1

T48

1

T200

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T20

1

T3

1

T17

3

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T5

3

T17

1

T48

3

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T7

2

T48

2

T42

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T3

1

T45

1

T42

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T3

1

T17

3

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T5

21

T20

6

T3

13

auto[1]

1079

1

T5

19

T20

14

T3

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T5

10

T20

4

T3

3

from_0to1

511

1

T5

10

T20

4

T3

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T5

19

T20

8

T3

10

auto[1]

1063

1

T5

21

T20

12

T3

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T5

24

T20

7

T3

10

auto[1]

1053

1

T5

16

T20

13

T3

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T5

1

T17

2

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T3

1

T17

1

T7

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T5

3

T17

2

T7

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T5

2

T48

2

T42

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T5

1

T3

1

T7

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T3

1

T17

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T20

1

T3

1

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T5

2

T17

1

T7

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T5

2

T45

2

T27

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T20

2

T48

1

T200

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T5

1

T20

1

T17

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T5

1

T20

1

T3

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T5

2

T17

2

T48

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T5

1

T3

1

T17

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T5

2

T20

1

T17

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T5

1

T20

2

T7

1