Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117804

1

T4

2

T5

120

T6

383

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140548	1			T4	3		T5	157		T6	345
values[0x0]	66110	1			T4	1		T5	65		T6	328
values[0x1]	66431	1			T4	2		T5	63		T6	296

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147520

1

T4

3

T5

140

T6

469

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	988	1			T3	1		T7	7		T43	1
valid_sources[0x01]	1701	1			T3	4		T7	4		T9	1
valid_sources[0x02]	897	1			T2	4		T3	3		T7	3
valid_sources[0x03]	1410	1			T20	1		T21	1		T3	5
valid_sources[0x04]	2213	1			T5	32		T3	3		T7	1
valid_sources[0x05]	890	1			T3	4		T18	1		T7	4
valid_sources[0x06]	1095	1			T5	13		T14	11		T2	1
valid_sources[0x07]	1022	1			T1	1		T3	8		T7	3
valid_sources[0x08]	1159	1			T3	3		T7	6		T51	3
valid_sources[0x09]	923	1			T1	1		T7	1		T13	2
valid_sources[0x0a]	714	1			T3	4		T7	4		T51	1
valid_sources[0x0b]	1528	1			T2	5		T3	3		T7	3
valid_sources[0x0c]	2363	1			T1	1		T2	4		T7	5
valid_sources[0x0d]	852	1			T21	1		T3	14		T18	1
valid_sources[0x0e]	1095	1			T2	7		T3	8		T7	3
valid_sources[0x0f]	1628	1			T20	1		T3	2		T7	5
valid_sources[0x10]	915	1			T15	10		T3	5		T17	123
valid_sources[0x11]	906	1			T14	6		T3	5		T7	6
valid_sources[0x12]	1303	1			T3	6		T7	4		T51	4
valid_sources[0x13]	912	1			T20	1		T1	1		T3	1
valid_sources[0x14]	1612	1			T7	3		T12	1		T13	11
valid_sources[0x15]	1421	1			T3	5		T7	1		T12	2
valid_sources[0x16]	1305	1			T3	4		T7	5		T44	2
valid_sources[0x17]	1099	1			T20	1		T2	4		T7	8
valid_sources[0x18]	881	1			T21	2		T3	1		T7	2
valid_sources[0x19]	710	1			T2	6		T7	8		T13	2
valid_sources[0x1a]	1043	1			T20	2		T3	4		T7	4
valid_sources[0x1b]	857	1			T51	1		T43	5		T33	5
valid_sources[0x1c]	944	1			T5	11		T7	5		T45	6
valid_sources[0x1d]	836	1			T1	1		T7	3		T12	1
valid_sources[0x1e]	1024	1			T2	16		T3	2		T7	5
valid_sources[0x1f]	1436	1			T21	1		T2	4		T3	2
valid_sources[0x20]	983	1			T3	12		T7	4		T51	1
valid_sources[0x21]	709	1			T20	1		T3	3		T7	5
valid_sources[0x22]	975	1			T3	1		T7	2		T12	1
valid_sources[0x23]	1290	1			T20	1		T21	1		T2	23
valid_sources[0x24]	1003	1			T1	1		T3	4		T7	4
valid_sources[0x25]	929	1			T20	1		T7	11		T51	1
valid_sources[0x26]	1994	1			T5	29		T3	10		T7	4
valid_sources[0x27]	956	1			T20	1		T7	1		T12	1
valid_sources[0x28]	787	1			T3	7		T7	11		T28	2
valid_sources[0x29]	1020	1			T4	1		T5	28		T3	3
valid_sources[0x2a]	1315	1			T5	2		T1	1		T7	16
valid_sources[0x2b]	771	1			T2	4		T7	2		T13	10
valid_sources[0x2c]	786	1			T21	1		T3	2		T7	6
valid_sources[0x2d]	887	1			T2	6		T3	1		T18	1
valid_sources[0x2e]	907	1			T7	5		T19	2		T44	1
valid_sources[0x2f]	815	1			T7	5		T12	1		T27	3
valid_sources[0x30]	865	1			T2	8		T3	5		T7	3
valid_sources[0x31]	781	1			T7	2		T12	1		T13	7
valid_sources[0x32]	1220	1			T20	3		T1	2		T3	1
valid_sources[0x33]	950	1			T20	1		T3	8		T7	3
valid_sources[0x34]	981	1			T5	24		T1	1		T2	38
valid_sources[0x35]	1647	1			T20	1		T21	1		T1	1
valid_sources[0x36]	1106	1			T4	2		T3	7		T7	1
valid_sources[0x37]	683	1			T20	1		T7	7		T12	1
valid_sources[0x38]	739	1			T20	1		T3	3		T7	3
valid_sources[0x39]	880	1			T3	10		T28	1		T13	13
valid_sources[0x3a]	1369	1			T3	4		T7	6		T13	5
valid_sources[0x3b]	991	1			T20	1		T2	1		T7	8
valid_sources[0x3c]	1502	1			T5	10		T2	2		T7	4
valid_sources[0x3d]	2330	1			T21	1		T7	3		T13	9
valid_sources[0x3e]	763	1			T20	2		T21	2		T1	1
valid_sources[0x3f]	1510	1			T7	8		T98	1		T36	6
valid_sources[0x40]	747	1			T21	2		T1	1		T3	3
valid_sources[0x41]	838	1			T5	21		T21	3		T3	3
valid_sources[0x42]	1226	1			T20	1		T7	3		T12	2
valid_sources[0x43]	937	1			T20	1		T14	9		T7	4
valid_sources[0x44]	1040	1			T5	3		T3	2		T7	2
valid_sources[0x45]	1437	1			T20	1		T7	5		T43	3
valid_sources[0x46]	921	1			T20	1		T2	12		T15	1
valid_sources[0x47]	724	1			T7	3		T44	1		T13	6
valid_sources[0x48]	605	1			T20	1		T2	4		T7	3
valid_sources[0x49]	781	1			T2	35		T3	1		T7	3
valid_sources[0x4a]	1629	1			T2	1		T7	6		T51	1
valid_sources[0x4b]	839	1			T20	2		T1	1		T3	3
valid_sources[0x4c]	1080	1			T20	1		T3	1		T7	5
valid_sources[0x4d]	856	1			T1	1		T3	5		T7	3
valid_sources[0x4e]	967	1			T5	17		T2	8		T12	1
valid_sources[0x4f]	970	1			T21	1		T7	5		T12	1
valid_sources[0x50]	1188	1			T20	2		T3	5		T18	1
valid_sources[0x51]	919	1			T2	4		T3	3		T7	2
valid_sources[0x52]	1088	1			T7	7		T12	3		T13	11
valid_sources[0x53]	833	1			T18	1		T7	5		T51	1
valid_sources[0x54]	948	1			T20	1		T1	1		T12	1
valid_sources[0x55]	983	1			T20	1		T3	1		T7	8
valid_sources[0x56]	852	1			T4	2		T21	2		T7	2
valid_sources[0x57]	2859	1			T20	2		T3	8		T18	1
valid_sources[0x58]	1538	1			T20	2		T3	5		T7	4
valid_sources[0x59]	1027	1			T20	2		T3	7		T13	5
valid_sources[0x5a]	879	1			T2	8		T3	2		T7	6
valid_sources[0x5b]	968	1			T20	1		T3	2		T18	1
valid_sources[0x5c]	793	1			T3	2		T7	1		T45	35
valid_sources[0x5d]	1512	1			T20	1		T7	2		T13	16
valid_sources[0x5e]	811	1			T3	1		T18	1		T7	8
valid_sources[0x5f]	906	1			T20	2		T2	4		T3	6
valid_sources[0x60]	784	1			T3	2		T7	2		T51	1
valid_sources[0x61]	637	1			T3	1		T18	1		T7	1
valid_sources[0x62]	1155	1			T20	1		T7	5		T12	5
valid_sources[0x63]	951	1			T1	1		T7	1		T13	8
valid_sources[0x64]	999	1			T3	1		T7	4		T12	1
valid_sources[0x65]	692	1			T5	19		T3	2		T7	4
valid_sources[0x66]	1549	1			T7	7		T51	1		T98	7
valid_sources[0x67]	841	1			T20	3		T3	2		T18	1
valid_sources[0x68]	1281	1			T3	3		T7	3		T51	1
valid_sources[0x69]	898	1			T3	5		T7	1		T13	1
valid_sources[0x6a]	1083	1			T5	44		T20	1		T21	1
valid_sources[0x6b]	796	1			T21	1		T3	3		T7	8
valid_sources[0x6c]	858	1			T1	1		T3	1		T7	3
valid_sources[0x6d]	1020	1			T20	6		T2	1		T3	14
valid_sources[0x6e]	1397	1			T7	4		T36	46		T43	3
valid_sources[0x6f]	1010	1			T7	3		T12	1		T13	6
valid_sources[0x70]	704	1			T21	1		T7	4		T12	2
valid_sources[0x71]	1016	1			T20	1		T21	2		T18	1
valid_sources[0x72]	824	1			T3	8		T7	8		T45	13
valid_sources[0x73]	1586	1			T20	1		T18	1		T7	7
valid_sources[0x74]	718	1			T3	10		T7	5		T48	7
valid_sources[0x75]	708	1			T20	1		T3	4		T7	3
valid_sources[0x76]	833	1			T2	10		T3	8		T7	2
valid_sources[0x77]	1019	1			T20	1		T2	5		T3	1
valid_sources[0x78]	1220	1			T7	2		T51	1		T13	6
valid_sources[0x79]	835	1			T21	1		T3	1		T7	3
valid_sources[0x7a]	1044	1			T21	1		T7	2		T43	1
valid_sources[0x7b]	1219	1			T4	1		T7	5		T28	1
valid_sources[0x7c]	1465	1			T1	1		T3	4		T18	1
valid_sources[0x7d]	1116	1			T7	3		T51	3		T45	13
valid_sources[0x7e]	985	1			T7	3		T26	1		T43	3
valid_sources[0x7f]	858	1			T21	1		T7	4		T12	2
valid_sources[0x80]	1730	1			T21	1		T3	9		T44	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63004

1

T4

1

T5

82

T6

170

values[0x0]

all_enables

biggest_size

32139

1

T5

23

T6

134

T20

11

values[0x1]

all_enables

biggest_size

22661

1

T4

1

T5

15

T6

79