Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T45,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T3,T7
1	0	Covered	T5,T6,T20
1	1	Covered	T14,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T45,T48
0	1	Covered	T70,T72,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T45,T48
0	1	Covered	T14,T45,T48
1	0	Covered	T52,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T45,T48
1	-	Covered	T14,T45,T48

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T3,T7
DetectSt	168	Covered	T14,T45,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T14,T45,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T45,T48
DebounceSt->IdleSt	163	Covered	T14,T3,T7
DetectSt->IdleSt	186	Covered	T70,T72,T94
DetectSt->StableSt	191	Covered	T14,T45,T48
IdleSt->DebounceSt	148	Covered	T14,T3,T7
StableSt->IdleSt	206	Covered	T14,T45,T48

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T44,T45
0	1	Covered	T14,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T45,T48
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T45,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T44,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T70,T72,T94
DetectSt	-	-	-	-	0	1	-	Covered	T14,T45,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T45,T48
StableSt	-	-	-	-	-	-	0	Covered	T14,T45,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	294	0	0
CntIncr_A	6272770	59876	0	0
CntNoWrap_A	6272770	5611664	0	0
DetectStDropOut_A	6272770	4	0	0
DetectedOut_A	6272770	875	0	0
DetectedPulseOut_A	6272770	131	0	0
DisabledIdleSt_A	6272770	5545368	0	0
DisabledNoDetection_A	6272770	5547667	0	0
EnterDebounceSt_A	6272770	164	0	0
EnterDetectSt_A	6272770	135	0	0
EnterStableSt_A	6272770	131	0	0
PulseIsPulse_A	6272770	131	0	0
StayInStableSt	6272770	744	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	6823	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	129	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	294
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	3
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T27	0	1
T37	0	2
T42	0	2
T44	623	1
T45	0	4
T47	0	1
T48	0	13
T53	0	4
T80	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	59876
T2	23021	0
T3	13820	1
T7	46472	3427
T14	2353	132
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T27	0	38
T37	0	13
T42	0	27
T44	623	30
T45	0	135
T47	0	58
T48	0	292

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611664
T1	19483	19082
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	346
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6272770	4
T70	740	1
T71	17239	0
T72	0	1
T76	5415	0
T94	0	1
T97	0	1
T103	641	0
T104	418	0
T105	424	0
T106	431	0
T107	546	0
T108	438	0
T109	1813	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	875
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	6
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	5
T42	0	2
T44	623	0
T45	0	19
T48	0	44
T53	0	16
T80	0	11
T110	0	19
T111	0	22
T112	0	11

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	131
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	1
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	1
T42	0	1
T44	623	0
T45	0	2
T48	0	6
T53	0	2
T80	0	1
T110	0	2
T111	0	2
T112	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	5545368
T1	19483	19082
T2	23021	22604
T3	13820	7093
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	145
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	5547667
T1	19483	19083
T2	23021	22613
T3	13820	7113
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	149
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	164
T2	23021	0
T3	13820	1
T7	46472	1
T14	2353	2
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T27	0	1
T37	0	1
T42	0	1
T44	623	1
T45	0	2
T47	0	1
T48	0	7

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	135
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	1
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	1
T42	0	1
T44	623	0
T45	0	2
T48	0	6
T53	0	2
T80	0	1
T110	0	2
T111	0	2
T112	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	131
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	1
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	1
T42	0	1
T44	623	0
T45	0	2
T48	0	6
T53	0	2
T80	0	1
T110	0	2
T111	0	2
T112	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	131
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	1
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	1
T42	0	1
T44	623	0
T45	0	2
T48	0	6
T53	0	2
T80	0	1
T110	0	2
T111	0	2
T112	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	744
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	5
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	4
T42	0	1
T44	623	0
T45	0	17
T48	0	38
T53	0	14
T80	0	10
T110	0	17
T111	0	20
T112	0	9

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6272770	6823
T1	19483	3
T2	23021	12
T3	13820	26
T5	37799	9
T6	18720	26
T14	2353	5
T15	407	0
T16	8065	25
T17	0	5
T20	503	4
T21	522	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	129
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	1
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T37	0	1
T42	0	1
T44	623	0
T45	0	2
T48	0	6
T53	0	2
T80	0	1
T110	0	2
T111	0	2
T112	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T27
1	0	Covered	T5,T6,T20
1	1	Covered	T1,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T53
0	1	Covered	T1,T75,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T53
0	1	Unreachable
1	0	Covered	T26,T27,T53

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T27
DetectSt	168	Covered	T1,T26,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T26,T27,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T26,T27
DebounceSt->IdleSt	163	Covered	T1,T75,T116
DetectSt->IdleSt	186	Covered	T1,T75,T78
DetectSt->StableSt	191	Covered	T26,T27,T53
IdleSt->DebounceSt	148	Covered	T1,T26,T27
StableSt->IdleSt	206	Covered	T26,T27,T53

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T27
0	1	Covered	T1,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T26,T27
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T75,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T1,T75,T78
DetectSt	-	-	-	-	0	1	-	Covered	T26,T27,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T27,T53
StableSt	-	-	-	-	-	-	0	Covered	T26,T27,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	190	0	0
CntIncr_A	6272770	66677	0	0
CntNoWrap_A	6272770	5611768	0	0
DetectStDropOut_A	6272770	18	0	0
DetectedOut_A	6272770	32995	0	0
DetectedPulseOut_A	6272770	56	0	0
DisabledIdleSt_A	6272770	5146357	0	0
DisabledNoDetection_A	6272770	5148711	0	0
EnterDebounceSt_A	6272770	117	0	0
EnterDetectSt_A	6272770	74	0	0
EnterStableSt_A	6272770	56	0	0
PulseIsPulse_A	6272770	56	0	0
StayInStableSt	6272770	32939	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	6823	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_sticky_sva.StableStDropOut_A	6272770	342241	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	190
T1	19483	4
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	6
T27	0	2
T53	0	2
T54	0	2
T55	0	2
T63	0	2
T64	0	2
T65	0	2
T66	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	66677
T1	19483	294
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	129
T27	0	93
T53	0	77
T54	0	95
T55	0	93
T63	0	83
T64	0	70
T65	0	56
T66	0	63

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611768
T1	19483	19078
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6272770	18
T1	19483	1
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T75	0	3
T78	0	1
T117	0	2
T118	0	1
T119	0	1
T120	0	3
T121	0	2
T122	0	1
T123	0	2

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	32995
T26	1230	380
T27	0	89
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	37
T54	0	5
T55	0	497
T63	0	7
T64	0	478
T65	0	377
T66	0	407
T77	0	176
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	56
T26	1230	3
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	5146357
T1	19483	52
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	5148711
T1	19483	53
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	117
T1	19483	3
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T27	0	1
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	74
T1	19483	1
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T27	0	1
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	56
T26	1230	3
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	56
T26	1230	3
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	32939
T26	1230	377
T27	0	88
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	36
T54	0	4
T55	0	496
T63	0	6
T64	0	477
T65	0	376
T66	0	406
T77	0	175
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6272770	6823
T1	19483	3
T2	23021	12
T3	13820	26
T5	37799	9
T6	18720	26
T14	2353	5
T15	407	0
T16	8065	25
T17	0	5
T20	503	4
T21	522	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	342241
T26	1230	183
T27	0	32
T36	34138	0
T42	2624	0
T43	16797	0
T53	0	34
T54	0	31
T55	0	265
T63	0	91
T64	0	100
T65	0	87
T66	0	119
T77	0	151
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T20,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T20,T21
1	1	Covered	T5,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T27,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T27
1	0	Covered	T5,T20,T21
1	1	Covered	T1,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T55
0	1	Covered	T26,T54,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T55
0	1	Unreachable
1	0	Covered	T26,T27,T55

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T27
DetectSt	168	Covered	T26,T27,T54
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T26,T27,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T54
DebounceSt->IdleSt	163	Covered	T1,T26,T53
DetectSt->IdleSt	186	Covered	T26,T54,T77
DetectSt->StableSt	191	Covered	T26,T27,T55
IdleSt->DebounceSt	148	Covered	T1,T26,T27
StableSt->IdleSt	206	Covered	T26,T27,T55

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T27
0	1	Covered	T1,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T54
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T26,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T54,T77
DetectSt	-	-	-	-	0	1	-	Covered	T26,T27,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T27,T55
StableSt	-	-	-	-	-	-	0	Covered	T26,T27,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	173	0	0
CntIncr_A	6272770	64274	0	0
CntNoWrap_A	6272770	5611785	0	0
DetectStDropOut_A	6272770	14	0	0
DetectedOut_A	6272770	24871	0	0
DetectedPulseOut_A	6272770	55	0	0
DisabledIdleSt_A	6272770	5146357	0	0
DisabledNoDetection_A	6272770	5148711	0	0
EnterDebounceSt_A	6272770	105	0	0
EnterDetectSt_A	6272770	69	0	0
EnterStableSt_A	6272770	55	0	0
PulseIsPulse_A	6272770	55	0	0
StayInStableSt	6272770	24816	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_sticky_sva.StableStDropOut_A	6272770	371988	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	173
T1	19483	3
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	10
T27	0	2
T53	0	1
T54	0	2
T55	0	2
T63	0	1
T64	0	4
T65	0	2
T66	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	64274
T1	19483	18903
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	518
T27	0	78
T53	0	11
T54	0	30
T55	0	60
T63	0	60
T64	0	76
T65	0	24
T66	0	73

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611785
T1	19483	19079
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6272770	14
T26	1230	2
T36	34138	0
T42	2624	0
T43	16797	0
T54	0	1
T74	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T115	1249	0
T124	0	2
T125	0	3
T126	0	4

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	24871
T26	1230	1
T27	0	71
T36	34138	0
T42	2624	0
T43	16797	0
T55	0	323
T65	0	109
T66	0	377
T71	0	73
T76	0	76
T77	0	151
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	132
T114	0	109
T115	1249	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	55
T26	1230	1
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T55	0	1
T65	0	1
T66	0	1
T71	0	1
T76	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	1
T114	0	1
T115	1249	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	5146357
T1	19483	52
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	5148711
T1	19483	53
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	105
T1	19483	3
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	7
T27	0	1
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	4
T65	0	1
T66	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	69
T26	1230	3
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T54	0	1
T55	0	1
T65	0	1
T66	0	1
T71	0	1
T76	0	1
T77	0	2
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	1
T115	1249	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	55
T26	1230	1
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T55	0	1
T65	0	1
T66	0	1
T71	0	1
T76	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	1
T114	0	1
T115	1249	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	55
T26	1230	1
T27	0	1
T36	34138	0
T42	2624	0
T43	16797	0
T55	0	1
T65	0	1
T66	0	1
T71	0	1
T76	0	1
T77	0	1
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	1
T114	0	1
T115	1249	0

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	24816
T27	2844	70
T33	20040	0
T37	6107	0
T38	1133	0
T49	26255	0
T50	16453	0
T53	6245	0
T55	0	322
T57	494	0
T65	0	108
T66	0	376
T71	0	72
T76	0	75
T77	0	150
T113	0	131
T114	0	108
T127	0	71
T128	522	0
T129	423	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	371988
T26	1230	32
T27	0	62
T36	34138	0
T42	2624	0
T43	16797	0
T55	0	474
T65	0	390
T66	0	149
T71	0	352
T76	0	26
T77	0	65
T98	522	0
T99	442	0
T100	424	0
T101	531	0
T102	402	0
T113	0	28043
T114	0	83
T115	1249	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T26,T27
1	0	Covered	T5,T6,T20
1	1	Covered	T1,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T53
0	1	Covered	T27,T74,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T53
0	1	Unreachable
1	0	Covered	T1,T26,T53

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T26,T27
DetectSt	168	Covered	T1,T26,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T26,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T26,T27
DebounceSt->IdleSt	163	Covered	T63,T66,T127
DetectSt->IdleSt	186	Covered	T27,T74,T75
DetectSt->StableSt	191	Covered	T1,T26,T53
IdleSt->DebounceSt	148	Covered	T1,T26,T27
StableSt->IdleSt	206	Covered	T1,T26,T53

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T26,T27
0	1	Covered	T1,T26,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T26,T27
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T66,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T74,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T26,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T26,T53
StableSt	-	-	-	-	-	-	0	Covered	T1,T26,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	177	0	0
CntIncr_A	6272770	186693	0	0
CntNoWrap_A	6272770	5611781	0	0
DetectStDropOut_A	6272770	13	0	0
DetectedOut_A	6272770	109661	0	0
DetectedPulseOut_A	6272770	61	0	0
DisabledIdleSt_A	6272770	5146357	0	0
DisabledNoDetection_A	6272770	5148711	0	0
EnterDebounceSt_A	6272770	104	0	0
EnterDetectSt_A	6272770	74	0	0
EnterStableSt_A	6272770	61	0	0
PulseIsPulse_A	6272770	61	0	0
StayInStableSt	6272770	109600	0	0
gen_high_event_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_sticky_sva.StableStDropOut_A	6272770	121345	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	177
T1	19483	4
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	6
T27	0	2
T53	0	2
T54	0	2
T55	0	2
T63	0	1
T64	0	2
T65	0	2
T66	0	5

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	186693
T1	19483	52
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	111
T27	0	53
T53	0	54
T54	0	37
T55	0	87
T63	0	83
T64	0	22
T65	0	19
T66	0	220

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611781
T1	19483	19078
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6272770	13
T27	2844	1
T33	20040	0
T37	6107	0
T38	1133	0
T49	26255	0
T50	16453	0
T53	6245	0
T57	494	0
T74	0	1
T75	0	1
T121	0	1
T128	522	0
T129	423	0
T130	0	1
T131	0	5
T132	0	2
T133	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	109661
T1	19483	60
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	377
T53	0	39
T54	0	28
T55	0	725
T64	0	147
T65	0	85
T71	0	312
T77	0	219
T113	0	22827

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	61
T1	19483	2
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T53	0	1
T54	0	1
T55	0	1
T64	0	1
T65	0	1
T71	0	1
T77	0	1
T113	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	5146357
T1	19483	52
T2	23021	22604
T3	13820	7106
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	5148711
T1	19483	53
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	104
T1	19483	2
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T27	0	1
T53	0	1
T54	0	1
T55	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	5

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	74
T1	19483	2
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T27	0	1
T53	0	1
T54	0	1
T55	0	1
T64	0	1
T65	0	1
T77	0	1
T113	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	61
T1	19483	2
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T53	0	1
T54	0	1
T55	0	1
T64	0	1
T65	0	1
T71	0	1
T77	0	1
T113	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	61
T1	19483	2
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	3
T53	0	1
T54	0	1
T55	0	1
T64	0	1
T65	0	1
T71	0	1
T77	0	1
T113	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	109600
T1	19483	58
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	374
T53	0	38
T54	0	27
T55	0	724
T64	0	146
T65	0	84
T71	0	311
T77	0	218
T113	0	22826

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	121345
T1	19483	18906
T2	23021	0
T3	13820	0
T7	46472	0
T14	2353	0
T15	407	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T26	0	242
T53	0	70
T54	0	73
T55	0	50
T64	0	490
T65	0	426
T71	0	42
T77	0	105
T113	0	45

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T42
0	1	Covered	T3
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T42
0	1	Covered	T10,T42,T38
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T42
1	-	Covered	T10,T42,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T10
DetectSt	168	Covered	T3,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T10,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T10
DebounceSt->IdleSt	163	Covered	T38,T134,T68
DetectSt->IdleSt	186	Covered	T3
DetectSt->StableSt	191	Covered	T9,T10,T42
IdleSt->DebounceSt	148	Covered	T3,T9,T10
StableSt->IdleSt	206	Covered	T10,T42,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T3
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T42,T38
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	95	0	0
CntIncr_A	6272770	168178	0	0
CntNoWrap_A	6272770	5611863	0	0
DetectStDropOut_A	6272770	1	0	0
DetectedOut_A	6272770	57478	0	0
DetectedPulseOut_A	6272770	45	0	0
DisabledIdleSt_A	6272770	4985343	0	0
DisabledNoDetection_A	6272770	4987641	0	0
EnterDebounceSt_A	6272770	49	0	0
EnterDetectSt_A	6272770	46	0	0
EnterStableSt_A	6272770	45	0	0
PulseIsPulse_A	6272770	45	0	0
StayInStableSt	6272770	57404	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	95
T3	13820	2
T7	46472	0
T8	616	0
T9	812	2
T10	0	2
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T38	0	3
T39	0	2
T41	0	2
T42	0	2
T44	623	0
T134	0	1
T135	0	4
T136	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	168178
T3	13820	81
T7	46472	0
T8	616	0
T9	812	78
T10	0	100
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T38	0	184
T39	0	17
T41	0	43
T42	0	19
T44	623	0
T134	0	34159
T135	0	86
T136	0	23

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611863
T1	19483	19082
T2	23021	22604
T3	13820	7104
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6272770	1
T3	13820	1
T7	46472	0
T8	616	0
T9	812	0
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T44	623	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	57478
T9	812	45
T10	1258	73
T11	617	0
T12	2921	0
T13	10011	0
T38	0	24
T39	0	44
T41	0	119
T42	0	119
T45	4952	0
T46	486	0
T51	2257	0
T135	0	114
T136	0	95
T137	0	57
T138	0	157
T139	403	0
T140	402	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	45
T9	812	1
T10	1258	1
T11	617	0
T12	2921	0
T13	10011	0
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T45	4952	0
T46	486	0
T51	2257	0
T135	0	2
T136	0	1
T137	0	1
T138	0	1
T139	403	0
T140	402	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	4985343
T1	19483	19082
T2	23021	22604
T3	13820	6522
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	4987641
T1	19483	19083
T2	23021	22613
T3	13820	6542
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	49
T3	13820	1
T7	46472	0
T8	616	0
T9	812	1
T10	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T38	0	2
T39	0	1
T41	0	1
T42	0	1
T44	623	0
T134	0	1
T135	0	2
T136	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	46
T3	13820	1
T7	46472	0
T8	616	0
T9	812	1
T10	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T44	623	0
T135	0	2
T136	0	1
T137	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	45
T9	812	1
T10	1258	1
T11	617	0
T12	2921	0
T13	10011	0
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T45	4952	0
T46	486	0
T51	2257	0
T135	0	2
T136	0	1
T137	0	1
T138	0	1
T139	403	0
T140	402	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	45
T9	812	1
T10	1258	1
T11	617	0
T12	2921	0
T13	10011	0
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T45	4952	0
T46	486	0
T51	2257	0
T135	0	2
T136	0	1
T137	0	1
T138	0	1
T139	403	0
T140	402	0

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	57404
T9	812	43
T10	1258	72
T11	617	0
T12	2921	0
T13	10011	0
T38	0	23
T39	0	42
T41	0	117
T42	0	118
T45	4952	0
T46	486	0
T51	2257	0
T135	0	111
T136	0	94
T137	0	55
T138	0	155
T139	403	0
T140	402	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	15
T10	1258	1
T11	617	0
T12	2921	0
T13	10011	0
T38	0	1
T42	0	1
T45	4952	0
T46	486	0
T47	684	0
T51	2257	0
T135	0	1
T136	0	1
T139	403	0
T140	402	0
T141	0	1
T142	0	3
T143	0	1
T144	0	1
T145	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T5,T6,T20
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T8,T9
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T3,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T142,T68,T130
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T9

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T130,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	128	0	0
CntIncr_A	6272770	171885	0	0
CntNoWrap_A	6272770	5611830	0	0
DetectStDropOut_A	6272770	0	0	0
DetectedOut_A	6272770	189080	0	0
DetectedPulseOut_A	6272770	62	0	0
DisabledIdleSt_A	6272770	5100603	0	0
DisabledNoDetection_A	6272770	5102910	0	0
EnterDebounceSt_A	6272770	66	0	0
EnterDetectSt_A	6272770	62	0	0
EnterStableSt_A	6272770	62	0	0
PulseIsPulse_A	6272770	62	0	0
StayInStableSt	6272770	188996	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	2631	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	39	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6272770	128
T3	13820	4
T7	46472	0
T8	616	2
T9	812	2
T10	0	4
T11	0	2
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	2
T38	0	6
T40	0	2
T41	0	2
T42	0	4
T44	623	0

CntIncr_A

Name	Attempts	Real Successes
Total	6272770	171885
T3	13820	160
T7	46472	0
T8	616	31
T9	812	78
T10	0	200
T11	0	64
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	44
T38	0	276
T40	0	20
T41	0	43
T42	0	38
T44	623	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	6272770	5611830
T1	19483	19082
T2	23021	22604
T3	13820	7102
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6272770	189080
T3	13820	305
T7	46472	0
T8	616	1
T9	812	201
T10	0	319
T11	0	38
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	179
T38	0	124
T40	0	41
T41	0	42
T42	0	47
T44	623	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6272770	62
T3	13820	2
T7	46472	0
T8	616	1
T9	812	1
T10	0	2
T11	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	3
T40	0	1
T41	0	1
T42	0	2
T44	623	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6272770	5100603
T1	19483	19082
T2	23021	22604
T3	13820	6423
T4	580	179
T5	37799	35394
T6	18720	18307
T14	2353	349
T15	407	6
T20	503	102
T21	522	121

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6272770	5102910
T1	19483	19083
T2	23021	22613
T3	13820	6443
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6272770	66
T3	13820	2
T7	46472	0
T8	616	1
T9	812	1
T10	0	2
T11	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	3
T40	0	1
T41	0	1
T42	0	2
T44	623	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6272770	62
T3	13820	2
T7	46472	0
T8	616	1
T9	812	1
T10	0	2
T11	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	3
T40	0	1
T41	0	1
T42	0	2
T44	623	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	6272770	62
T3	13820	2
T7	46472	0
T8	616	1
T9	812	1
T10	0	2
T11	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	3
T40	0	1
T41	0	1
T42	0	2
T44	623	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6272770	62
T3	13820	2
T7	46472	0
T8	616	1
T9	812	1
T10	0	2
T11	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	3
T40	0	1
T41	0	1
T42	0	2
T44	623	0

StayInStableSt

Name	Attempts	Real Successes
Total	6272770	188996
T3	13820	302
T7	46472	0
T8	616	0
T9	812	200
T10	0	316
T11	0	36
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	178
T38	0	120
T40	0	39
T41	0	41
T42	0	44
T44	623	0
T135	0	78

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6272770	2631
T1	19483	0
T2	23021	0
T3	13820	20
T5	37799	17
T6	18720	0
T7	0	22
T14	2353	5
T15	407	0
T16	8065	0
T17	0	5
T18	0	5
T19	0	2
T20	503	6
T21	522	4
T28	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6272770	5614314
T1	19483	19083
T2	23021	22613
T3	13820	7127
T4	580	180
T5	37799	35399
T6	18720	18314
T14	2353	353
T15	407	7
T20	503	103
T21	522	122

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6272770	39
T3	13820	1
T7	46472	0
T8	616	1
T9	812	1
T10	0	1
T16	8065	0
T17	502	0
T18	492	0
T19	426	0
T28	503	0
T37	0	1
T38	0	2
T41	0	1
T42	0	1
T44	623	0
T135	0	2
T147	0	1

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr