Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T41
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T11
1	-	Covered	T3,T9,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T148,T68,T149
DetectSt->IdleSt	186	Covered	T76
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T3,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T76
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T41
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	95	0	0
CntIncr_A	6272770	159915	0	0
CntNoWrap_A	6272770	5611863	0	0
DetectStDropOut_A	6272770	1	0	0
DetectedOut_A	6272770	135685	0	0
DetectedPulseOut_A	6272770	45	0	0
DisabledIdleSt_A	6272770	5015178	0	0
DisabledNoDetection_A	6272770	5017480	0	0
EnterDebounceSt_A	6272770	49	0	0
EnterDetectSt_A	6272770	46	0	0
EnterStableSt_A	6272770	45	0	0
PulseIsPulse_A	6272770	45	0	0
StayInStableSt	6272770	135619	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	95	0	0
T3	13820	4	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	2	0	0
T11	0	2	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	6	0	0
T44	623	0	0	0
T135	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T147	0	4	0	0
T150	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	159915	0	0
T3	13820	162	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	78	0	0
T11	0	64	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	129	0	0
T44	623	0	0	0
T135	0	43	0	0
T137	0	99	0	0
T138	0	17	0	0
T147	0	88	0	0
T150	0	46	0	0
T151	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611863	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7102	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1	0	0
T76	5415	1	0	0
T114	885	0	0	0
T152	454	0	0	0
T153	501	0	0	0
T154	506	0	0	0
T155	502	0	0	0
T156	502	0	0	0
T157	29516	0	0	0
T158	4408	0	0	0
T159	5956	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	135685	0	0
T3	13820	83	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	43	0	0
T11	0	38	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	123	0	0
T44	623	0	0	0
T135	0	89	0	0
T137	0	51	0	0
T138	0	87	0	0
T147	0	84	0	0
T150	0	41	0	0
T151	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	45	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T11	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	3	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5015178	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	6522	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5017480	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	6542	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	49	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T11	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	3	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	46	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T11	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	3	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	45	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T11	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	3	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	45	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T11	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	3	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T147	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	135619	0	0
T3	13820	81	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	42	0	0
T11	0	36	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	119	0	0
T44	623	0	0	0
T135	0	88	0	0
T137	0	50	0	0
T138	0	86	0	0
T147	0	81	0	0
T150	0	39	0	0
T151	0	58	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	23	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T41	0	2	0	0
T44	623	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T142	0	3	0	0
T147	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T162,T163,T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T11
1	-	Covered	T3,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T11
DetectSt	168	Covered	T3,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T11
DebounceSt->IdleSt	163	Covered	T3,T68,T165
DetectSt->IdleSt	186	Covered	T162,T163,T164
DetectSt->StableSt	191	Covered	T3,T8,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T11
StableSt->IdleSt	206	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T162,T163,T164
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	153	0	0
CntIncr_A	6272770	98124	0	0
CntNoWrap_A	6272770	5611805	0	0
DetectStDropOut_A	6272770	3	0	0
DetectedOut_A	6272770	102992	0	0
DetectedPulseOut_A	6272770	72	0	0
DisabledIdleSt_A	6272770	5297307	0	0
DisabledNoDetection_A	6272770	5299605	0	0
EnterDebounceSt_A	6272770	78	0	0
EnterDetectSt_A	6272770	75	0	0
EnterStableSt_A	6272770	72	0	0
PulseIsPulse_A	6272770	72	0	0
StayInStableSt	6272770	102888	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	3032	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	153	0	0
T3	13820	5	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	623	0	0	0
T134	0	4	0	0
T135	0	4	0	0
T136	0	4	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	98124	0	0
T3	13820	243	0	0
T7	46472	0	0	0
T8	616	31	0	0
T9	812	0	0	0
T11	0	64	0	0
T12	0	85	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	17	0	0
T42	0	19	0	0
T44	623	0	0	0
T134	0	68318	0	0
T135	0	86	0	0
T136	0	46	0	0
T166	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611805	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7101	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	3	0	0
T95	13425	0	0	0
T96	20417	0	0	0
T120	1055	0	0	0
T162	952	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T167	411	0	0	0
T168	416	0	0	0
T169	496	0	0	0
T170	202002	0	0	0
T171	521	0	0	0
T172	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	102992	0	0
T3	13820	146	0	0
T7	46472	0	0	0
T8	616	41	0	0
T9	812	0	0	0
T11	0	41	0	0
T12	0	4	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	73	0	0
T42	0	139	0	0
T44	623	0	0	0
T134	0	26100	0	0
T135	0	150	0	0
T136	0	74	0	0
T166	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	72	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5297307	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	6522	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5299605	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	6542	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	78	0	0
T3	13820	3	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	75	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	72	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	72	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	102888	0	0
T3	13820	143	0	0
T7	46472	0	0	0
T8	616	40	0	0
T9	812	0	0	0
T11	0	40	0	0
T12	0	3	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	71	0	0
T42	0	138	0	0
T44	623	0	0	0
T134	0	26097	0	0
T135	0	147	0	0
T136	0	72	0	0
T166	0	130	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	3032	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	25	0	0
T4	580	2	0	0
T5	37799	23	0	0
T6	18720	0	0	0
T7	0	22	0	0
T14	2353	3	0	0
T15	407	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	2	0	0
T20	503	5	0	0
T21	522	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	39	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T42	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T20
1	1	Covered	T5,T6,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T40,T41
1	0	Covered	T5,T6,T20
1	1	Covered	T10,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T41
0	1	Covered	T159,T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T41
0	1	Covered	T10,T41,T135
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T41
1	-	Covered	T10,T41,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T40,T41
DetectSt	168	Covered	T10,T40,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T41
DebounceSt->IdleSt	163	Covered	T135,T68,T173
DetectSt->IdleSt	186	Covered	T159,T163
DetectSt->StableSt	191	Covered	T10,T40,T41
IdleSt->DebounceSt	148	Covered	T10,T40,T41
StableSt->IdleSt	206	Covered	T10,T41,T135

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T41
0	1	Covered	T10,T40,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T135,T173,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T40,T41
DetectSt	-	-	-	-	1	-	-	Covered	T159,T163
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T135
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	149	0	0
CntIncr_A	6272770	64314	0	0
CntNoWrap_A	6272770	5611809	0	0
DetectStDropOut_A	6272770	2	0	0
DetectedOut_A	6272770	151335	0	0
DetectedPulseOut_A	6272770	70	0	0
DisabledIdleSt_A	6272770	5296430	0	0
DisabledNoDetection_A	6272770	5298727	0	0
EnterDebounceSt_A	6272770	77	0	0
EnterDetectSt_A	6272770	72	0	0
EnterStableSt_A	6272770	70	0	0
PulseIsPulse_A	6272770	70	0	0
StayInStableSt	6272770	151236	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	149	0	0
T10	1258	4	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	2	0	0
T134	0	2	0	0
T135	0	3	0	0
T136	0	4	0	0
T138	0	4	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	64314	0	0
T10	1258	200	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	17	0	0
T40	0	20	0	0
T41	0	86	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	37	0	0
T134	0	34159	0	0
T135	0	86	0	0
T136	0	46	0	0
T138	0	34	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611809	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	2	0	0
T86	7433	0	0	0
T127	181818	0	0	0
T141	1215	0	0	0
T159	5956	1	0	0
T163	0	1	0	0
T175	550	0	0	0
T176	24075	0	0	0
T177	423	0	0	0
T178	750	0	0	0
T179	402	0	0	0
T180	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	151335	0	0
T10	1258	473	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	73	0	0
T40	0	47	0	0
T41	0	135	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	21	0	0
T134	0	128624	0	0
T135	0	3	0	0
T136	0	175	0	0
T138	0	71	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	70	0	0
T10	1258	2	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5296430	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5298727	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	77	0	0
T10	1258	2	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	2	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	72	0	0
T10	1258	2	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	70	0	0
T10	1258	2	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	70	0	0
T10	1258	2	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	151236	0	0
T10	1258	470	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T39	0	71	0	0
T40	0	45	0	0
T41	0	132	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	20	0	0
T134	0	128622	0	0
T135	0	2	0	0
T136	0	172	0	0
T138	0	69	0	0
T139	403	0	0	0
T140	402	0	0	0
T174	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	40	0	0
T10	1258	1	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T41	0	1	0	0
T45	4952	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T51	2257	0	0	0
T65	0	1	0	0
T71	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T138	0	2	0	0
T139	403	0	0	0
T140	402	0	0	0
T141	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T42
1	0	Covered	T5,T6,T20
1	1	Covered	T3,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T38
0	1	Covered	T3,T37,T38
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T37,T38
1	-	Covered	T3,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T37,T38
DetectSt	168	Covered	T3,T37,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T37,T38
DebounceSt->IdleSt	163	Covered	T166,T183,T145
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T37,T38
IdleSt->DebounceSt	148	Covered	T3,T37,T38
StableSt->IdleSt	206	Covered	T3,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T37,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T37,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T166,T183,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	99	0	0
CntIncr_A	6272770	3339	0	0
CntNoWrap_A	6272770	5611859	0	0
DetectStDropOut_A	6272770	0	0	0
DetectedOut_A	6272770	4386	0	0
DetectedPulseOut_A	6272770	47	0	0
DisabledIdleSt_A	6272770	5427711	0	0
DisabledNoDetection_A	6272770	5430007	0	0
EnterDebounceSt_A	6272770	52	0	0
EnterDetectSt_A	6272770	47	0	0
EnterStableSt_A	6272770	47	0	0
PulseIsPulse_A	6272770	47	0	0
StayInStableSt	6272770	4315	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	6359	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	99	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T44	623	0	0	0
T71	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0
T148	0	4	0	0
T160	0	2	0	0
T166	0	3	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	3339	0	0
T3	13820	80	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	44	0	0
T38	0	92	0	0
T44	623	0	0	0
T71	0	39	0	0
T135	0	86	0	0
T136	0	23	0	0
T148	0	158	0	0
T160	0	23	0	0
T166	0	100	0	0
T181	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611859	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7104	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	4386	0	0
T3	13820	285	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	178	0	0
T38	0	156	0	0
T44	623	0	0	0
T71	0	182	0	0
T135	0	236	0	0
T136	0	1	0	0
T148	0	280	0	0
T160	0	242	0	0
T166	0	41	0	0
T181	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	47	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T148	0	2	0	0
T160	0	1	0	0
T166	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5427711	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	6423	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5430007	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	6443	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	52	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T148	0	2	0	0
T160	0	1	0	0
T166	0	2	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	47	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T148	0	2	0	0
T160	0	1	0	0
T166	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	47	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T148	0	2	0	0
T160	0	1	0	0
T166	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	47	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T135	0	2	0	0
T136	0	1	0	0
T148	0	2	0	0
T160	0	1	0	0
T166	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	4315	0	0
T3	13820	284	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	177	0	0
T38	0	155	0	0
T44	623	0	0	0
T71	0	180	0	0
T135	0	233	0	0
T148	0	277	0	0
T160	0	240	0	0
T166	0	40	0	0
T181	0	79	0	0
T184	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	6359	0	0
T1	19483	3	0	0
T2	23021	13	0	0
T3	13820	17	0	0
T5	37799	11	0	0
T6	18720	27	0	0
T14	2353	2	0	0
T15	407	0	0	0
T16	8065	24	0	0
T17	0	5	0	0
T20	503	5	0	0
T21	522	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	22	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	623	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T20
1	1	Covered	T5,T6,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T5,T6,T20
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T8
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T166
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T11
1	-	Covered	T3,T10,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T8,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T10
DebounceSt->IdleSt	163	Covered	T3,T8,T148
DetectSt->IdleSt	186	Covered	T8
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T8,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T8
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T166
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	142	0	0
CntIncr_A	6272770	53095	0	0
CntNoWrap_A	6272770	5611816	0	0
DetectStDropOut_A	6272770	1	0	0
DetectedOut_A	6272770	20766	0	0
DetectedPulseOut_A	6272770	67	0	0
DisabledIdleSt_A	6272770	5346493	0	0
DisabledNoDetection_A	6272770	5348794	0	0
EnterDebounceSt_A	6272770	74	0	0
EnterDetectSt_A	6272770	68	0	0
EnterStableSt_A	6272770	67	0	0
PulseIsPulse_A	6272770	67	0	0
StayInStableSt	6272770	20672	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	142	0	0
T3	13820	3	0	0
T7	46472	0	0	0
T8	616	3	0	0
T9	812	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	2	0	0
T44	623	0	0	0
T134	0	2	0	0
T136	0	2	0	0
T151	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	53095	0	0
T3	13820	162	0	0
T7	46472	0	0	0
T8	616	62	0	0
T9	812	0	0	0
T10	0	100	0	0
T11	0	64	0	0
T12	0	85	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	17	0	0
T44	623	0	0	0
T134	0	34159	0	0
T136	0	23	0	0
T151	0	15	0	0
T166	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611816	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7103	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1	0	0
T8	616	1	0	0
T9	812	0	0	0
T10	1258	0	0	0
T11	617	0	0	0
T12	2921	0	0	0
T13	10011	0	0	0
T45	4952	0	0	0
T51	2257	0	0	0
T139	403	0	0	0
T140	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	20766	0	0
T3	13820	17	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	198	0	0
T11	0	39	0	0
T12	0	38	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	45	0	0
T44	623	0	0	0
T134	0	44	0	0
T136	0	69	0	0
T148	0	234	0	0
T151	0	81	0	0
T166	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	67	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T136	0	1	0	0
T148	0	2	0	0
T151	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5346493	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	6522	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5348794	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	6542	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	74	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T136	0	1	0	0
T151	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	68	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T136	0	1	0	0
T151	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	67	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T136	0	1	0	0
T148	0	2	0	0
T151	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	67	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	1	0	0
T44	623	0	0	0
T134	0	1	0	0
T136	0	1	0	0
T148	0	2	0	0
T151	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	20672	0	0
T3	13820	16	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	197	0	0
T11	0	37	0	0
T12	0	36	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T39	0	43	0	0
T44	623	0	0	0
T134	0	43	0	0
T136	0	68	0	0
T148	0	231	0	0
T151	0	79	0	0
T166	0	130	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	39	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T44	623	0	0	0
T71	0	1	0	0
T76	0	2	0	0
T134	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T166	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T20
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T5,T6,T20
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Covered	T3,T8,T42
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T10
1	-	Covered	T3,T8,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T8,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T10
DebounceSt->IdleSt	163	Covered	T183,T68,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T10
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T8,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T68
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	83	0	0
CntIncr_A	6272770	28369	0	0
CntNoWrap_A	6272770	5611875	0	0
DetectStDropOut_A	6272770	0	0	0
DetectedOut_A	6272770	56570	0	0
DetectedPulseOut_A	6272770	40	0	0
DisabledIdleSt_A	6272770	5458953	0	0
DisabledNoDetection_A	6272770	5461252	0	0
EnterDebounceSt_A	6272770	43	0	0
EnterDetectSt_A	6272770	40	0	0
EnterStableSt_A	6272770	40	0	0
PulseIsPulse_A	6272770	40	0	0
StayInStableSt	6272770	56514	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6272770	6139	0	0
gen_low_level_sva.LowLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	83	0	0
T3	13820	4	0	0
T7	46472	0	0	0
T8	616	4	0	0
T9	812	0	0	0
T10	0	2	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	4	0	0
T42	0	2	0	0
T44	623	0	0	0
T71	0	2	0	0
T74	0	2	0	0
T161	0	4	0	0
T182	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	28369	0	0
T3	13820	162	0	0
T7	46472	0	0	0
T8	616	62	0	0
T9	812	0	0	0
T10	0	100	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	88	0	0
T42	0	19	0	0
T44	623	0	0	0
T71	0	26	0	0
T74	0	95	0	0
T161	0	100	0	0
T182	0	62	0	0
T187	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611875	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7102	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	56570	0	0
T3	13820	296	0	0
T7	46472	0	0	0
T8	616	81	0	0
T9	812	0	0	0
T10	0	450	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	94	0	0
T42	0	40	0	0
T44	623	0	0	0
T71	0	7	0	0
T74	0	41	0	0
T161	0	215	0	0
T182	0	106	0	0
T187	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	40	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5458953	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	6522	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5461252	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	6542	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	43	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	40	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	40	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	40	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	2	0	0
T9	812	0	0	0
T10	0	1	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T74	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	56514	0	0
T3	13820	293	0	0
T7	46472	0	0	0
T8	616	78	0	0
T9	812	0	0	0
T10	0	448	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	92	0	0
T42	0	39	0	0
T44	623	0	0	0
T71	0	6	0	0
T74	0	39	0	0
T161	0	212	0	0
T182	0	105	0	0
T187	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	6139	0	0
T1	19483	0	0	0
T2	23021	10	0	0
T3	13820	20	0	0
T5	37799	11	0	0
T6	18720	32	0	0
T14	2353	6	0	0
T15	407	0	0	0
T16	8065	21	0	0
T17	0	4	0	0
T18	0	7	0	0
T20	503	5	0	0
T21	522	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	23	0	0
T3	13820	1	0	0
T7	46472	0	0	0
T8	616	1	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T37	0	2	0	0
T42	0	1	0	0
T44	623	0	0	0
T71	0	1	0	0
T142	0	1	0	0
T161	0	1	0	0
T182	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0