Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T16,T13
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T13
1	0	Covered	T6,T13,T43
1	1	Covered	T6,T16,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T13
0	1	Covered	T13,T81,T83
1	0	Covered	T13,T33,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T43
0	1	Covered	T16,T43,T49
1	0	Covered	T73,T52,T207

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T16,T43
1	-	Covered	T16,T43,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T16,T13
DetectSt	168	Covered	T6,T16,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T16,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T16,T13
DebounceSt->IdleSt	163	Covered	T16,T79,T208
DetectSt->IdleSt	186	Covered	T13,T33,T81
DetectSt->StableSt	191	Covered	T6,T16,T43
IdleSt->DebounceSt	148	Covered	T6,T16,T13
StableSt->IdleSt	206	Covered	T6,T16,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T16,T13
0	1	Covered	T6,T16,T13
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T16,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T16,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T16,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T79,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T16,T13
DetectSt	-	-	-	-	1	-	-	Covered	T13,T33,T81
DetectSt	-	-	-	-	0	1	-	Covered	T6,T16,T43
DetectSt	-	-	-	-	0	0	-	Covered	T6,T16,T13
StableSt	-	-	-	-	-	-	1	Covered	T16,T43,T49
StableSt	-	-	-	-	-	-	0	Covered	T6,T16,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	3036	0	0
CntIncr_A	6272770	100006	0	0
CntNoWrap_A	6272770	5608922	0	0
DetectStDropOut_A	6272770	409	0	0
DetectedOut_A	6272770	70221	0	0
DetectedPulseOut_A	6272770	858	0	0
DisabledIdleSt_A	6272770	5184627	0	0
DisabledNoDetection_A	6272770	5186802	0	0
EnterDebounceSt_A	6272770	1543	0	0
EnterDetectSt_A	6272770	1496	0	0
EnterStableSt_A	6272770	858	0	0
PulseIsPulse_A	6272770	858	0	0
StayInStableSt	6272770	69269	0	0
gen_high_event_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	733	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	3036	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	6	0	0
T13	0	20	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	18	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	14	0	0
T43	0	50	0	0
T49	0	20	0	0
T50	0	54	0	0
T60	0	12	0	0
T61	0	2	0	0
T62	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	100006	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	78	0	0
T13	0	776	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	2986	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	457	0	0
T43	0	1775	0	0
T49	0	410	0	0
T50	0	1323	0	0
T60	0	306	0	0
T61	0	21	0	0
T62	0	1062	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5608922	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18301	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	409	0	0
T13	10011	7	0	0
T26	1230	0	0	0
T36	34138	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T48	17648	0	0	0
T81	0	11	0	0
T83	0	12	0	0
T84	0	5	0	0
T87	0	12	0	0
T88	0	3	0	0
T89	0	5	0	0
T98	522	0	0	0
T99	442	0	0	0
T139	403	0	0	0
T140	402	0	0	0
T209	0	8	0	0
T210	0	29	0	0
T211	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	70221	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	610	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	517	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T35	0	1802	0	0
T43	0	2989	0	0
T49	0	941	0	0
T50	0	2636	0	0
T60	0	341	0	0
T61	0	42	0	0
T62	0	1013	0	0
T212	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	858	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	3	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	7	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T35	0	25	0	0
T43	0	25	0	0
T49	0	10	0	0
T50	0	27	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	18	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5184627	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	15005	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5186802	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	15008	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1543	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	3	0	0
T13	0	10	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	12	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	7	0	0
T43	0	25	0	0
T49	0	10	0	0
T50	0	27	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1496	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	3	0	0
T13	0	10	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	7	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	7	0	0
T43	0	25	0	0
T49	0	10	0	0
T50	0	27	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	858	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	3	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	7	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T35	0	25	0	0
T43	0	25	0	0
T49	0	10	0	0
T50	0	27	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	18	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	858	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	3	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	7	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T35	0	25	0	0
T43	0	25	0	0
T49	0	10	0	0
T50	0	27	0	0
T60	0	6	0	0
T61	0	1	0	0
T62	0	18	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	69269	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	604	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	510	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T35	0	1772	0	0
T43	0	2962	0	0
T49	0	927	0	0
T50	0	2605	0	0
T60	0	334	0	0
T61	0	40	0	0
T62	0	993	0	0
T212	0	30	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	733	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T16	8065	7	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	20	0	0
T43	0	23	0	0
T44	623	0	0	0
T49	0	6	0	0
T50	0	23	0	0
T60	0	5	0	0
T62	0	16	0	0
T79	0	8	0	0
T213	0	18	0	0
T214	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T14,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T14,T2
1	0	Covered	T5,T6,T14
1	1	Covered	T6,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T3
0	1	Covered	T48,T82,T85
1	0	Covered	T52,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T69,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T2,T3
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T14,T2
DetectSt	168	Covered	T6,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T2,T3
DebounceSt->IdleSt	163	Covered	T14,T12,T48
DetectSt->IdleSt	186	Covered	T48,T82,T85
DetectSt->StableSt	191	Covered	T6,T2,T3
IdleSt->DebounceSt	148	Covered	T6,T14,T2
StableSt->IdleSt	206	Covered	T6,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T14,T2
0	1	Covered	T6,T14,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T12,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T48,T82,T85
DetectSt	-	-	-	-	0	1	-	Covered	T6,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T6,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T6,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	921	0	0
CntIncr_A	6272770	44523	0	0
CntNoWrap_A	6272770	5611037	0	0
DetectStDropOut_A	6272770	83	0	0
DetectedOut_A	6272770	12132	0	0
DetectedPulseOut_A	6272770	337	0	0
DisabledIdleSt_A	6272770	5266132	0	0
DisabledNoDetection_A	6272770	5267768	0	0
EnterDebounceSt_A	6272770	497	0	0
EnterDetectSt_A	6272770	424	0	0
EnterStableSt_A	6272770	337	0	0
PulseIsPulse_A	6272770	337	0	0
StayInStableSt	6272770	11747	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	285	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	921	0	0
T1	19483	0	0	0
T2	23021	14	0	0
T3	13820	2	0	0
T6	18720	6	0	0
T7	0	14	0	0
T12	0	1	0	0
T14	2353	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	11	0	0
T43	0	8	0	0
T46	0	2	0	0
T48	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	44523	0	0
T1	19483	0	0	0
T2	23021	910	0	0
T3	13820	25	0	0
T6	18720	81	0	0
T7	0	385	0	0
T12	0	20	0	0
T14	2353	20	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	562	0	0
T43	0	336	0	0
T46	0	25	0	0
T48	0	235	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611037	0	0
T1	19483	19082	0	0
T2	23021	22590	0	0
T3	13820	7104	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18301	0	0
T14	2353	348	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	83	0	0
T26	1230	0	0	0
T36	34138	0	0	0
T42	2624	0	0	0
T43	16797	0	0	0
T48	17648	1	0	0
T82	0	8	0	0
T85	0	3	0	0
T86	0	8	0	0
T90	0	9	0	0
T91	0	3	0	0
T92	0	9	0	0
T93	0	2	0	0
T95	0	2	0	0
T96	0	5	0	0
T98	522	0	0	0
T99	442	0	0	0
T100	424	0	0	0
T101	531	0	0	0
T102	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	12132	0	0
T1	19483	0	0	0
T2	23021	239	0	0
T3	13820	3	0	0
T6	18720	176	0	0
T7	0	153	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	82	0	0
T43	0	153	0	0
T46	0	4	0	0
T48	0	12	0	0
T49	0	168	0	0
T50	0	177	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	337	0	0
T1	19483	0	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T6	18720	3	0	0
T7	0	7	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	5	0	0
T43	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5266132	0	0
T1	19483	19082	0	0
T2	23021	18131	0	0
T3	13820	5985	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	17700	0	0
T14	2353	307	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5267768	0	0
T1	19483	19083	0	0
T2	23021	18131	0	0
T3	13820	6003	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	17704	0	0
T14	2353	310	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	497	0	0
T1	19483	0	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T6	18720	3	0	0
T7	0	7	0	0
T12	0	1	0	0
T14	2353	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	6	0	0
T43	0	4	0	0
T46	0	1	0	0
T48	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	424	0	0
T1	19483	0	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T6	18720	3	0	0
T7	0	7	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	5	0	0
T43	0	4	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	337	0	0
T1	19483	0	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T6	18720	3	0	0
T7	0	7	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	5	0	0
T43	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	337	0	0
T1	19483	0	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T6	18720	3	0	0
T7	0	7	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	5	0	0
T43	0	4	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T50	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	11747	0	0
T1	19483	0	0	0
T2	23021	232	0	0
T3	13820	2	0	0
T6	18720	170	0	0
T7	0	146	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T36	0	77	0	0
T43	0	147	0	0
T46	0	3	0	0
T48	0	11	0	0
T49	0	164	0	0
T50	0	169	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	285	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T7	46472	7	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T36	0	5	0	0
T43	0	2	0	0
T44	623	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	4	0	0
T60	0	1	0	0
T80	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T16,T13
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T13
1	0	Covered	T6,T13,T43
1	1	Covered	T6,T16,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T13
0	1	Covered	T13,T49,T50
1	0	Covered	T13,T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T43
0	1	Covered	T6,T16,T43
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T16,T43
1	-	Covered	T6,T16,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T16,T13
DetectSt	168	Covered	T6,T16,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T16,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T16,T13
DebounceSt->IdleSt	163	Covered	T16,T79,T208
DetectSt->IdleSt	186	Covered	T13,T49,T50
DetectSt->StableSt	191	Covered	T6,T16,T43
IdleSt->DebounceSt	148	Covered	T6,T16,T13
StableSt->IdleSt	206	Covered	T6,T16,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T16,T13
0	1	Covered	T6,T16,T13
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T16,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T16,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T16,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T79,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T16,T13
DetectSt	-	-	-	-	1	-	-	Covered	T13,T49,T50
DetectSt	-	-	-	-	0	1	-	Covered	T6,T16,T43
DetectSt	-	-	-	-	0	0	-	Covered	T6,T16,T13
StableSt	-	-	-	-	-	-	1	Covered	T6,T16,T43
StableSt	-	-	-	-	-	-	0	Covered	T6,T16,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	2902	0	0
CntIncr_A	6272770	103002	0	0
CntNoWrap_A	6272770	5609056	0	0
DetectStDropOut_A	6272770	349	0	0
DetectedOut_A	6272770	73303	0	0
DetectedPulseOut_A	6272770	896	0	0
DisabledIdleSt_A	6272770	5185685	0	0
DisabledNoDetection_A	6272770	5187876	0	0
EnterDebounceSt_A	6272770	1479	0	0
EnterDetectSt_A	6272770	1426	0	0
EnterStableSt_A	6272770	896	0	0
PulseIsPulse_A	6272770	896	0	0
StayInStableSt	6272770	72328	0	0
gen_high_event_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	813	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	2902	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	20	0	0
T13	0	54	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	19	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	50	0	0
T35	0	46	0	0
T43	0	46	0	0
T49	0	44	0	0
T50	0	16	0	0
T60	0	36	0	0
T62	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	103002	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	360	0	0
T13	0	2118	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	3297	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	1625	0	0
T35	0	1794	0	0
T43	0	2024	0	0
T49	0	1522	0	0
T50	0	618	0	0
T60	0	1116	0	0
T62	0	752	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5609056	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18287	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	349	0	0
T13	10011	14	0	0
T26	1230	0	0	0
T36	34138	0	0	0
T46	486	0	0	0
T47	684	0	0	0
T48	17648	0	0	0
T49	0	11	0	0
T50	0	1	0	0
T69	0	9	0	0
T81	0	17	0	0
T83	0	4	0	0
T87	0	6	0	0
T88	0	13	0	0
T98	522	0	0	0
T99	442	0	0	0
T139	403	0	0	0
T140	402	0	0	0
T210	0	7	0	0
T215	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	73303	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	1324	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	461	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	2059	0	0
T35	0	1640	0	0
T43	0	1861	0	0
T49	0	3	0	0
T60	0	1739	0	0
T62	0	251	0	0
T84	0	1963	0	0
T213	0	788	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	896	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	10	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	6	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	25	0	0
T35	0	23	0	0
T43	0	23	0	0
T49	0	3	0	0
T60	0	18	0	0
T62	0	16	0	0
T84	0	17	0	0
T213	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5185685	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	14367	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5187876	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	14368	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1479	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	10	0	0
T13	0	27	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	14	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	25	0	0
T35	0	23	0	0
T43	0	23	0	0
T49	0	22	0	0
T50	0	8	0	0
T60	0	18	0	0
T62	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1426	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	10	0	0
T13	0	27	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	6	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	25	0	0
T35	0	23	0	0
T43	0	23	0	0
T49	0	22	0	0
T50	0	8	0	0
T60	0	18	0	0
T62	0	16	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	896	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	10	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	6	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	25	0	0
T35	0	23	0	0
T43	0	23	0	0
T49	0	3	0	0
T60	0	18	0	0
T62	0	16	0	0
T84	0	17	0	0
T213	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	896	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	10	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	6	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	25	0	0
T35	0	23	0	0
T43	0	23	0	0
T49	0	3	0	0
T60	0	18	0	0
T62	0	16	0	0
T84	0	17	0	0
T213	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	72328	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	1309	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	455	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	2028	0	0
T35	0	1615	0	0
T43	0	1835	0	0
T60	0	1715	0	0
T62	0	235	0	0
T84	0	1941	0	0
T213	0	767	0	0
T214	0	2423	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	813	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	5	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	6	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	19	0	0
T35	0	21	0	0
T43	0	20	0	0
T60	0	12	0	0
T62	0	16	0	0
T84	0	11	0	0
T213	0	19	0	0
T214	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T5,T6,T14
1	1	Covered	T6,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T3
0	1	Covered	T3,T216,T217
1	0	Covered	T52,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T7
0	1	Covered	T2,T7,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T2,T7
1	-	Covered	T2,T7,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T2,T3
DetectSt	168	Covered	T6,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T2,T3
DebounceSt->IdleSt	163	Covered	T7,T33,T60
DetectSt->IdleSt	186	Covered	T3,T216,T217
DetectSt->StableSt	191	Covered	T6,T2,T7
IdleSt->DebounceSt	148	Covered	T6,T2,T3
StableSt->IdleSt	206	Covered	T6,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T2,T3
0	1	Covered	T6,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T33,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T3,T216,T217
DetectSt	-	-	-	-	0	1	-	Covered	T6,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T6,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T48
StableSt	-	-	-	-	-	-	0	Covered	T6,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	834	0	0
CntIncr_A	6272770	47823	0	0
CntNoWrap_A	6272770	5611124	0	0
DetectStDropOut_A	6272770	78	0	0
DetectedOut_A	6272770	15111	0	0
DetectedPulseOut_A	6272770	305	0	0
DisabledIdleSt_A	6272770	5271454	0	0
DisabledNoDetection_A	6272770	5273183	0	0
EnterDebounceSt_A	6272770	447	0	0
EnterDetectSt_A	6272770	388	0	0
EnterStableSt_A	6272770	305	0	0
PulseIsPulse_A	6272770	305	0	0
StayInStableSt	6272770	14787	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	282	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	834	0	0
T1	19483	0	0	0
T2	23021	8	0	0
T3	13820	4	0	0
T6	18720	10	0	0
T7	0	17	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	13	0	0
T34	0	4	0	0
T35	0	2	0	0
T43	0	6	0	0
T48	0	2	0	0
T60	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	47823	0	0
T1	19483	0	0	0
T2	23021	420	0	0
T3	13820	311	0	0
T6	18720	185	0	0
T7	0	412	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	500	0	0
T34	0	298	0	0
T35	0	47	0	0
T43	0	183	0	0
T48	0	30	0	0
T60	0	180	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611124	0	0
T1	19483	19082	0	0
T2	23021	22596	0	0
T3	13820	7102	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18297	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	78	0	0
T3	13820	2	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T44	623	0	0	0
T86	0	1	0	0
T91	0	13	0	0
T216	0	2	0	0
T217	0	1	0	0
T218	0	8	0	0
T219	0	7	0	0
T220	0	2	0	0
T221	0	8	0	0
T222	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	15111	0	0
T1	19483	0	0	0
T2	23021	238	0	0
T3	13820	0	0	0
T6	18720	244	0	0
T7	0	380	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	245	0	0
T34	0	10	0	0
T35	0	94	0	0
T43	0	184	0	0
T48	0	21	0	0
T60	0	271	0	0
T223	0	202	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	305	0	0
T1	19483	0	0	0
T2	23021	4	0	0
T3	13820	0	0	0
T6	18720	5	0	0
T7	0	8	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	3	0	0
T48	0	1	0	0
T60	0	5	0	0
T223	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5271454	0	0
T1	19483	19082	0	0
T2	23021	18131	0	0
T3	13820	6107	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	16988	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5273183	0	0
T1	19483	19083	0	0
T2	23021	18131	0	0
T3	13820	6127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	16990	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	447	0	0
T1	19483	0	0	0
T2	23021	4	0	0
T3	13820	2	0	0
T6	18720	5	0	0
T7	0	9	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	7	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	3	0	0
T48	0	1	0	0
T60	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	388	0	0
T1	19483	0	0	0
T2	23021	4	0	0
T3	13820	2	0	0
T6	18720	5	0	0
T7	0	8	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	3	0	0
T48	0	1	0	0
T60	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	305	0	0
T1	19483	0	0	0
T2	23021	4	0	0
T3	13820	0	0	0
T6	18720	5	0	0
T7	0	8	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	3	0	0
T48	0	1	0	0
T60	0	5	0	0
T223	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	305	0	0
T1	19483	0	0	0
T2	23021	4	0	0
T3	13820	0	0	0
T6	18720	5	0	0
T7	0	8	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	3	0	0
T48	0	1	0	0
T60	0	5	0	0
T223	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	14787	0	0
T1	19483	0	0	0
T2	23021	234	0	0
T3	13820	0	0	0
T6	18720	234	0	0
T7	0	372	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	239	0	0
T34	0	8	0	0
T35	0	93	0	0
T43	0	179	0	0
T48	0	20	0	0
T60	0	264	0	0
T223	0	198	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	282	0	0
T2	23021	4	0	0
T3	13820	0	0	0
T7	46472	8	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	0	1	0	0
T44	623	0	0	0
T48	0	1	0	0
T60	0	3	0	0
T223	0	4	0	0
T224	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T16,T13
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T13
1	0	Covered	T6,T13,T43
1	1	Covered	T6,T16,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T13
0	1	Covered	T6,T33,T81
1	0	Covered	T6,T33,T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T13,T43
0	1	Covered	T16,T13,T43
1	0	Covered	T68,T225

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T13,T43
1	-	Covered	T16,T13,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T16,T13
DetectSt	168	Covered	T6,T16,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T16,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T16,T13
DebounceSt->IdleSt	163	Covered	T16,T79,T208
DetectSt->IdleSt	186	Covered	T6,T33,T49
DetectSt->StableSt	191	Covered	T16,T13,T43
IdleSt->DebounceSt	148	Covered	T6,T16,T13
StableSt->IdleSt	206	Covered	T16,T13,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T16,T13
0	1	Covered	T6,T16,T13
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T16,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T16,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T16,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T79,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T16,T13
DetectSt	-	-	-	-	1	-	-	Covered	T6,T33,T49
DetectSt	-	-	-	-	0	1	-	Covered	T16,T13,T43
DetectSt	-	-	-	-	0	0	-	Covered	T6,T16,T13
StableSt	-	-	-	-	-	-	1	Covered	T16,T13,T43
StableSt	-	-	-	-	-	-	0	Covered	T16,T13,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	2808	0	0
CntIncr_A	6272770	99967	0	0
CntNoWrap_A	6272770	5609150	0	0
DetectStDropOut_A	6272770	332	0	0
DetectedOut_A	6272770	68671	0	0
DetectedPulseOut_A	6272770	868	0	0
DisabledIdleSt_A	6272770	5185574	0	0
DisabledNoDetection_A	6272770	5187757	0	0
EnterDebounceSt_A	6272770	1428	0	0
EnterDetectSt_A	6272770	1381	0	0
EnterStableSt_A	6272770	868	0	0
PulseIsPulse_A	6272770	868	0	0
StayInStableSt	6272770	67717	0	0
gen_high_event_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	768	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	2808	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	22	0	0
T13	0	52	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	12	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	46	0	0
T35	0	12	0	0
T43	0	46	0	0
T49	0	8	0	0
T50	0	24	0	0
T60	0	42	0	0
T62	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	99967	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	562	0	0
T13	0	1196	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	2589	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	1504	0	0
T35	0	420	0	0
T43	0	1840	0	0
T49	0	277	0	0
T50	0	756	0	0
T60	0	1050	0	0
T62	0	1127	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5609150	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18285	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	332	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	8	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	12	0	0
T69	0	9	0	0
T81	0	29	0	0
T208	0	10	0	0
T210	0	29	0	0
T211	0	13	0	0
T226	0	14	0	0
T227	0	7	0	0
T228	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	68671	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	2294	0	0
T16	8065	86	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	312	0	0
T43	0	2045	0	0
T44	623	0	0	0
T50	0	200	0	0
T60	0	1819	0	0
T62	0	322	0	0
T79	0	28	0	0
T83	0	17	0	0
T213	0	2006	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	26	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	6	0	0
T43	0	23	0	0
T44	623	0	0	0
T50	0	12	0	0
T60	0	21	0	0
T62	0	23	0	0
T79	0	1	0	0
T83	0	4	0	0
T213	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5185574	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	15538	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5187757	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	15544	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1428	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	11	0	0
T13	0	26	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	11	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	23	0	0
T35	0	6	0	0
T43	0	23	0	0
T49	0	4	0	0
T50	0	12	0	0
T60	0	21	0	0
T62	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1381	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	11	0	0
T13	0	26	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	1	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	23	0	0
T35	0	6	0	0
T43	0	23	0	0
T49	0	4	0	0
T50	0	12	0	0
T60	0	21	0	0
T62	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	26	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	6	0	0
T43	0	23	0	0
T44	623	0	0	0
T50	0	12	0	0
T60	0	21	0	0
T62	0	23	0	0
T79	0	1	0	0
T83	0	4	0	0
T213	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	26	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	6	0	0
T43	0	23	0	0
T44	623	0	0	0
T50	0	12	0	0
T60	0	21	0	0
T62	0	23	0	0
T79	0	1	0	0
T83	0	4	0	0
T213	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	67717	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	2267	0	0
T16	8065	85	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	306	0	0
T43	0	2019	0	0
T44	623	0	0	0
T50	0	188	0	0
T60	0	1793	0	0
T62	0	299	0	0
T79	0	27	0	0
T83	0	13	0	0
T213	0	1980	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	768	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	25	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	6	0	0
T43	0	20	0	0
T44	623	0	0	0
T50	0	12	0	0
T60	0	16	0	0
T62	0	23	0	0
T79	0	1	0	0
T83	0	4	0	0
T213	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T7,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T5,T6,T14
1	1	Covered	T2,T7,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T48,T67,T216
1	0	Covered	T52,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T2,T7,T13
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T13
1	-	Covered	T2,T7,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T13
DetectSt	168	Covered	T2,T7,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T7,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T13
DebounceSt->IdleSt	163	Covered	T2,T13,T60
DetectSt->IdleSt	186	Covered	T48,T67,T216
DetectSt->StableSt	191	Covered	T2,T7,T13
IdleSt->DebounceSt	148	Covered	T2,T7,T13
StableSt->IdleSt	206	Covered	T2,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T13
0	1	Covered	T2,T7,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T13,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T13
DetectSt	-	-	-	-	1	-	-	Covered	T48,T67,T216
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T13
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T13
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T13
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	779	0	0
CntIncr_A	6272770	44080	0	0
CntNoWrap_A	6272770	5611179	0	0
DetectStDropOut_A	6272770	43	0	0
DetectedOut_A	6272770	15871	0	0
DetectedPulseOut_A	6272770	320	0	0
DisabledIdleSt_A	6272770	5267715	0	0
DisabledNoDetection_A	6272770	5269418	0	0
EnterDebounceSt_A	6272770	412	0	0
EnterDetectSt_A	6272770	367	0	0
EnterStableSt_A	6272770	320	0	0
PulseIsPulse_A	6272770	320	0	0
StayInStableSt	6272770	15510	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	779	0	0
T2	23021	12	0	0
T3	13820	0	0	0
T7	46472	4	0	0
T13	0	3	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	6	0	0
T36	0	6	0	0
T43	0	6	0	0
T44	623	0	0	0
T48	0	2	0	0
T60	0	9	0	0
T67	0	2	0	0
T223	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	44080	0	0
T2	23021	749	0	0
T3	13820	0	0	0
T7	46472	182	0	0
T13	0	112	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	339	0	0
T36	0	237	0	0
T43	0	225	0	0
T44	623	0	0	0
T48	0	177	0	0
T60	0	131	0	0
T67	0	152	0	0
T223	0	238	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611179	0	0
T1	19483	19082	0	0
T2	23021	22592	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	43	0	0
T26	1230	0	0	0
T36	34138	0	0	0
T42	2624	0	0	0
T43	16797	0	0	0
T48	17648	1	0	0
T67	0	1	0	0
T90	0	2	0	0
T92	0	3	0	0
T95	0	2	0	0
T98	522	0	0	0
T99	442	0	0	0
T100	424	0	0	0
T101	531	0	0	0
T102	402	0	0	0
T130	0	1	0	0
T142	0	1	0	0
T216	0	3	0	0
T229	0	11	0	0
T230	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	15871	0	0
T2	23021	248	0	0
T3	13820	0	0	0
T7	46472	10	0	0
T13	0	45	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	124	0	0
T36	0	129	0	0
T43	0	144	0	0
T44	623	0	0	0
T60	0	234	0	0
T213	0	50	0	0
T223	0	8	0	0
T224	0	287	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	320	0	0
T2	23021	5	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T60	0	4	0	0
T213	0	1	0	0
T223	0	2	0	0
T224	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5267715	0	0
T1	19483	19082	0	0
T2	23021	18131	0	0
T3	13820	6107	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5269418	0	0
T1	19483	19083	0	0
T2	23021	18131	0	0
T3	13820	6127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	412	0	0
T2	23021	7	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	2	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T48	0	1	0	0
T60	0	5	0	0
T67	0	1	0	0
T223	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	367	0	0
T2	23021	5	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T48	0	1	0	0
T60	0	4	0	0
T67	0	1	0	0
T223	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	320	0	0
T2	23021	5	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T60	0	4	0	0
T213	0	1	0	0
T223	0	2	0	0
T224	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	320	0	0
T2	23021	5	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T60	0	4	0	0
T213	0	1	0	0
T223	0	2	0	0
T224	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	15510	0	0
T2	23021	243	0	0
T3	13820	0	0	0
T7	46472	8	0	0
T13	0	44	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	121	0	0
T36	0	126	0	0
T43	0	141	0	0
T44	623	0	0	0
T60	0	230	0	0
T213	0	48	0	0
T223	0	6	0	0
T224	0	281	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	276	0	0
T2	23021	5	0	0
T3	13820	0	0	0
T7	46472	2	0	0
T13	0	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T44	623	0	0	0
T60	0	4	0	0
T82	0	8	0	0
T223	0	2	0	0
T224	0	6	0	0