Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T16,T13
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T16,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T16,T13
1	0	Covered	T6,T13,T43
1	1	Covered	T6,T16,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T16,T13
0	1	Covered	T6,T33,T81
1	0	Covered	T6,T33,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T13,T43
0	1	Covered	T16,T13,T43
1	0	Covered	T60,T231

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T13,T43
1	-	Covered	T16,T13,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T16,T13
DetectSt	168	Covered	T6,T16,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T16,T13,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T16,T13
DebounceSt->IdleSt	163	Covered	T16,T79,T208
DetectSt->IdleSt	186	Covered	T6,T33,T50
DetectSt->StableSt	191	Covered	T16,T13,T43
IdleSt->DebounceSt	148	Covered	T6,T16,T13
StableSt->IdleSt	206	Covered	T16,T13,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T16,T13
0	1	Covered	T6,T16,T13
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T16,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T16,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T16,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T16,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T79,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T16,T13
DetectSt	-	-	-	-	1	-	-	Covered	T6,T33,T50
DetectSt	-	-	-	-	0	1	-	Covered	T16,T13,T43
DetectSt	-	-	-	-	0	0	-	Covered	T6,T16,T13
StableSt	-	-	-	-	-	-	1	Covered	T16,T13,T43
StableSt	-	-	-	-	-	-	0	Covered	T16,T13,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	2824	0	0
CntIncr_A	6272770	100860	0	0
CntNoWrap_A	6272770	5609134	0	0
DetectStDropOut_A	6272770	295	0	0
DetectedOut_A	6272770	69226	0	0
DetectedPulseOut_A	6272770	868	0	0
DisabledIdleSt_A	6272770	5185868	0	0
DisabledNoDetection_A	6272770	5188047	0	0
EnterDebounceSt_A	6272770	1445	0	0
EnterDetectSt_A	6272770	1384	0	0
EnterStableSt_A	6272770	868	0	0
PulseIsPulse_A	6272770	868	0	0
StayInStableSt	6272770	68267	0	0
gen_high_event_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	767	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	2824	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	52	0	0
T13	0	22	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	9	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	60	0	0
T35	0	50	0	0
T43	0	10	0	0
T49	0	46	0	0
T50	0	54	0	0
T60	0	16	0	0
T62	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	100860	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	1333	0	0
T13	0	649	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	1914	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	1961	0	0
T35	0	1900	0	0
T43	0	340	0	0
T49	0	1403	0	0
T50	0	2100	0	0
T60	0	352	0	0
T62	0	943	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5609134	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18255	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	295	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	16	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	13	0	0
T81	0	15	0	0
T87	0	12	0	0
T88	0	15	0	0
T89	0	5	0	0
T210	0	13	0	0
T211	0	9	0	0
T232	0	14	0	0
T233	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	69226	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	485	0	0
T16	8065	58	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	1288	0	0
T43	0	576	0	0
T44	623	0	0	0
T49	0	2187	0	0
T60	0	366	0	0
T62	0	506	0	0
T79	0	197	0	0
T83	0	2220	0	0
T213	0	908	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	11	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	25	0	0
T43	0	5	0	0
T44	623	0	0	0
T49	0	23	0	0
T60	0	8	0	0
T62	0	23	0	0
T79	0	7	0	0
T83	0	14	0	0
T213	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5185868	0	0
T1	19483	19082	0	0
T2	23021	22604	0	0
T3	13820	7106	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	15538	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5188047	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	15544	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1445	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	26	0	0
T13	0	11	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	8	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	30	0	0
T35	0	25	0	0
T43	0	5	0	0
T49	0	23	0	0
T50	0	27	0	0
T60	0	8	0	0
T62	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	1384	0	0
T1	19483	0	0	0
T2	23021	0	0	0
T3	13820	0	0	0
T6	18720	26	0	0
T13	0	11	0	0
T14	2353	0	0	0
T15	407	0	0	0
T16	8065	1	0	0
T17	502	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T33	0	30	0	0
T35	0	25	0	0
T43	0	5	0	0
T49	0	23	0	0
T50	0	27	0	0
T60	0	8	0	0
T62	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	11	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	25	0	0
T43	0	5	0	0
T44	623	0	0	0
T49	0	23	0	0
T60	0	8	0	0
T62	0	23	0	0
T79	0	7	0	0
T83	0	14	0	0
T213	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	868	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	11	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	25	0	0
T43	0	5	0	0
T44	623	0	0	0
T49	0	23	0	0
T60	0	8	0	0
T62	0	23	0	0
T79	0	7	0	0
T83	0	14	0	0
T213	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	68267	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	474	0	0
T16	8065	57	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	1261	0	0
T43	0	571	0	0
T44	623	0	0	0
T49	0	2155	0	0
T60	0	358	0	0
T62	0	483	0	0
T79	0	190	0	0
T83	0	2200	0	0
T213	0	887	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	767	0	0
T7	46472	0	0	0
T8	616	0	0	0
T9	812	0	0	0
T10	1258	0	0	0
T13	0	11	0	0
T16	8065	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T35	0	23	0	0
T43	0	5	0	0
T44	623	0	0	0
T49	0	14	0	0
T62	0	23	0	0
T79	0	7	0	0
T83	0	8	0	0
T84	0	18	0	0
T213	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T5,T6,T14
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T65,T194,T90
1	0	Covered	T52,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T52,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T36,T34
DetectSt->IdleSt	186	Covered	T65,T194,T90
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T36,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T65,T194,T90
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6272770	854	0	0
CntIncr_A	6272770	45802	0	0
CntNoWrap_A	6272770	5611104	0	0
DetectStDropOut_A	6272770	50	0	0
DetectedOut_A	6272770	15818	0	0
DetectedPulseOut_A	6272770	346	0	0
DisabledIdleSt_A	6272770	5271975	0	0
DisabledNoDetection_A	6272770	5273687	0	0
EnterDebounceSt_A	6272770	455	0	0
EnterDetectSt_A	6272770	399	0	0
EnterStableSt_A	6272770	346	0	0
PulseIsPulse_A	6272770	346	0	0
StayInStableSt	6272770	15443	0	0
gen_high_level_sva.HighLevelEvent_A	6272770	5614314	0	0
gen_not_sticky_sva.StableStDropOut_A	6272770	314	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	854	0	0
T2	23021	12	0	0
T3	13820	2	0	0
T7	46472	2	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	21	0	0
T35	0	1	0	0
T36	0	23	0	0
T43	0	4	0	0
T44	623	0	0	0
T49	0	18	0	0
T67	0	17	0	0
T223	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	45802	0	0
T2	23021	934	0	0
T3	13820	139	0	0
T7	46472	72	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	1302	0	0
T35	0	37	0	0
T36	0	912	0	0
T43	0	126	0	0
T44	623	0	0	0
T49	0	450	0	0
T67	0	888	0	0
T223	0	474	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5611104	0	0
T1	19483	19082	0	0
T2	23021	22592	0	0
T3	13820	7104	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	50	0	0
T52	0	1	0	0
T65	22972	1	0	0
T85	26583	0	0	0
T90	0	1	0	0
T91	0	7	0	0
T151	17739	0	0	0
T194	0	1	0	0
T218	0	5	0	0
T222	0	7	0	0
T234	0	12	0	0
T235	0	3	0	0
T236	0	9	0	0
T237	724	0	0	0
T238	412	0	0	0
T239	409	0	0	0
T240	810	0	0	0
T241	421	0	0	0
T242	647	0	0	0
T243	1018	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	15818	0	0
T2	23021	63	0	0
T3	13820	15	0	0
T7	46472	24	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	291	0	0
T36	0	479	0	0
T43	0	120	0	0
T44	623	0	0	0
T49	0	424	0	0
T67	0	394	0	0
T213	0	81	0	0
T223	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	346	0	0
T2	23021	5	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	9	0	0
T36	0	11	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	9	0	0
T67	0	8	0	0
T213	0	1	0	0
T223	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5271975	0	0
T1	19483	19082	0	0
T2	23021	18131	0	0
T3	13820	6107	0	0
T4	580	179	0	0
T5	37799	35394	0	0
T6	18720	18307	0	0
T14	2353	349	0	0
T15	407	6	0	0
T20	503	102	0	0
T21	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5273687	0	0
T1	19483	19083	0	0
T2	23021	18131	0	0
T3	13820	6127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	455	0	0
T2	23021	7	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	12	0	0
T35	0	1	0	0
T36	0	12	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	9	0	0
T67	0	9	0	0
T223	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	399	0	0
T2	23021	5	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	9	0	0
T36	0	11	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	9	0	0
T67	0	8	0	0
T213	0	1	0	0
T223	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	346	0	0
T2	23021	5	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	9	0	0
T36	0	11	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	9	0	0
T67	0	8	0	0
T213	0	1	0	0
T223	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	346	0	0
T2	23021	5	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	9	0	0
T36	0	11	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	9	0	0
T67	0	8	0	0
T213	0	1	0	0
T223	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	15443	0	0
T2	23021	58	0	0
T3	13820	14	0	0
T7	46472	23	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	282	0	0
T36	0	468	0	0
T43	0	118	0	0
T44	623	0	0	0
T49	0	410	0	0
T67	0	386	0	0
T213	0	79	0	0
T223	0	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	5614314	0	0
T1	19483	19083	0	0
T2	23021	22613	0	0
T3	13820	7127	0	0
T4	580	180	0	0
T5	37799	35399	0	0
T6	18720	18314	0	0
T14	2353	353	0	0
T15	407	7	0	0
T20	503	103	0	0
T21	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6272770	314	0	0
T2	23021	5	0	0
T3	13820	1	0	0
T7	46472	1	0	0
T15	407	0	0	0
T16	8065	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	426	0	0	0
T28	503	0	0	0
T34	0	9	0	0
T36	0	11	0	0
T43	0	2	0	0
T44	623	0	0	0
T49	0	4	0	0
T67	0	8	0	0
T82	0	2	0	0
T223	0	4	0	0