Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1232042785	9966	0	0
auto_block_debounce_ctl_rd_A	1232042785	1873	0	0
auto_block_out_ctl_rd_A	1232042785	3000	0	0
com_det_ctl_0_rd_A	1232042785	3626	0	0
com_det_ctl_1_rd_A	1232042785	3886	0	0
com_det_ctl_2_rd_A	1232042785	3814	0	0
com_det_ctl_3_rd_A	1232042785	3773	0	0
com_out_ctl_0_rd_A	1232042785	4569	0	0
com_out_ctl_1_rd_A	1232042785	5097	0	0
com_out_ctl_2_rd_A	1232042785	4774	0	0
com_out_ctl_3_rd_A	1232042785	4743	0	0
com_pre_det_ctl_0_rd_A	1232042785	1216	0	0
com_pre_det_ctl_1_rd_A	1232042785	1283	0	0
com_pre_det_ctl_2_rd_A	1232042785	1234	0	0
com_pre_det_ctl_3_rd_A	1232042785	1183	0	0
com_pre_sel_ctl_0_rd_A	1232042785	5225	0	0
com_pre_sel_ctl_1_rd_A	1232042785	5101	0	0
com_pre_sel_ctl_2_rd_A	1232042785	5269	0	0
com_pre_sel_ctl_3_rd_A	1232042785	5277	0	0
com_sel_ctl_0_rd_A	1232042785	5247	0	0
com_sel_ctl_1_rd_A	1232042785	5032	0	0
com_sel_ctl_2_rd_A	1232042785	5227	0	0
com_sel_ctl_3_rd_A	1232042785	5083	0	0
ec_rst_ctl_rd_A	1232042785	2350	0	0
intr_enable_rd_A	1232042785	1732	0	0
key_intr_ctl_rd_A	1232042785	5816	0	0
key_intr_debounce_ctl_rd_A	1232042785	1174	0	0
key_invert_ctl_rd_A	1232042785	7085	0	0
pin_allowed_ctl_rd_A	1232042785	8305	0	0
pin_out_ctl_rd_A	1232042785	5130	0	0
pin_out_value_rd_A	1232042785	5177	0	0
regwen_rd_A	1232042785	1267	0	0
ulp_ac_debounce_ctl_rd_A	1232042785	1366	0	0
ulp_ctl_rd_A	1232042785	1256	0	0
ulp_lid_debounce_ctl_rd_A	1232042785	1504	0	0
ulp_pwrb_debounce_ctl_rd_A	1232042785	1331	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	9966	0	0
T3	898956	9	0	0
T7	375143	4	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	8	0	0
T44	311582	0	0	0
T45	0	4	0	0
T48	0	22	0	0
T53	0	9	0	0
T54	0	7	0	0
T80	0	6	0	0
T147	0	10	0	0
T174	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1873	0	0
T3	898956	22	0	0
T7	375143	5	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T27	0	7	0	0
T28	22649	0	0	0
T37	0	19	0	0
T42	0	9	0	0
T44	311582	0	0	0
T45	0	29	0	0
T103	0	11	0	0
T110	0	16	0	0
T174	0	8	0	0
T269	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	3000	0	0
T3	898956	31	0	0
T7	375143	12	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T27	0	5	0	0
T28	22649	0	0	0
T37	0	27	0	0
T42	0	12	0	0
T44	311582	0	0	0
T45	0	12	0	0
T103	0	12	0	0
T110	0	14	0	0
T174	0	14	0	0
T270	0	12	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	3626	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	57	0	0
T6	926654	47	0	0
T7	0	57	0	0
T13	0	58	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	61	0	0
T37	0	19	0	0
T45	0	4	0	0
T50	0	51	0	0
T213	0	66	0	0
T224	0	67	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	3886	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	50	0	0
T6	926654	67	0	0
T7	0	89	0	0
T13	0	26	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	66	0	0
T37	0	34	0	0
T50	0	55	0	0
T174	0	31	0	0
T213	0	57	0	0
T224	0	65	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	3814	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	34	0	0
T6	926654	65	0	0
T7	0	85	0	0
T13	0	33	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	64	0	0
T37	0	33	0	0
T45	0	3	0	0
T50	0	44	0	0
T213	0	74	0	0
T224	0	72	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	3773	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	43	0	0
T6	926654	53	0	0
T7	0	77	0	0
T13	0	29	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	83	0	0
T37	0	40	0	0
T45	0	6	0	0
T50	0	37	0	0
T213	0	57	0	0
T224	0	72	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	4569	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	45	0	0
T6	926654	64	0	0
T7	0	82	0	0
T13	0	38	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	81	0	0
T37	0	34	0	0
T50	0	63	0	0
T174	0	11	0	0
T213	0	69	0	0
T224	0	74	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5097	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	34	0	0
T6	926654	52	0	0
T7	0	78	0	0
T13	0	47	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	54	0	0
T37	0	20	0	0
T45	0	7	0	0
T50	0	38	0	0
T213	0	53	0	0
T224	0	80	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	4774	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	37	0	0
T6	926654	60	0	0
T7	0	87	0	0
T13	0	42	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	81	0	0
T37	0	30	0	0
T50	0	27	0	0
T174	0	19	0	0
T213	0	62	0	0
T224	0	53	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	4743	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	35	0	0
T6	926654	56	0	0
T7	0	67	0	0
T13	0	40	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	72	0	0
T37	0	33	0	0
T45	0	10	0	0
T50	0	36	0	0
T213	0	64	0	0
T224	0	72	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1216	0	0
T3	898956	26	0	0
T7	375143	10	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	40	0	0
T44	311582	0	0	0
T45	0	6	0	0
T74	0	18	0	0
T124	0	36	0	0
T174	0	21	0	0
T186	0	22	0	0
T206	0	8	0	0
T271	0	18	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1283	0	0
T3	898956	18	0	0
T7	375143	2	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	33	0	0
T44	311582	0	0	0
T74	0	18	0	0
T124	0	30	0	0
T174	0	9	0	0
T186	0	36	0	0
T206	0	4	0	0
T271	0	15	0	0
T272	0	20	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1234	0	0
T3	898956	25	0	0
T7	375143	9	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	27	0	0
T44	311582	0	0	0
T45	0	4	0	0
T74	0	19	0	0
T124	0	18	0	0
T144	0	9	0	0
T174	0	6	0	0
T186	0	30	0	0
T271	0	15	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1183	0	0
T3	898956	28	0	0
T7	375143	8	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	21	0	0
T44	311582	0	0	0
T45	0	4	0	0
T74	0	15	0	0
T124	0	28	0	0
T174	0	11	0	0
T186	0	35	0	0
T206	0	4	0	0
T271	0	9	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5225	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	57	0	0
T6	926654	58	0	0
T7	0	76	0	0
T13	0	33	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	68	0	0
T37	0	20	0	0
T50	0	40	0	0
T174	0	18	0	0
T213	0	80	0	0
T224	0	74	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5101	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	27	0	0
T6	926654	72	0	0
T7	0	88	0	0
T13	0	33	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	71	0	0
T37	0	27	0	0
T45	0	4	0	0
T50	0	49	0	0
T213	0	51	0	0
T224	0	95	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5269	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	34	0	0
T6	926654	41	0	0
T7	0	75	0	0
T13	0	57	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	73	0	0
T37	0	31	0	0
T50	0	72	0	0
T174	0	15	0	0
T213	0	82	0	0
T224	0	77	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5277	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	55	0	0
T6	926654	77	0	0
T7	0	98	0	0
T13	0	28	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	74	0	0
T37	0	33	0	0
T45	0	3	0	0
T50	0	43	0	0
T213	0	60	0	0
T224	0	66	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5247	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	48	0	0
T6	926654	68	0	0
T7	0	77	0	0
T13	0	43	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	69	0	0
T37	0	22	0	0
T50	0	15	0	0
T174	0	41	0	0
T213	0	77	0	0
T224	0	73	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5032	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	43	0	0
T6	926654	71	0	0
T7	0	69	0	0
T13	0	48	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	65	0	0
T37	0	25	0	0
T45	0	4	0	0
T50	0	39	0	0
T213	0	70	0	0
T224	0	65	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5227	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	48	0	0
T6	926654	66	0	0
T7	0	64	0	0
T13	0	42	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	62	0	0
T37	0	37	0	0
T45	0	4	0	0
T50	0	44	0	0
T213	0	48	0	0
T224	0	47	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5083	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	38	0	0
T6	926654	63	0	0
T7	0	58	0	0
T13	0	17	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	99	0	0
T37	0	48	0	0
T50	0	26	0	0
T174	0	23	0	0
T213	0	78	0	0
T224	0	80	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	2350	0	0
T1	243324	0	0	0
T2	575531	0	0	0
T3	898956	33	0	0
T4	139179	5	0	0
T5	926091	0	0	0
T6	926654	26	0	0
T7	0	47	0	0
T13	0	5	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T20	125883	0	0	0
T21	258780	0	0	0
T36	0	51	0	0
T37	0	37	0	0
T45	0	4	0	0
T50	0	20	0	0
T79	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1732	0	0
T3	898956	41	0	0
T7	375143	8	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	36	0	0
T44	311582	0	0	0
T74	0	12	0	0
T109	0	17	0	0
T174	0	20	0	0
T186	0	34	0	0
T271	0	10	0	0
T273	0	6	0	0
T274	0	10	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5816	0	0
T3	898956	30	0	0
T7	375143	12	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T12	0	5	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	23	0	0
T44	311582	0	0	0
T45	0	6	0	0
T74	0	20	0	0
T134	0	1	0	0
T136	0	6	0	0
T150	0	5	0	0
T174	0	13	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1174	0	0
T3	898956	18	0	0
T7	375143	2	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	37	0	0
T44	311582	0	0	0
T74	0	10	0	0
T124	0	39	0	0
T144	0	3	0	0
T174	0	5	0	0
T186	0	39	0	0
T271	0	12	0	0
T272	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	7085	0	0
T3	898956	23	0	0
T7	375143	92	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	38	0	0
T37	0	35	0	0
T44	311582	0	0	0
T45	0	46	0	0
T57	0	65	0	0
T174	0	22	0	0
T275	0	41	0	0
T276	0	85	0	0
T277	0	74	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	8305	0	0
T3	898956	91	0	0
T7	375143	83	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	23	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T27	0	41	0	0
T28	22649	0	0	0
T37	0	34	0	0
T42	0	57	0	0
T44	311582	0	0	0
T45	0	61	0	0
T174	0	86	0	0
T278	0	79	0	0
T279	0	54	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5130	0	0
T3	898956	99	0	0
T7	375143	72	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	39	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T27	0	56	0	0
T28	22649	0	0	0
T37	0	29	0	0
T42	0	41	0	0
T44	311582	0	0	0
T45	0	50	0	0
T174	0	141	0	0
T278	0	66	0	0
T279	0	29	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	5177	0	0
T3	898956	93	0	0
T7	375143	61	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	31	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T27	0	72	0	0
T28	22649	0	0	0
T37	0	41	0	0
T42	0	57	0	0
T44	311582	0	0	0
T45	0	60	0	0
T174	0	104	0	0
T278	0	68	0	0
T279	0	36	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1267	0	0
T3	898956	23	0	0
T7	375143	5	0	0
T8	147971	0	0	0
T9	57243	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T28	22649	0	0	0
T37	0	33	0	0
T44	311582	0	0	0
T45	0	1	0	0
T74	0	21	0	0
T124	0	31	0	0
T174	0	21	0	0
T186	0	35	0	0
T206	0	3	0	0
T271	0	5	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1366	0	0
T1	243324	13	0	0
T2	575531	0	0	0
T3	898956	28	0	0
T7	375143	16	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T26	0	7	0	0
T27	0	7	0	0
T37	0	45	0	0
T45	0	10	0	0
T74	0	17	0	0
T174	0	22	0	0
T271	0	13	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1256	0	0
T1	243324	6	0	0
T2	575531	0	0	0
T3	898956	10	0	0
T7	375143	10	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T26	0	5	0	0
T37	0	34	0	0
T74	0	31	0	0
T78	0	6	0	0
T174	0	10	0	0
T186	0	44	0	0
T271	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1504	0	0
T1	243324	8	0	0
T2	575531	0	0	0
T3	898956	23	0	0
T7	375143	6	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T26	0	23	0	0
T27	0	5	0	0
T37	0	33	0	0
T45	0	1	0	0
T74	0	26	0	0
T174	0	13	0	0
T271	0	18	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232042785	1331	0	0
T1	243324	1	0	0
T2	575531	0	0	0
T3	898956	15	0	0
T7	375143	11	0	0
T14	200072	0	0	0
T15	48943	0	0	0
T16	387136	0	0	0
T17	216180	0	0	0
T18	246056	0	0	0
T19	53346	0	0	0
T26	0	5	0	0
T27	0	9	0	0
T37	0	19	0	0
T45	0	6	0	0
T74	0	20	0	0
T174	0	20	0	0
T271	0	16	0	0