Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2114

1

T1

2

T3

18

T5

48

auto[1]

732

1

T1

8

T3

4

T5

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2166

1

T1

2

T3

15

T5

48

auto[1]

680

1

T1

8

T3

7

T5

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2030

1

T1

8

T3

11

T5

60

auto[1]

816

1

T1

2

T3

11

T6

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2109

1

T1

8

T3

22

T5

57

auto[1]

737

1

T1

2

T5

3

T29

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2525

1

T1

10

T3

22

T5

60

auto[1]

321

1

T31

28

T32

20

T30

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2602

1

T1

10

T3

22

T5

57

auto[1]

244

1

T5

3

T31

4

T32

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2512

1

T1

10

T3

22

T5

33

auto[1]

334

1

T5

27

T25

1

T31

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2624

1

T1

10

T3

22

T5

36

auto[1]

222

1

T5

24

T25

1

T8

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2430

1

T1

10

T3

22

T5

60

auto[1]

416

1

T25

1

T31

28

T32

20

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2186

1

T1

5

T3

18

T5

48

auto[1]

660

1

T1

5

T3

4

T5

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

922

1

T1

10

T3

4

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T63

3

T99

4

T231

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

150

1

T63

3

T65

20

T211

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

74

1

T31

28

T32

8

T65

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T8

2

T319

5

T320

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T321

7

T322

2

-

-

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T211

3

T234

2

T323

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T30

2

T211

3

T324

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

93

1

T278

12

T320

3

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T245

5

T325

22

T326

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T212

3

T311

1

T327

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T63

1

T328

1

T329

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T5

24

T32

12

T33

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T32

6

T211

3

T321

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

82

1

T99

5

T278

5

T319

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T330

2

T279

2

T331

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T33

8

T212

2

T262

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T332

3

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

11

1

T32

3

T319

4

T315

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T251

1

T321

2

T333

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T323

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

17

1

T5

3

T334

2

T335

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T98

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T336

3

T322

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T31

4

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

159

1

T5

12

T22

1

T337

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

142

1

T31

4

T111

8

T97

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

64

1

T3

4

T29

5

T151

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

88

1

T5

3

T33

4

T246

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

76

1

T29

8

T111

8

T33

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

78

1

T34

3

T98

1

T338

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T38

2

T123

4

T151

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

156

1

T6

1

T29

10

T22

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

111

1

T32

3

T246

6

T211

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T337

10

T303

2

T319

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T99

5

T239

1

T313

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

94

1

T47

6

T307

4

T247

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T212

2

T239

3

T75

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T1

2

T89

2

T279

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T339

2

T340

2

T341

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

129

1

T32

18

T33

6

T65

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T1

5

T22

1

T306

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T5

12

T47

6

T34

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T1

3

T240

1

T101

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T63

1

T248

5

T243

14

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T47

2

T40

1

T151

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T240

4

T245

5

T304

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T278

6

T342

2

T304

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T31

28

T22

1

T30

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T8

2

T22

1

T41

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T89

1

T151

1

T231

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T338

2

T319

5

T241

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T32

8

T111

3

T123

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T111

1

T123

4

T97

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T249

1

T306

1

T343

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T241

1

T344

2

T345

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded