Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T2

10

T17

8

T23

12

auto[1]

1059

1

T2

10

T17

12

T23

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T2

4

T17

3

T23

6

from_0to1

517

1

T2

5

T17

3

T23

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T2

10

T17

13

T23

6

auto[1]

1069

1

T2

10

T17

7

T23

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T2

10

T17

11

T23

10

auto[1]

1081

1

T2

10

T17

9

T23

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T22

1

T44

2

T142

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T17

1

T22

3

T111

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T23

2

T10

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T23

3

T61

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T2

2

T17

1

T23

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T2

2

T10

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T61

2

T44

1

T145

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T23

2

T61

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T2

1

T17

1

T44

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T61

1

T10

1

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T17

1

T23

1

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T2

3

T61

2

T111

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T17

1

T61

2

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T23

1

T10

1

T44

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T22

1

T44

1

T111

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T2

1

T17

1

T23

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T2

12

T17

10

T23

9

auto[1]

1082

1

T2

8

T17

10

T23

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T2

5

T17

3

T23

5

from_0to1

501

1

T2

5

T17

4

T23

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T2

12

T17

8

T23

8

auto[1]

1096

1

T2

8

T17

12

T23

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T2

11

T17

11

T23

9

auto[1]

1080

1

T2

9

T17

9

T23

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T2

2

T23

2

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T10

2

T22

1

T35

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T2

1

T17

1

T142

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T2

1

T23

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T2

1

T61

1

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T22

1

T44

1

T111

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T17

4

T61

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T2

2

T23

1

T10

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T61

2

T111

1

T36

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T17

2

T111

1

T142

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T61

2

T36

1

T35

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T2

1

T23

2

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T2

1

T23

1

T61

2

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T2

1

T61

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T23

2

T10

1

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T23

1

T44

2

T35

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T2

14

T17

15

T23

10

auto[1]

1064

1

T2

6

T17

5

T23

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T2

4

T17

6

T23

8

from_0to1

502

1

T2

4

T17

5

T23

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T2

14

T17

9

T23

15

auto[1]

1079

1

T2

6

T17

11

T23

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T2

10

T17

10

T23

11

auto[1]

1022

1

T2

10

T17

10

T23

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T2

1

T23

2

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T2

1

T17

2

T111

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T17

1

T23

1

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T2

1

T17

1

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T17

1

T23

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T2

3

T23

1

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T2

1

T17

2

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T17

1

T61

2

T36

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T23

1

T61

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T17

1

T23

2

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T2

1

T61

2

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T17

1

T23

2

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T23

1

T44

1

T142

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T23

2

T111

1

T142

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T23

1

T10

1

T111

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T17

1

T23

1

T22

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T2

10

T17

9

T23

11

auto[1]

1105

1

T2

10

T17

11

T23

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T2

6

T17

6

T23

6

from_0to1

514

1

T2

6

T17

5

T23

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T2

13

T17

12

T23

7

auto[1]

1060

1

T2

7

T17

8

T23

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T2

8

T17

7

T23

10

auto[1]

1072

1

T2

12

T17

13

T23

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T17

1

T23

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T2

3

T17

3

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T22

2

T111

1

T364

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T2

1

T23

1

T61

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T2

3

T17

2

T111

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T44

1

T111

1

T36

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T23

1

T44

1

T111

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T61

1

T22

1

T36

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T2

2

T61

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T23

1

T10

1

T111

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T23

1

T61

1

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T17

2

T23

2

T35

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T61

2

T36

1

T364

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T17

1

T23

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T2

3

T17

1

T23

2

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T17

1

T23

1

T61

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T2

10

T17

11

T23

10

auto[1]

1060

1

T2

10

T17

9

T23

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T2

5

T17

5

T23

3

from_0to1

518

1

T2

5

T17

5

T23

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T2

11

T17

9

T23

9

auto[1]

1101

1

T2

9

T17

11

T23

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T2

8

T17

9

T23

12

auto[1]

1085

1

T2

12

T17

11

T23

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T2

1

T22

1

T111

2

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T61

1

T44

2

T36

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T17

1

T23

1

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T2

2

T61

1

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T2

1

T61

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T2

2

T17

1

T44

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T17

1

T23

2

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T61

1

T10

1

T111

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T2

1

T17

1

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T2

1

T17

2

T61

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T23

1

T61

2

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T17

1

T23

1

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T17

1

T10

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T17

1

T61

1

T111

2

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T2

1

T17

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T2

1

T23

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T2

13

T17

8

T23

12

auto[1]

1056

1

T2

7

T17

12

T23

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T2

5

T17

4

T23

5

from_0to1

542

1

T2

5

T17

4

T23

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T2

11

T17

14

T23

8

auto[1]

1065

1

T2

9

T17

6

T23

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T2

12

T17

11

T23

10

auto[1]

1054

1

T2

8

T17

9

T23

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T2

1

T23

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T2

1

T17

1

T23

3

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T2

1

T111

2

T145

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T17

1

T61

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T2

1

T23

1

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T2

1

T17

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T2

2

T17

1

T23

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T23

2

T61

1

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T2

2

T17

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T17

1

T61

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T23

1

T61

1

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T61

1

T22

1

T36

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T17

1

T61

1

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T17

1

T61

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T111

1

T36

1

T35

3

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T2

1

T23

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T2

10

T17

8

T23

7

auto[1]

1056

1

T2

10

T17

12

T23

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T2

5

T17

5

T23

6

from_0to1

514

1

T2

5

T17

5

T23

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T2

10

T17

13

T23

17

auto[1]

1089

1

T2

10

T17

7

T23

3

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T2

9

T17

13

T23

10

auto[1]

1062

1

T2

11

T17

7

T23

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T17

1

T23

1

T61

3

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T2

1

T22

1

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T2

1

T17

1

T10

2

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T17

1

T23

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T2

1

T17

1

T23

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T2

1

T23

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T17

1

T23

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T10

3

T44

1

T364

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T17

2

T23

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T2

1

T23

2

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T23

1

T61

1

T44

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T2

2

T10

1

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T17

1

T23

2

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T2

1

T17

1

T23

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T2

2

T111

2

T142

2

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T17

1

T22

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T2

12

T17

12

T23

9

auto[1]

1091

1

T2

8

T17

8

T23

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T2

3

T17

4

T23

5

from_0to1

514

1

T2

4

T17

3

T23

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T2

10

T17

12

T23

11

auto[1]

1080

1

T2

10

T17

8

T23

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T2

10

T17

14

T23

15

auto[1]

1089

1

T2

10

T17

6

T23

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T17

1

T61

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T23

1

T22

1

T44

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T2

1

T17

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T23

1

T111

1

T142

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T2

2

T23

1

T22

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T35

1

T145

1

T365

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T17

2

T23

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T22

1

T111

1

T35

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T17

1

T23

2

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T2

2

T17

1

T23

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T61

1

T22

1

T44

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T61

1

T10

3

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T17

1

T23

4

T44

3

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T61

1

T10

1

T36

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T10

1

T44

2

T111

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T2

2

T61

1

T22

2