Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148547	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112848

1

T4

106

T1

279

T2

311

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134047	1			T4	182		T1	404		T2	334
values[0x0]	63475	1			T4	18		T1	68		T2	212
values[0x1]	63873	1			T4	23		T1	73		T2	180

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141144

1

T4

131

T1

336

T2

374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	878	1			T5	4		T6	2		T61	1
valid_sources[0x01]	953	1			T1	1		T3	4		T16	2
valid_sources[0x02]	836	1			T1	2		T3	4		T6	2
valid_sources[0x03]	1205	1			T3	3		T5	19		T6	1
valid_sources[0x04]	870	1			T1	5		T3	2		T11	4
valid_sources[0x05]	896	1			T1	4		T3	3		T5	2
valid_sources[0x06]	938	1			T1	2		T6	4		T61	2
valid_sources[0x07]	794	1			T3	1		T7	3		T9	2
valid_sources[0x08]	1016	1			T1	2		T3	4		T5	11
valid_sources[0x09]	831	1			T1	2		T5	18		T6	1
valid_sources[0x0a]	876	1			T1	1		T15	1		T6	1
valid_sources[0x0b]	827	1			T1	4		T3	4		T5	12
valid_sources[0x0c]	845	1			T1	3		T3	4		T5	8
valid_sources[0x0d]	959	1			T1	2		T3	1		T25	1
valid_sources[0x0e]	764	1			T3	1		T6	1		T47	2
valid_sources[0x0f]	1030	1			T1	2		T6	1		T47	3
valid_sources[0x10]	1030	1			T3	2		T5	16		T6	1
valid_sources[0x11]	928	1			T1	1		T3	3		T16	2
valid_sources[0x12]	1034	1			T1	2		T3	4		T25	3
valid_sources[0x13]	833	1			T1	2		T3	3		T5	7
valid_sources[0x14]	809	1			T1	3		T3	1		T5	5
valid_sources[0x15]	714	1			T1	1		T3	2		T5	2
valid_sources[0x16]	881	1			T3	4		T5	2		T22	5
valid_sources[0x17]	1325	1			T1	2		T3	2		T5	20
valid_sources[0x18]	822	1			T1	3		T3	1		T6	2
valid_sources[0x19]	1955	1			T3	3		T5	2		T25	2
valid_sources[0x1a]	1778	1			T1	4		T3	2		T5	3
valid_sources[0x1b]	1591	1			T1	2		T5	21		T23	19
valid_sources[0x1c]	1123	1			T1	3		T3	1		T15	1
valid_sources[0x1d]	1719	1			T1	1		T3	4		T5	16
valid_sources[0x1e]	1515	1			T3	4		T23	20		T6	3
valid_sources[0x1f]	1255	1			T1	1		T3	3		T5	22
valid_sources[0x20]	763	1			T4	1		T1	4		T3	3
valid_sources[0x21]	723	1			T5	14		T6	2		T31	8
valid_sources[0x22]	1942	1			T25	3		T6	1		T31	3
valid_sources[0x23]	1017	1			T3	3		T5	5		T23	20
valid_sources[0x24]	859	1			T1	2		T3	1		T5	1
valid_sources[0x25]	1303	1			T1	5		T12	2		T3	3
valid_sources[0x26]	1017	1			T1	7		T3	5		T5	6
valid_sources[0x27]	1304	1			T1	4		T3	3		T25	5
valid_sources[0x28]	1606	1			T1	2		T12	1		T3	2
valid_sources[0x29]	897	1			T1	4		T3	1		T6	1
valid_sources[0x2a]	1823	1			T1	1		T12	2		T16	1
valid_sources[0x2b]	750	1			T1	5		T3	4		T25	8
valid_sources[0x2c]	853	1			T1	3		T5	2		T6	2
valid_sources[0x2d]	867	1			T1	3		T5	5		T25	6
valid_sources[0x2e]	1967	1			T4	8		T1	1		T6	2
valid_sources[0x2f]	895	1			T1	3		T3	2		T5	12
valid_sources[0x30]	767	1			T1	3		T25	1		T6	1
valid_sources[0x31]	1300	1			T1	2		T3	1		T5	13
valid_sources[0x32]	1816	1			T1	4		T5	1		T49	2
valid_sources[0x33]	1574	1			T3	6		T6	1		T61	3
valid_sources[0x34]	1289	1			T4	11		T1	3		T5	1
valid_sources[0x35]	950	1			T5	4		T6	3		T31	9
valid_sources[0x36]	936	1			T1	1		T5	4		T6	2
valid_sources[0x37]	798	1			T1	1		T3	2		T5	7
valid_sources[0x38]	823	1			T1	1		T3	3		T31	2
valid_sources[0x39]	900	1			T1	4		T3	4		T16	1
valid_sources[0x3a]	1422	1			T4	20		T1	4		T5	1
valid_sources[0x3b]	1017	1			T1	1		T5	11		T31	12
valid_sources[0x3c]	713	1			T1	2		T3	2		T45	1
valid_sources[0x3d]	751	1			T1	2		T3	1		T5	1
valid_sources[0x3e]	892	1			T4	20		T1	5		T5	3
valid_sources[0x3f]	912	1			T16	1		T25	1		T6	3
valid_sources[0x40]	722	1			T1	3		T3	2		T5	1
valid_sources[0x41]	757	1			T1	4		T3	5		T25	7
valid_sources[0x42]	771	1			T1	1		T3	3		T5	15
valid_sources[0x43]	778	1			T1	7		T3	1		T5	10
valid_sources[0x44]	692	1			T1	2		T5	9		T47	5
valid_sources[0x45]	840	1			T1	2		T5	7		T6	2
valid_sources[0x46]	825	1			T1	4		T5	2		T25	8
valid_sources[0x47]	774	1			T3	3		T16	1		T5	3
valid_sources[0x48]	1752	1			T1	5		T3	4		T5	3
valid_sources[0x49]	671	1			T3	3		T5	5		T6	2
valid_sources[0x4a]	770	1			T1	1		T25	9		T6	1
valid_sources[0x4b]	912	1			T3	2		T5	4		T25	10
valid_sources[0x4c]	940	1			T1	1		T6	1		T31	4
valid_sources[0x4d]	703	1			T1	2		T3	3		T5	4
valid_sources[0x4e]	833	1			T1	2		T25	4		T6	4
valid_sources[0x4f]	867	1			T1	4		T5	7		T6	2
valid_sources[0x50]	1094	1			T1	2		T5	9		T25	2
valid_sources[0x51]	1164	1			T1	2		T3	3		T5	3
valid_sources[0x52]	1527	1			T1	2		T2	337		T3	1
valid_sources[0x53]	933	1			T1	2		T3	2		T5	9
valid_sources[0x54]	762	1			T1	2		T6	2		T52	3
valid_sources[0x55]	1600	1			T1	1		T3	1		T25	5
valid_sources[0x56]	822	1			T5	3		T6	1		T31	4
valid_sources[0x57]	906	1			T1	3		T3	1		T5	2
valid_sources[0x58]	907	1			T1	1		T3	1		T5	6
valid_sources[0x59]	755	1			T4	37		T1	1		T5	1
valid_sources[0x5a]	1193	1			T1	2		T5	4		T61	2
valid_sources[0x5b]	788	1			T1	3		T3	1		T5	1
valid_sources[0x5c]	1098	1			T1	1		T3	3		T16	1
valid_sources[0x5d]	992	1			T1	1		T3	3		T5	4
valid_sources[0x5e]	1219	1			T1	1		T12	1		T5	3
valid_sources[0x5f]	770	1			T1	3		T3	1		T5	1
valid_sources[0x60]	1089	1			T1	2		T14	6		T5	1
valid_sources[0x61]	928	1			T1	2		T3	3		T25	8
valid_sources[0x62]	1140	1			T2	20		T3	3		T5	4
valid_sources[0x63]	790	1			T1	2		T3	1		T25	6
valid_sources[0x64]	772	1			T1	3		T3	3		T5	8
valid_sources[0x65]	1059	1			T5	1		T25	5		T6	5
valid_sources[0x66]	761	1			T1	1		T2	3		T3	5
valid_sources[0x67]	859	1			T4	27		T1	4		T3	2
valid_sources[0x68]	1742	1			T1	3		T3	1		T5	3
valid_sources[0x69]	1006	1			T1	6		T25	4		T6	2
valid_sources[0x6a]	976	1			T3	4		T25	8		T6	1
valid_sources[0x6b]	1002	1			T1	4		T3	1		T5	8
valid_sources[0x6c]	851	1			T1	3		T3	1		T5	2
valid_sources[0x6d]	1854	1			T1	2		T3	1		T16	2
valid_sources[0x6e]	863	1			T1	4		T3	1		T5	18
valid_sources[0x6f]	884	1			T1	3		T3	2		T5	17
valid_sources[0x70]	1312	1			T1	3		T5	30		T25	8
valid_sources[0x71]	955	1			T1	1		T3	3		T5	12
valid_sources[0x72]	1095	1			T1	1		T5	4		T6	3
valid_sources[0x73]	730	1			T1	1		T3	1		T5	10
valid_sources[0x74]	806	1			T1	1		T3	3		T25	4
valid_sources[0x75]	1025	1			T1	4		T3	3		T17	122
valid_sources[0x76]	690	1			T1	5		T5	6		T25	8
valid_sources[0x77]	1015	1			T1	3		T5	14		T23	20
valid_sources[0x78]	903	1			T1	3		T3	1		T25	12
valid_sources[0x79]	798	1			T3	1		T5	7		T25	2
valid_sources[0x7a]	1085	1			T1	2		T3	2		T5	6
valid_sources[0x7b]	1008	1			T1	5		T3	1		T6	1
valid_sources[0x7c]	1836	1			T1	1		T3	1		T16	1
valid_sources[0x7d]	814	1			T1	5		T3	1		T5	5
valid_sources[0x7e]	788	1			T1	6		T3	5		T5	6
valid_sources[0x7f]	949	1			T1	4		T3	1		T5	5
valid_sources[0x80]	913	1			T5	7		T25	6		T61	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60694

1

T4

77

T1

211

T2

178

values[0x0]

all_enables

biggest_size

30578

1

T4

15

T1

36

T2

82

values[0x1]

all_enables

biggest_size

21576

1

T4

14

T1

32

T2

51