Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T24,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T24,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T24,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T24,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T24,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T24,T6
0	1	Covered	T10,T103,T108
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T24,T6
0	1	Covered	T4,T24,T6
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T24,T6
1	-	Covered	T4,T24,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T24,T6
DetectSt	168	Covered	T4,T24,T6
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T4,T24,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T24,T6
DebounceSt->IdleSt	163	Covered	T4,T39,T95
DetectSt->IdleSt	186	Covered	T10,T103,T108
DetectSt->StableSt	191	Covered	T4,T24,T6
IdleSt->DebounceSt	148	Covered	T4,T24,T6
StableSt->IdleSt	206	Covered	T4,T24,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T24,T6
0	1	Covered	T4,T24,T6
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T24,T6
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T24,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T24,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T95,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T24,T6
DetectSt	-	-	-	-	1	-	-	Covered	T10,T103,T108
DetectSt	-	-	-	-	0	1	-	Covered	T4,T24,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T24,T6
StableSt	-	-	-	-	-	-	0	Covered	T4,T24,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	245	0	0
CntIncr_A	7934265	104949	0	0
CntNoWrap_A	7934265	7269319	0	0
DetectStDropOut_A	7934265	3	0	0
DetectedOut_A	7934265	750	0	0
DetectedPulseOut_A	7934265	108	0	0
DisabledIdleSt_A	7934265	7158832	0	0
DisabledNoDetection_A	7934265	7161230	0	0
EnterDebounceSt_A	7934265	136	0	0
EnterDetectSt_A	7934265	111	0	0
EnterStableSt_A	7934265	108	0	0
PulseIsPulse_A	7934265	108	0	0
StayInStableSt	7934265	642	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6867	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	107	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	245	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	3	0	0
T6	0	2	0	0
T10	0	4	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	4	0	0
T24	0	2	0	0
T35	0	2	0	0
T36	0	6	0	0
T45	0	4	0	0
T46	0	4	0	0
T48	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	104949	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	114	0	0
T6	0	53	0	0
T10	0	93	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	167	0	0
T24	0	10	0	0
T35	0	34	0	0
T36	0	152	0	0
T45	0	85	0	0
T46	0	54	0	0
T48	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269319	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	492	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T32	29183	0	0	0
T38	28370	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T103	0	1	0	0
T108	0	1	0	0
T109	772	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	750	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	5	0	0
T6	0	6	0	0
T10	0	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	12	0	0
T24	0	6	0	0
T35	0	3	0	0
T36	0	29	0	0
T45	0	12	0	0
T46	0	10	0	0
T48	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	108	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T6	0	1	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7158832	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	307	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7161230	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	312	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	136	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	2	0	0
T6	0	1	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	111	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T6	0	1	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	108	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T6	0	1	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	108	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T6	0	1	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	642	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	4	0	0
T6	0	5	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	10	0	0
T24	0	5	0	0
T35	0	2	0	0
T36	0	26	0	0
T45	0	10	0	0
T46	0	8	0	0
T48	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6867	0	0
T1	20664	13	0	0
T2	10916	51	0	0
T3	6381	12	0	0
T4	2743	7	0	0
T5	0	36	0	0
T12	336610	5	0	0
T13	423	1	0	0
T14	675	0	0	0
T15	423	3	0	0
T16	442	4	0	0
T17	502	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	107	0	0
T1	20664	0	0	0
T2	10916	0	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T6	0	1	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T44,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T44,T34
0	1	Covered	T66,T67,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T44,T34
0	1	Unreachable
1	0	Covered	T2,T44,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T2,T44,T34
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T44,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T44,T34
DebounceSt->IdleSt	163	Covered	T7,T11,T54
DetectSt->IdleSt	186	Covered	T66,T67,T92
DetectSt->StableSt	191	Covered	T2,T44,T34
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T2,T44,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T44,T34
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T44,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T11,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T66,T67,T92
DetectSt	-	-	-	-	0	1	-	Covered	T2,T44,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T44,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T44,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	177	0	0
CntIncr_A	7934265	56915	0	0
CntNoWrap_A	7934265	7269387	0	0
DetectStDropOut_A	7934265	12	0	0
DetectedOut_A	7934265	305217	0	0
DetectedPulseOut_A	7934265	38	0	0
DisabledIdleSt_A	7934265	5273937	0	0
DisabledNoDetection_A	7934265	5276379	0	0
EnterDebounceSt_A	7934265	127	0	0
EnterDetectSt_A	7934265	50	0	0
EnterStableSt_A	7934265	38	0	0
PulseIsPulse_A	7934265	38	0	0
StayInStableSt	7934265	305179	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6867	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_sticky_sva.StableStDropOut_A	7934265	651360	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	177	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	3	0	0
T11	0	5	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T39	0	2	0	0
T44	0	2	0	0
T49	805	0	0	0
T54	0	8	0	0
T66	0	6	0	0
T67	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	56915	0	0
T2	10916	92	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	228	0	0
T11	0	115	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	22	0	0
T35	0	78	0	0
T39	0	67	0	0
T44	0	75	0	0
T49	805	0	0	0
T54	0	272	0	0
T66	0	234	0	0
T67	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269387	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	12	0	0
T64	502	0	0	0
T66	13073	1	0	0
T67	1362	1	0	0
T92	0	1	0	0
T97	8843	0	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	2	0	0
T121	0	4	0	0
T122	18493	0	0	0
T123	25338	0	0	0
T124	502	0	0	0
T125	524	0	0	0
T126	499	0	0	0
T127	19207	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	305217	0	0
T2	10916	49	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	5	0	0
T35	0	316	0	0
T44	0	664	0	0
T49	805	0	0	0
T66	0	78	0	0
T93	0	565	0	0
T112	0	47	0	0
T113	0	121	0	0
T115	0	296542	0	0
T116	0	153	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	38	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T66	0	1	0	0
T93	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T115	0	3	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5273937	0	0
T1	20664	20249	0	0
T2	10916	4219	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5276379	0	0
T1	20664	20257	0	0
T2	10916	4238	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	127	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	3	0	0
T11	0	5	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T54	0	8	0	0
T66	0	4	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T115	0	3	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	38	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T66	0	1	0	0
T93	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T115	0	3	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	38	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T66	0	1	0	0
T93	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T115	0	3	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	305179	0	0
T2	10916	48	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	4	0	0
T35	0	315	0	0
T44	0	663	0	0
T49	805	0	0	0
T66	0	77	0	0
T93	0	563	0	0
T112	0	46	0	0
T113	0	120	0	0
T115	0	296539	0	0
T116	0	152	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6867	0	0
T1	20664	13	0	0
T2	10916	51	0	0
T3	6381	12	0	0
T4	2743	7	0	0
T5	0	36	0	0
T12	336610	5	0	0
T13	423	1	0	0
T14	675	0	0	0
T15	423	3	0	0
T16	442	4	0	0
T17	502	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	651360	0	0
T2	10916	38	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	82	0	0
T35	0	508	0	0
T44	0	237	0	0
T49	805	0	0	0
T66	0	139	0	0
T93	0	260677	0	0
T112	0	24	0	0
T113	0	174	0	0
T115	0	243	0	0
T116	0	65	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T2,T12
1	1	Covered	T4,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T2,T12
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Covered	T44,T67,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Unreachable
1	0	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T2,T7,T11
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T11
DebounceSt->IdleSt	163	Covered	T39,T66,T67
DetectSt->IdleSt	186	Covered	T44,T67,T88
DetectSt->StableSt	191	Covered	T2,T7,T11
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T2,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T66,T67,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T44,T67,T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	160	0	0
CntIncr_A	7934265	133156	0	0
CntNoWrap_A	7934265	7269404	0	0
DetectStDropOut_A	7934265	5	0	0
DetectedOut_A	7934265	608570	0	0
DetectedPulseOut_A	7934265	45	0	0
DisabledIdleSt_A	7934265	5273937	0	0
DisabledNoDetection_A	7934265	5276379	0	0
EnterDebounceSt_A	7934265	110	0	0
EnterDetectSt_A	7934265	50	0	0
EnterStableSt_A	7934265	45	0	0
PulseIsPulse_A	7934265	45	0	0
StayInStableSt	7934265	608525	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_sticky_sva.StableStDropOut_A	7934265	986788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	160	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	2	0	0
T11	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T39	0	2	0	0
T44	0	6	0	0
T49	805	0	0	0
T54	0	4	0	0
T66	0	4	0	0
T67	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	133156	0	0
T2	10916	47	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	74	0	0
T11	0	19	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	56	0	0
T35	0	94	0	0
T39	0	67	0	0
T44	0	282	0	0
T49	805	0	0	0
T54	0	154	0	0
T66	0	237	0	0
T67	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269404	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5	0	0
T34	14275	0	0	0
T36	7762	0	0	0
T44	11608	2	0	0
T55	763	0	0	0
T57	496	0	0	0
T58	490	0	0	0
T67	0	1	0	0
T88	0	1	0	0
T111	28106	0	0	0
T128	0	1	0	0
T129	438	0	0	0
T130	423	0	0	0
T131	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	608570	0	0
T2	10916	8	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	180	0	0
T11	0	141	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T35	0	741	0	0
T44	0	192	0	0
T49	805	0	0	0
T54	0	541	0	0
T66	0	263	0	0
T112	0	47	0	0
T113	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	45	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5273937	0	0
T1	20664	20249	0	0
T2	10916	4219	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5276379	0	0
T1	20664	20257	0	0
T2	10916	4238	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	110	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T44	0	3	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	3	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	3	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	45	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	45	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	608525	0	0
T2	10916	7	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	179	0	0
T11	0	140	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	740	0	0
T44	0	191	0	0
T49	805	0	0	0
T54	0	539	0	0
T66	0	262	0	0
T112	0	46	0	0
T113	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	986788	0	0
T2	10916	128	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	167	0	0
T11	0	462	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	51	0	0
T35	0	74	0	0
T44	0	309	0	0
T49	805	0	0	0
T54	0	355	0	0
T66	0	73	0	0
T112	0	60	0	0
T113	0	240	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T7,T11,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T54
0	1	Covered	T66,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T54
0	1	Unreachable
1	0	Covered	T7,T11,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T7,T11,T54
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T7,T11,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T54
DebounceSt->IdleSt	163	Covered	T2,T39,T66
DetectSt->IdleSt	186	Covered	T66,T92,T93
DetectSt->StableSt	191	Covered	T7,T11,T54
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T7,T11,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T54
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T66,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T66,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T54
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	160	0	0
CntIncr_A	7934265	299984	0	0
CntNoWrap_A	7934265	7269404	0	0
DetectStDropOut_A	7934265	8	0	0
DetectedOut_A	7934265	609065	0	0
DetectedPulseOut_A	7934265	47	0	0
DisabledIdleSt_A	7934265	5273937	0	0
DisabledNoDetection_A	7934265	5276379	0	0
EnterDebounceSt_A	7934265	105	0	0
EnterDetectSt_A	7934265	55	0	0
EnterStableSt_A	7934265	47	0	0
PulseIsPulse_A	7934265	47	0	0
StayInStableSt	7934265	609018	0	0
gen_high_event_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_sticky_sva.StableStDropOut_A	7934265	223580	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	160	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	2	0	0
T11	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T39	0	2	0	0
T44	0	2	0	0
T49	805	0	0	0
T54	0	4	0	0
T66	0	5	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	299984	0	0
T2	10916	19	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	81	0	0
T11	0	69	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	95	0	0
T35	0	74	0	0
T39	0	69	0	0
T44	0	97	0	0
T49	805	0	0	0
T54	0	42	0	0
T66	0	229	0	0
T67	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269404	0	0
T1	20664	20249	0	0
T2	10916	4421	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	8	0	0
T64	502	0	0	0
T66	13073	1	0	0
T67	1362	0	0	0
T92	0	1	0	0
T93	0	2	0	0
T97	8843	0	0	0
T118	0	1	0	0
T122	18493	0	0	0
T123	25338	0	0	0
T124	502	0	0	0
T125	524	0	0	0
T126	499	0	0	0
T127	19207	0	0	0
T128	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	609065	0	0
T7	1660	203	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	480	0	0
T31	31361	0	0	0
T34	0	9	0	0
T35	0	430	0	0
T44	0	850	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	219	0	0
T61	507	0	0	0
T66	0	214	0	0
T109	772	0	0	0
T112	0	10	0	0
T113	0	232	0	0
T114	0	365884	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	47	0	0
T7	1660	1	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	1	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	2	0	0
T61	507	0	0	0
T66	0	1	0	0
T109	772	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5273937	0	0
T1	20664	20249	0	0
T2	10916	4219	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5276379	0	0
T1	20664	20257	0	0
T2	10916	4238	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	105	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T54	0	2	0	0
T66	0	3	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	55	0	0
T7	1660	1	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	1	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	2	0	0
T61	507	0	0	0
T66	0	2	0	0
T109	772	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	47	0	0
T7	1660	1	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	1	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	2	0	0
T61	507	0	0	0
T66	0	1	0	0
T109	772	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	47	0	0
T7	1660	1	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	1	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	2	0	0
T61	507	0	0	0
T66	0	1	0	0
T109	772	0	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	609018	0	0
T7	1660	202	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	479	0	0
T31	31361	0	0	0
T34	0	8	0	0
T35	0	429	0	0
T44	0	849	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	217	0	0
T61	507	0	0	0
T66	0	213	0	0
T109	772	0	0	0
T112	0	9	0	0
T113	0	231	0	0
T114	0	365883	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	223580	0	0
T7	1660	142	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	80	0	0
T31	31361	0	0	0
T34	0	24	0	0
T35	0	417	0	0
T44	0	49	0	0
T45	656	0	0	0
T46	599	0	0	0
T54	0	823	0	0
T61	507	0	0	0
T66	0	135	0	0
T109	772	0	0	0
T112	0	145	0	0
T113	0	34	0	0
T114	0	108	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T10,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T44
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T10,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T44
0	1	Covered	T36,T35,T42
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T44
1	-	Covered	T36,T35,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T44
DetectSt	168	Covered	T2,T10,T44
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T10,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T44
DebounceSt->IdleSt	163	Covered	T89,T134
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T10,T44
IdleSt->DebounceSt	148	Covered	T2,T10,T44
StableSt->IdleSt	206	Covered	T2,T10,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T44
0	1	Covered	T2,T10,T44
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T44
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T35,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	76	0	0
CntIncr_A	7934265	19021	0	0
CntNoWrap_A	7934265	7269488	0	0
DetectStDropOut_A	7934265	0	0	0
DetectedOut_A	7934265	3450	0	0
DetectedPulseOut_A	7934265	37	0	0
DisabledIdleSt_A	7934265	7216545	0	0
DisabledNoDetection_A	7934265	7218938	0	0
EnterDebounceSt_A	7934265	39	0	0
EnterDetectSt_A	7934265	37	0	0
EnterStableSt_A	7934265	37	0	0
PulseIsPulse_A	7934265	37	0	0
StayInStableSt	7934265	3396	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	76	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	19021	0	0
T2	10916	76	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	54	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	42	0	0
T36	0	116	0	0
T39	0	41	0	0
T41	0	48	0	0
T42	0	150	0	0
T44	0	81	0	0
T49	805	0	0	0
T89	0	54	0	0
T94	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269488	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3450	0	0
T2	10916	54	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	244	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	127	0	0
T36	0	191	0	0
T39	0	2	0	0
T41	0	51	0	0
T42	0	84	0	0
T44	0	37	0	0
T49	805	0	0	0
T94	0	108	0	0
T135	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T94	0	1	0	0
T135	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7216545	0	0
T1	20664	20249	0	0
T2	10916	3840	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7218938	0	0
T1	20664	20257	0	0
T2	10916	3858	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	39	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T94	0	1	0	0
T135	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T94	0	1	0	0
T135	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T94	0	1	0	0
T135	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3396	0	0
T2	10916	52	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	242	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	125	0	0
T36	0	188	0	0
T39	0	1	0	0
T41	0	50	0	0
T42	0	82	0	0
T44	0	35	0	0
T49	805	0	0	0
T94	0	107	0	0
T135	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	18	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	1	0	0
T39	7570	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T59	495	0	0	0
T94	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T9,T10,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T4,T1,T2
1	1	Covered	T9,T10,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T38
0	1	Covered	T41,T146,T147
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T38
0	1	Covered	T10,T36,T35
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T38
1	-	Covered	T10,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T22
DetectSt	168	Covered	T9,T10,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T9,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T38
DebounceSt->IdleSt	163	Covered	T22,T148,T149
DetectSt->IdleSt	186	Covered	T39,T41,T146
DetectSt->StableSt	191	Covered	T9,T10,T38
IdleSt->DebounceSt	148	Covered	T9,T10,T22
StableSt->IdleSt	206	Covered	T10,T38,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T38
0	1	Covered	T9,T10,T22
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T147,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T22
DetectSt	-	-	-	-	1	-	-	Covered	T39,T41,T146
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	131	0	0
CntIncr_A	7934265	14628	0	0
CntNoWrap_A	7934265	7269433	0	0
DetectStDropOut_A	7934265	3	0	0
DetectedOut_A	7934265	9022	0	0
DetectedPulseOut_A	7934265	60	0	0
DisabledIdleSt_A	7934265	7233088	0	0
DisabledNoDetection_A	7934265	7235479	0	0
EnterDebounceSt_A	7934265	70	0	0
EnterDetectSt_A	7934265	64	0	0
EnterStableSt_A	7934265	60	0	0
PulseIsPulse_A	7934265	60	0	0
StayInStableSt	7934265	8935	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	2730	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	131	0	0
T9	621	2	0	0
T10	5402	2	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	2	0	0
T35	0	8	0	0
T36	0	8	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	4	0	0
T42	0	6	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T109	772	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14628	0	0
T9	621	59	0	0
T10	5402	54	0	0
T11	2172	0	0	0
T22	0	5880	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	11	0	0
T35	0	4073	0	0
T36	0	244	0	0
T38	0	26	0	0
T39	0	41	0	0
T42	0	225	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	77	0	0
T109	772	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269433	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3	0	0
T41	6717	1	0	0
T99	22297	0	0	0
T100	5218	0	0	0
T113	1319	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	21037	0	0	0
T152	521	0	0	0
T153	403	0	0	0
T154	450	0	0	0
T155	413	0	0	0
T156	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	9022	0	0
T9	621	153	0	0
T10	5402	2	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	51	0	0
T35	0	3868	0	0
T36	0	276	0	0
T38	0	68	0	0
T41	0	50	0	0
T42	0	206	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	39	0	0
T109	772	0	0	0
T157	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	60	0	0
T9	621	1	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T109	772	0	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7233088	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7235479	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	70	0	0
T9	621	1	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T22	0	1	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	3	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T109	772	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T9	621	1	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	3	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T109	772	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	60	0	0
T9	621	1	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T109	772	0	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	60	0	0
T9	621	1	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T109	772	0	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	8935	0	0
T9	621	151	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T34	0	49	0	0
T35	0	3863	0	0
T36	0	271	0	0
T38	0	66	0	0
T41	0	48	0	0
T42	0	202	0	0
T46	599	0	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T61	507	0	0	0
T89	0	37	0	0
T109	772	0	0	0
T157	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2730	0	0
T1	20664	0	0	0
T2	10916	35	0	0
T3	6381	0	0	0
T4	2743	4	0	0
T6	0	8	0	0
T12	336610	0	0	0
T13	423	1	0	0
T14	675	0	0	0
T15	423	3	0	0
T16	442	7	0	0
T17	502	5	0	0
T23	0	18	0	0
T50	0	2	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T32	29183	0	0	0
T35	0	3	0	0
T36	0	3	0	0
T38	28370	0	0	0
T42	0	2	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T109	772	0	0	0
T138	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0