Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T10,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T10,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T36
0	1	Covered	T2,T36,T42
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T36
1	-	Covered	T2,T36,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T36
DetectSt	168	Covered	T2,T10,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T36
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T10,T36
IdleSt->DebounceSt	148	Covered	T2,T10,T36
StableSt->IdleSt	206	Covered	T2,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T36
0	1	Covered	T2,T10,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T36,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	96	0	0
CntIncr_A	7934265	87346	0	0
CntNoWrap_A	7934265	7269468	0	0
DetectStDropOut_A	7934265	0	0	0
DetectedOut_A	7934265	123035	0	0
DetectedPulseOut_A	7934265	48	0	0
DisabledIdleSt_A	7934265	6942908	0	0
DisabledNoDetection_A	7934265	6945298	0	0
EnterDebounceSt_A	7934265	48	0	0
EnterDetectSt_A	7934265	48	0	0
EnterStableSt_A	7934265	48	0	0
PulseIsPulse_A	7934265	48	0	0
StayInStableSt	7934265	122962	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	96	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T39	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T49	805	0	0	0
T94	0	2	0	0
T157	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	87346	0	0
T2	10916	76	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	54	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	4010	0	0
T36	0	122	0	0
T39	0	41	0	0
T42	0	75	0	0
T43	0	40	0	0
T49	805	0	0	0
T94	0	68	0	0
T157	0	49	0	0
T163	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269468	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	123035	0	0
T2	10916	40	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	44	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	45	0	0
T36	0	400	0	0
T39	0	1	0	0
T42	0	117	0	0
T43	0	132	0	0
T49	805	0	0	0
T94	0	111	0	0
T157	0	41	0	0
T163	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6942908	0	0
T1	20664	20249	0	0
T2	10916	3575	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6945298	0	0
T1	20664	20257	0	0
T2	10916	3592	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T94	0	1	0	0
T157	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	122962	0	0
T2	10916	39	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	42	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	43	0	0
T36	0	397	0	0
T42	0	116	0	0
T43	0	129	0	0
T49	805	0	0	0
T94	0	109	0	0
T135	0	38	0	0
T157	0	39	0	0
T163	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	21	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T36	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	1	0	0
T146	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T38
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T38
0	1	Covered	T164
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T38
0	1	Covered	T2,T10,T34
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T38
1	-	Covered	T2,T10,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T38
DetectSt	168	Covered	T2,T10,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T38
DebounceSt->IdleSt	163	Covered	T122,T96,T160
DetectSt->IdleSt	186	Covered	T39,T164
DetectSt->StableSt	191	Covered	T2,T10,T38
IdleSt->DebounceSt	148	Covered	T2,T10,T38
StableSt->IdleSt	206	Covered	T2,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T38
0	1	Covered	T2,T10,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T96,T160,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39,T164
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	108	0	0
CntIncr_A	7934265	3004	0	0
CntNoWrap_A	7934265	7269456	0	0
DetectStDropOut_A	7934265	1	0	0
DetectedOut_A	7934265	3399	0	0
DetectedPulseOut_A	7934265	50	0	0
DisabledIdleSt_A	7934265	7246849	0	0
DisabledNoDetection_A	7934265	7249250	0	0
EnterDebounceSt_A	7934265	57	0	0
EnterDetectSt_A	7934265	52	0	0
EnterStableSt_A	7934265	50	0	0
PulseIsPulse_A	7934265	50	0	0
StayInStableSt	7934265	3335	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	3110	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	108	0	0
T2	10916	4	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T36	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T49	805	0	0	0
T89	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3004	0	0
T2	10916	152	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	54	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	11	0	0
T36	0	106	0	0
T38	0	26	0	0
T39	0	41	0	0
T42	0	150	0	0
T49	805	0	0	0
T89	0	77	0	0
T122	0	22	0	0
T165	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269456	0	0
T1	20664	20249	0	0
T2	10916	4418	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1	0	0
T93	336562	0	0	0
T94	753	0	0	0
T164	537	1	0	0
T166	887	0	0	0
T167	634	0	0	0
T168	671	0	0	0
T169	663	0	0	0
T170	422	0	0	0
T171	501	0	0	0
T172	788	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3399	0	0
T2	10916	308	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	144	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	2	0	0
T36	0	327	0	0
T38	0	41	0	0
T42	0	215	0	0
T43	0	54	0	0
T49	805	0	0	0
T89	0	117	0	0
T164	0	2	0	0
T165	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7246849	0	0
T1	20664	20249	0	0
T2	10916	3840	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7249250	0	0
T1	20664	20257	0	0
T2	10916	3858	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	57	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T122	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	52	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3335	0	0
T2	10916	305	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	143	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	324	0	0
T38	0	39	0	0
T42	0	212	0	0
T43	0	52	0	0
T49	805	0	0	0
T89	0	115	0	0
T164	0	1	0	0
T165	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3110	0	0
T1	20664	0	0	0
T2	10916	50	0	0
T3	6381	0	0	0
T4	2743	5	0	0
T12	336610	0	0	0
T13	423	2	0	0
T14	675	4	0	0
T15	423	1	0	0
T16	442	4	0	0
T17	502	3	0	0
T23	0	15	0	0
T49	0	4	0	0
T50	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	35	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	805	0	0	0
T137	0	1	0	0
T158	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T38
0	1	Covered	T135,T173
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T44
0	1	Covered	T6,T38,T36
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T44
1	-	Covered	T6,T38,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T38
DetectSt	168	Covered	T6,T10,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T38
DebounceSt->IdleSt	163	Covered	T122,T174,T140
DetectSt->IdleSt	186	Covered	T39,T135,T173
DetectSt->StableSt	191	Covered	T6,T10,T38
IdleSt->DebounceSt	148	Covered	T6,T10,T38
StableSt->IdleSt	206	Covered	T6,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T38
0	1	Covered	T6,T10,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T140,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39,T135,T173
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T38,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	145	0	0
CntIncr_A	7934265	148673	0	0
CntNoWrap_A	7934265	7269419	0	0
DetectStDropOut_A	7934265	2	0	0
DetectedOut_A	7934265	62438	0	0
DetectedPulseOut_A	7934265	68	0	0
DisabledIdleSt_A	7934265	6960941	0	0
DisabledNoDetection_A	7934265	6963331	0	0
EnterDebounceSt_A	7934265	75	0	0
EnterDetectSt_A	7934265	71	0	0
EnterStableSt_A	7934265	68	0	0
PulseIsPulse_A	7934265	68	0	0
StayInStableSt	7934265	62343	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	145	0	0
T6	7052	2	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	2	0	0
T11	2172	0	0	0
T36	0	6	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	4	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	148673	0	0
T6	7052	52	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	54	0	0
T11	2172	0	0	0
T36	0	164	0	0
T37	0	130	0	0
T38	0	26	0	0
T39	0	41	0	0
T43	0	20	0	0
T44	0	81	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	108	0	0
T122	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269419	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2	0	0
T75	24024	0	0	0
T118	1191	0	0	0
T135	37234	1	0	0
T173	0	1	0	0
T177	708	0	0	0
T178	806	0	0	0
T179	402	0	0	0
T180	522	0	0	0
T181	796	0	0	0
T182	423	0	0	0
T183	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	62438	0	0
T6	7052	39	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	243	0	0
T11	2172	0	0	0
T36	0	306	0	0
T37	0	46	0	0
T38	0	1	0	0
T43	0	117	0	0
T44	0	241	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	94	0	0
T164	0	52	0	0
T176	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T164	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6960941	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6963331	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	75	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T122	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	71	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T164	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T164	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	62343	0	0
T6	7052	38	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	241	0	0
T11	2172	0	0	0
T36	0	303	0	0
T37	0	44	0	0
T43	0	116	0	0
T44	0	239	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	91	0	0
T163	0	125	0	0
T164	0	51	0	0
T176	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	40	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T158	0	2	0	0
T163	0	2	0	0
T164	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T36,T39,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T36,T39,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T36,T39,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T4,T1,T2
1	1	Covered	T36,T39,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T39,T42
0	1	Covered	T159,T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T42,T43
0	1	Covered	T36,T42,T166
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T39,T42
1	-	Covered	T36,T42,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T39,T42
DetectSt	168	Covered	T36,T39,T42
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T36,T39,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T39,T42
DebounceSt->IdleSt	163	Covered	T185,T186
DetectSt->IdleSt	186	Covered	T159,T184
DetectSt->StableSt	191	Covered	T36,T39,T42
IdleSt->DebounceSt	148	Covered	T36,T39,T42
StableSt->IdleSt	206	Covered	T36,T39,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T39,T42
0	1	Covered	T36,T39,T42
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T39,T42
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T39,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T39,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T185,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T39,T42
DetectSt	-	-	-	-	1	-	-	Covered	T159,T184
DetectSt	-	-	-	-	0	1	-	Covered	T36,T39,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T42
StableSt	-	-	-	-	-	-	0	Covered	T36,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	90	0	0
CntIncr_A	7934265	2556	0	0
CntNoWrap_A	7934265	7269474	0	0
DetectStDropOut_A	7934265	2	0	0
DetectedOut_A	7934265	2661	0	0
DetectedPulseOut_A	7934265	42	0	0
DisabledIdleSt_A	7934265	7241985	0	0
DisabledNoDetection_A	7934265	7244376	0	0
EnterDebounceSt_A	7934265	46	0	0
EnterDetectSt_A	7934265	44	0	0
EnterStableSt_A	7934265	42	0	0
PulseIsPulse_A	7934265	42	0	0
StayInStableSt	7934265	2601	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6630	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	90	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	6	0	0
T39	7570	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T59	495	0	0	0
T137	0	2	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T159	0	2	0	0
T160	0	2	0	0
T164	0	2	0	0
T166	0	4	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2556	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	192	0	0
T39	7570	41	0	0
T42	0	150	0	0
T43	0	20	0	0
T59	495	0	0	0
T137	0	73	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T159	0	47	0	0
T160	0	60	0	0
T164	0	10	0	0
T166	0	98	0	0
T173	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269474	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2	0	0
T137	19401	0	0	0
T159	3086	1	0	0
T160	3356	0	0	0
T184	0	1	0	0
T187	8098	0	0	0
T188	694	0	0	0
T189	508	0	0	0
T190	86252	0	0	0
T191	431	0	0	0
T192	445	0	0	0
T193	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2661	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	127	0	0
T39	7570	1	0	0
T42	0	332	0	0
T43	0	75	0	0
T59	495	0	0	0
T137	0	28	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	278	0	0
T161	0	42	0	0
T164	0	55	0	0
T166	0	88	0	0
T173	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	42	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	3	0	0
T39	7570	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	495	0	0	0
T137	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7241985	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7244376	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	46	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	3	0	0
T39	7570	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	495	0	0	0
T137	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	44	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	3	0	0
T39	7570	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	495	0	0	0
T137	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	42	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	3	0	0
T39	7570	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	495	0	0	0
T137	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	42	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	3	0	0
T39	7570	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T59	495	0	0	0
T137	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2601	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	123	0	0
T39	7570	0	0	0
T42	0	329	0	0
T43	0	73	0	0
T59	495	0	0	0
T137	0	27	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T146	0	53	0	0
T160	0	277	0	0
T161	0	40	0	0
T164	0	53	0	0
T166	0	85	0	0
T173	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6630	0	0
T1	20664	10	0	0
T2	10916	49	0	0
T3	6381	11	0	0
T4	2743	4	0	0
T5	0	28	0	0
T12	336610	5	0	0
T13	423	2	0	0
T14	675	0	0	0
T15	423	1	0	0
T16	442	5	0	0
T17	502	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	22	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	2	0	0
T39	7570	0	0	0
T42	0	1	0	0
T59	495	0	0	0
T121	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T146	0	2	0	0
T160	0	1	0	0
T166	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T9,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T9,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T9,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T9,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T38
0	1	Covered	T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T38
0	1	Covered	T6,T35,T122
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T38
1	-	Covered	T6,T35,T122

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T38
DetectSt	168	Covered	T6,T9,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T38
DebounceSt->IdleSt	163	Covered	T122,T140,T133
DetectSt->IdleSt	186	Covered	T94
DetectSt->StableSt	191	Covered	T6,T9,T38
IdleSt->DebounceSt	148	Covered	T6,T9,T38
StableSt->IdleSt	206	Covered	T6,T38,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T38
0	1	Covered	T6,T9,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T140,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T38
DetectSt	-	-	-	-	1	-	-	Covered	T94
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T35,T39
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	104	0	0
CntIncr_A	7934265	6967	0	0
CntNoWrap_A	7934265	7269460	0	0
DetectStDropOut_A	7934265	1	0	0
DetectedOut_A	7934265	3986	0	0
DetectedPulseOut_A	7934265	50	0	0
DisabledIdleSt_A	7934265	7228196	0	0
DisabledNoDetection_A	7934265	7230593	0	0
EnterDebounceSt_A	7934265	54	0	0
EnterDetectSt_A	7934265	51	0	0
EnterStableSt_A	7934265	50	0	0
PulseIsPulse_A	7934265	50	0	0
StayInStableSt	7934265	3915	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	104	0	0
T6	7052	2	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	2	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6967	0	0
T6	7052	52	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	59	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	42	0	0
T36	0	58	0	0
T37	0	130	0	0
T38	0	26	0	0
T39	0	41	0	0
T42	0	75	0	0
T44	0	81	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	3932	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269460	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1	0	0
T93	336562	0	0	0
T94	753	1	0	0
T163	1125	0	0	0
T166	887	0	0	0
T167	634	0	0	0
T168	671	0	0	0
T169	663	0	0	0
T170	422	0	0	0
T171	501	0	0	0
T172	788	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3986	0	0
T6	7052	39	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	45	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	89	0	0
T36	0	41	0	0
T37	0	228	0	0
T38	0	68	0	0
T39	0	2	0	0
T42	0	364	0	0
T44	0	242	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	1	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7228196	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7230593	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	54	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	1	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	51	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	1	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	1	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	1	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3915	0	0
T6	7052	38	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	43	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	86	0	0
T36	0	39	0	0
T37	0	225	0	0
T38	0	66	0	0
T39	0	1	0	0
T40	0	60	0	0
T42	0	362	0	0
T44	0	240	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	27	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T122	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T157	0	1	0	0
T164	0	2	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T39
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T39,T40
0	1	Covered	T108
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T41
0	1	Covered	T40,T166,T136
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T39,T40
1	-	Covered	T40,T166,T136

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T39,T40
DetectSt	168	Covered	T2,T39,T40
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T39,T40
DebounceSt->IdleSt	163	Covered	T196,T197,T198
DetectSt->IdleSt	186	Covered	T108
DetectSt->StableSt	191	Covered	T2,T39,T40
IdleSt->DebounceSt	148	Covered	T2,T39,T40
StableSt->IdleSt	206	Covered	T2,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T39,T40
0	1	Covered	T2,T39,T40
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T39,T40
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T196,T197,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T108
DetectSt	-	-	-	-	0	1	-	Covered	T2,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T40,T166
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	83	0	0
CntIncr_A	7934265	2574	0	0
CntNoWrap_A	7934265	7269481	0	0
DetectStDropOut_A	7934265	1	0	0
DetectedOut_A	7934265	3429	0	0
DetectedPulseOut_A	7934265	39	0	0
DisabledIdleSt_A	7934265	7252897	0	0
DisabledNoDetection_A	7934265	7255291	0	0
EnterDebounceSt_A	7934265	43	0	0
EnterDetectSt_A	7934265	40	0	0
EnterStableSt_A	7934265	39	0	0
PulseIsPulse_A	7934265	39	0	0
StayInStableSt	7934265	3372	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6260	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	83	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T49	805	0	0	0
T136	0	4	0	0
T137	0	4	0	0
T157	0	2	0	0
T166	0	2	0	0
T176	0	2	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2574	0	0
T2	10916	85	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	41	0	0
T40	0	25	0	0
T41	0	48	0	0
T49	805	0	0	0
T136	0	196	0	0
T137	0	140	0	0
T157	0	49	0	0
T166	0	49	0	0
T176	0	91	0	0
T199	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269481	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1	0	0
T108	56836	1	0	0
T200	496	0	0	0
T201	590	0	0	0
T202	32556	0	0	0
T203	521	0	0	0
T204	912	0	0	0
T205	1444	0	0	0
T206	432	0	0	0
T207	926	0	0	0
T208	410	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3429	0	0
T2	10916	50	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	43	0	0
T41	0	49	0	0
T49	805	0	0	0
T136	0	267	0	0
T137	0	186	0	0
T157	0	41	0	0
T166	0	186	0	0
T176	0	44	0	0
T199	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	39	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T157	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7252897	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7255291	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	43	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T157	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	40	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T157	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	39	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T157	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	39	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T157	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3372	0	0
T2	10916	48	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T40	0	42	0	0
T41	0	47	0	0
T49	805	0	0	0
T136	0	265	0	0
T137	0	184	0	0
T157	0	39	0	0
T160	0	39	0	0
T166	0	185	0	0
T176	0	42	0	0
T199	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6260	0	0
T1	20664	10	0	0
T2	10916	42	0	0
T3	6381	12	0	0
T4	2743	2	0	0
T5	0	30	0	0
T12	336610	0	0	0
T13	423	2	0	0
T14	675	0	0	0
T15	423	3	0	0
T16	442	5	0	0
T17	502	5	0	0
T23	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	19	0	0
T40	20348	1	0	0
T89	20050	0	0	0
T90	8222	0	0	0
T112	602	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T140	0	1	0	0
T160	0	1	0	0
T166	0	1	0	0
T194	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	21630	0	0	0
T212	17267	0	0	0
T213	425	0	0	0
T214	421	0	0	0
T215	525	0	0	0
T216	464	0	0	0