Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	93.48	100.00		100.00	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	93.48	100.00		100.00	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T36,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T22,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T36,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T34
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T22,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T35
0	1	Covered	T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T35
0	1	Covered	T36,T42,T122
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T36,T35
1	-	Covered	T36,T42,T122

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T22,T36
DetectSt	168	Covered	T2,T36,T35
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T36,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T36,T35
DebounceSt->IdleSt	163	Covered	T22,T149,T134
DetectSt->IdleSt	186	Covered	T89
DetectSt->StableSt	191	Covered	T2,T36,T35
IdleSt->DebounceSt	148	Covered	T2,T22,T36
StableSt->IdleSt	206	Covered	T2,T36,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T36,T35
0	1	Covered	T2,T22,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T36,T35
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T22,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T36,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T217,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T22,T36
DetectSt	-	-	-	-	1	-	-	Covered	T89
DetectSt	-	-	-	-	0	1	-	Covered	T2,T36,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T36,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	117	0	0
CntIncr_A	7934265	14430	0	0
CntNoWrap_A	7934265	7269447	0	0
DetectStDropOut_A	7934265	1	0	0
DetectedOut_A	7934265	8728	0	0
DetectedPulseOut_A	7934265	56	0	0
DisabledIdleSt_A	7934265	7204241	0	0
DisabledNoDetection_A	7934265	7206634	0	0
EnterDebounceSt_A	7934265	62	0	0
EnterDetectSt_A	7934265	57	0	0
EnterStableSt_A	7934265	56	0	0
PulseIsPulse_A	7934265	56	0	0
StayInStableSt	7934265	8648	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	117	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T37	0	4	0	0
T39	0	2	0	0
T41	0	4	0	0
T42	0	4	0	0
T49	805	0	0	0
T89	0	6	0	0
T122	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14430	0	0
T2	10916	85	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	5881	0	0
T35	0	21	0	0
T36	0	164	0	0
T37	0	130	0	0
T39	0	41	0	0
T41	0	96	0	0
T42	0	150	0	0
T49	805	0	0	0
T89	0	185	0	0
T122	0	3911	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269447	0	0
T1	20664	20249	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1	0	0
T41	6717	0	0	0
T89	20050	1	0	0
T98	13012	0	0	0
T99	22297	0	0	0
T151	21037	0	0	0
T152	521	0	0	0
T153	403	0	0	0
T154	450	0	0	0
T155	413	0	0	0
T218	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	8728	0	0
T2	10916	176	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	46	0	0
T36	0	108	0	0
T37	0	82	0	0
T39	0	2	0	0
T41	0	139	0	0
T42	0	164	0	0
T49	805	0	0	0
T89	0	82	0	0
T122	0	3955	0	0
T165	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	56	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	2	0	0
T122	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7204241	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7206634	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	62	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	3	0	0
T122	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	57	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	3	0	0
T122	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	56	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	2	0	0
T122	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	56	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	2	0	0
T122	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	8648	0	0
T2	10916	174	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	44	0	0
T36	0	104	0	0
T37	0	79	0	0
T39	0	1	0	0
T41	0	136	0	0
T42	0	161	0	0
T49	805	0	0	0
T89	0	79	0	0
T122	0	3954	0	0
T165	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	30	0	0
T33	6648	0	0	0
T35	57618	0	0	0
T36	7762	2	0	0
T37	0	1	0	0
T39	7570	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	495	0	0	0
T89	0	1	0	0
T122	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T10
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T38
0	1	Covered	T89
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T38
0	1	Covered	T10,T36,T42
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T38
1	-	Covered	T10,T36,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T38
DetectSt	168	Covered	T6,T10,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T10,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T38
DebounceSt->IdleSt	163	Covered	T122
DetectSt->IdleSt	186	Covered	T39,T89
DetectSt->StableSt	191	Covered	T6,T10,T38
IdleSt->DebounceSt	148	Covered	T6,T10,T38
StableSt->IdleSt	206	Covered	T6,T10,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T38
0	1	Covered	T6,T10,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39,T89
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T36,T42
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	72	0	0
CntIncr_A	7934265	1942	0	0
CntNoWrap_A	7934265	7269492	0	0
DetectStDropOut_A	7934265	1	0	0
DetectedOut_A	7934265	3283	0	0
DetectedPulseOut_A	7934265	34	0	0
DisabledIdleSt_A	7934265	7197641	0	0
DisabledNoDetection_A	7934265	7200032	0	0
EnterDebounceSt_A	7934265	37	0	0
EnterDetectSt_A	7934265	36	0	0
EnterStableSt_A	7934265	34	0	0
PulseIsPulse_A	7934265	34	0	0
StayInStableSt	7934265	3230	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6297	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	72	0	0
T6	7052	2	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	2	0	0
T11	2172	0	0	0
T36	0	6	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	2	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1942	0	0
T6	7052	52	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	54	0	0
T11	2172	0	0	0
T36	0	180	0	0
T37	0	65	0	0
T38	0	26	0	0
T39	0	41	0	0
T42	0	75	0	0
T43	0	20	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	54	0	0
T122	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269492	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1	0	0
T41	6717	0	0	0
T89	20050	1	0	0
T98	13012	0	0	0
T99	22297	0	0	0
T151	21037	0	0	0
T152	521	0	0	0
T153	403	0	0	0
T154	450	0	0	0
T155	413	0	0	0
T218	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3283	0	0
T6	7052	37	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	44	0	0
T11	2172	0	0	0
T36	0	296	0	0
T37	0	29	0	0
T38	0	41	0	0
T42	0	167	0	0
T43	0	42	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T136	0	41	0	0
T159	0	135	0	0
T160	0	143	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	34	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T136	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7197641	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7200032	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T122	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	36	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T89	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	34	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T136	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	34	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T136	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3230	0	0
T6	7052	35	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	43	0	0
T11	2172	0	0	0
T36	0	291	0	0
T37	0	28	0	0
T38	0	39	0	0
T42	0	166	0	0
T43	0	41	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T136	0	39	0	0
T159	0	132	0	0
T160	0	141	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6297	0	0
T1	20664	12	0	0
T2	10916	51	0	0
T3	6381	11	0	0
T4	2743	3	0	0
T5	0	25	0	0
T12	336610	0	0	0
T13	423	3	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	5	0	0
T17	502	6	0	0
T23	0	17	0	0
T25	0	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14	0	0
T10	5402	1	0	0
T11	2172	0	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	0	0	0
T32	29183	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	28370	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T109	772	0	0	0
T139	0	2	0	0
T159	0	1	0	0
T194	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T9,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T9,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T9,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T22
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T9,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T44
0	1	Covered	T2,T36,T42
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T44
1	-	Covered	T2,T36,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T44
DetectSt	168	Covered	T2,T9,T44
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T9,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T44
DebounceSt->IdleSt	163	Covered	T165,T43,T174
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T44
IdleSt->DebounceSt	148	Covered	T2,T9,T44
StableSt->IdleSt	206	Covered	T2,T44,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T44
0	1	Covered	T2,T9,T44
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T44
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T165,T43,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T36,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	131	0	0
CntIncr_A	7934265	8260	0	0
CntNoWrap_A	7934265	7269433	0	0
DetectStDropOut_A	7934265	0	0	0
DetectedOut_A	7934265	5050	0	0
DetectedPulseOut_A	7934265	64	0	0
DisabledIdleSt_A	7934265	7200495	0	0
DisabledNoDetection_A	7934265	7202888	0	0
EnterDebounceSt_A	7934265	67	0	0
EnterDetectSt_A	7934265	64	0	0
EnterStableSt_A	7934265	64	0	0
PulseIsPulse_A	7934265	64	0	0
StayInStableSt	7934265	4961	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	131	0	0
T2	10916	4	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	2	0	0
T49	805	0	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	8260	0	0
T2	10916	152	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	59	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	4010	0	0
T36	0	164	0	0
T39	0	41	0	0
T40	0	25	0	0
T41	0	48	0	0
T42	0	150	0	0
T44	0	81	0	0
T49	805	0	0	0
T89	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269433	0	0
T1	20664	20249	0	0
T2	10916	4418	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	5050	0	0
T2	10916	177	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	45	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	46	0	0
T36	0	195	0	0
T39	0	1	0	0
T40	0	128	0	0
T41	0	40	0	0
T42	0	195	0	0
T44	0	296	0	0
T49	805	0	0	0
T89	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7200495	0	0
T1	20664	20249	0	0
T2	10916	3840	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7202888	0	0
T1	20664	20257	0	0
T2	10916	3858	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	67	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T49	805	0	0	0
T89	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	4961	0	0
T2	10916	175	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T9	0	43	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	44	0	0
T36	0	192	0	0
T40	0	126	0	0
T41	0	39	0	0
T42	0	193	0	0
T43	0	43	0	0
T44	0	294	0	0
T49	805	0	0	0
T157	0	57	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T36	0	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T49	805	0	0	0
T89	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T36,T35,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T36,T35,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T36,T35,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T38
1	0	Covered	T4,T1,T2
1	1	Covered	T36,T35,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T35,T37
0	1	Not Covered
1	0	Covered	T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T35,T37
0	1	Covered	T35,T37,T163
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T35,T37
1	-	Covered	T35,T37,T163

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T35,T39
DetectSt	168	Covered	T36,T35,T39
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T36,T35,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T35,T39
DebounceSt->IdleSt	163	Covered	T36,T121,T184
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T36,T35,T37
IdleSt->DebounceSt	148	Covered	T36,T35,T39
StableSt->IdleSt	206	Covered	T36,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T35,T39
0	1	Covered	T36,T35,T39
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T35,T39
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T35,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T35,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T121,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T35,T39
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T36,T35,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T163
StableSt	-	-	-	-	-	-	0	Covered	T36,T35,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	69	0	0
CntIncr_A	7934265	2340	0	0
CntNoWrap_A	7934265	7269495	0	0
DetectStDropOut_A	7934265	0	0	0
DetectedOut_A	7934265	2693	0	0
DetectedPulseOut_A	7934265	31	0	0
DisabledIdleSt_A	7934265	6952922	0	0
DisabledNoDetection_A	7934265	6955318	0	0
EnterDebounceSt_A	7934265	37	0	0
EnterDetectSt_A	7934265	32	0	0
EnterStableSt_A	7934265	31	0	0
PulseIsPulse_A	7934265	31	0	0
StayInStableSt	7934265	2650	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6192	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	69	0	0
T33	6648	0	0	0
T35	57618	4	0	0
T36	7762	5	0	0
T37	0	2	0	0
T39	7570	2	0	0
T59	495	0	0	0
T89	0	2	0	0
T136	0	2	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	2	0	0
T163	0	2	0	0
T194	0	2	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2340	0	0
T33	6648	0	0	0
T35	57618	42	0	0
T36	7762	180	0	0
T37	0	65	0	0
T39	7570	41	0	0
T59	495	0	0	0
T89	0	54	0	0
T136	0	98	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	60	0	0
T163	0	95	0	0
T194	0	11	0	0
T199	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269495	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2693	0	0
T33	6648	0	0	0
T35	57618	117	0	0
T36	7762	197	0	0
T37	0	29	0	0
T39	7570	0	0	0
T59	495	0	0	0
T89	0	38	0	0
T121	0	44	0	0
T136	0	62	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	37	0	0
T163	0	168	0	0
T194	0	43	0	0
T199	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	31	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	2	0	0
T37	0	1	0	0
T39	7570	0	0	0
T59	495	0	0	0
T89	0	1	0	0
T121	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T194	0	1	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6952922	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6955318	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	37	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	3	0	0
T37	0	1	0	0
T39	7570	1	0	0
T59	495	0	0	0
T89	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T194	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	2	0	0
T37	0	1	0	0
T39	7570	1	0	0
T59	495	0	0	0
T89	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T194	0	1	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	31	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	2	0	0
T37	0	1	0	0
T39	7570	0	0	0
T59	495	0	0	0
T89	0	1	0	0
T121	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T194	0	1	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	31	0	0
T33	6648	0	0	0
T35	57618	2	0	0
T36	7762	2	0	0
T37	0	1	0	0
T39	7570	0	0	0
T59	495	0	0	0
T89	0	1	0	0
T121	0	1	0	0
T136	0	1	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T194	0	1	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2650	0	0
T33	6648	0	0	0
T35	57618	114	0	0
T36	7762	193	0	0
T37	0	28	0	0
T39	7570	0	0	0
T59	495	0	0	0
T89	0	36	0	0
T121	0	42	0	0
T136	0	61	0	0
T141	797	0	0	0
T142	503	0	0	0
T143	418	0	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	36	0	0
T163	0	167	0	0
T194	0	41	0	0
T199	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6192	0	0
T1	20664	12	0	0
T2	10916	50	0	0
T3	6381	8	0	0
T4	2743	3	0	0
T5	0	30	0	0
T12	336610	0	0	0
T13	423	2	0	0
T14	675	0	0	0
T15	423	1	0	0
T16	442	5	0	0
T17	502	6	0	0
T23	0	16	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	18	0	0
T35	57618	1	0	0
T37	0	1	0	0
T39	7570	0	0	0
T60	492	0	0	0
T88	0	1	0	0
T136	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T144	562	0	0	0
T145	508	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T184	0	1	0	0
T196	0	2	0	0
T221	530	0	0	0
T222	665	0	0	0
T223	525	0	0	0
T224	506	0	0	0
T225	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T36,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T36,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T36,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T36
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T36,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T35
0	1	Covered	T41,T121,T195
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T35
0	1	Covered	T2,T36,T35
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T36,T35
1	-	Covered	T2,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T36,T35
DetectSt	168	Covered	T2,T36,T35
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T36,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T36,T35
DebounceSt->IdleSt	163	Covered	T135,T161,T226
DetectSt->IdleSt	186	Covered	T41,T121,T195
DetectSt->StableSt	191	Covered	T2,T36,T35
IdleSt->DebounceSt	148	Covered	T2,T36,T35
StableSt->IdleSt	206	Covered	T2,T36,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T36,T35
0	1	Covered	T2,T36,T35
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T36,T35
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T36,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T36,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T135,T161,T226
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T36,T35
DetectSt	-	-	-	-	1	-	-	Covered	T41,T121,T195
DetectSt	-	-	-	-	0	1	-	Covered	T2,T36,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T2,T36,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	147	0	0
CntIncr_A	7934265	25214	0	0
CntNoWrap_A	7934265	7269417	0	0
DetectStDropOut_A	7934265	3	0	0
DetectedOut_A	7934265	9377	0	0
DetectedPulseOut_A	7934265	68	0	0
DisabledIdleSt_A	7934265	7202301	0	0
DisabledNoDetection_A	7934265	7204689	0	0
EnterDebounceSt_A	7934265	76	0	0
EnterDetectSt_A	7934265	71	0	0
EnterStableSt_A	7934265	68	0	0
PulseIsPulse_A	7934265	68	0	0
StayInStableSt	7934265	9284	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	147	0	0
T2	10916	4	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	4	0	0
T49	805	0	0	0
T164	0	2	0	0
T165	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	25214	0	0
T2	10916	152	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	4052	0	0
T36	0	58	0	0
T39	0	41	0	0
T40	0	25	0	0
T41	0	96	0	0
T42	0	150	0	0
T49	805	0	0	0
T164	0	10	0	0
T165	0	75	0	0
T176	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269417	0	0
T1	20664	20249	0	0
T2	10916	4418	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3	0	0
T41	6717	1	0	0
T99	22297	0	0	0
T100	5218	0	0	0
T113	1319	0	0	0
T121	0	1	0	0
T151	21037	0	0	0
T152	521	0	0	0
T153	403	0	0	0
T154	450	0	0	0
T155	413	0	0	0
T156	523	0	0	0
T195	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	9377	0	0
T2	10916	334	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3929	0	0
T36	0	51	0	0
T39	0	2	0	0
T40	0	83	0	0
T41	0	50	0	0
T42	0	89	0	0
T49	805	0	0	0
T164	0	41	0	0
T165	0	43	0	0
T176	0	181	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T49	805	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7202301	0	0
T1	20664	20249	0	0
T2	10916	3840	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7204689	0	0
T1	20664	20257	0	0
T2	10916	3858	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	76	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	71	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	805	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T49	805	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	68	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T49	805	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	9284	0	0
T2	10916	331	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3926	0	0
T36	0	50	0	0
T39	0	1	0	0
T40	0	82	0	0
T41	0	48	0	0
T42	0	86	0	0
T49	805	0	0	0
T164	0	40	0	0
T165	0	41	0	0
T176	0	179	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	41	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	805	0	0	0
T136	0	2	0	0
T137	0	1	0	0
T163	0	2	0	0
T164	0	1	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T6,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T38
1	0	Covered	T4,T1,T2
1	1	Covered	T6,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T35
0	1	Covered	T166,T136,T160
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T34,T35
1	-	Covered	T166,T136,T160

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T34,T35
DetectSt	168	Covered	T6,T34,T35
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T6,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T34,T35
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T34,T35
IdleSt->DebounceSt	148	Covered	T6,T34,T35
StableSt->IdleSt	206	Covered	T6,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T34,T35
0	1	Covered	T6,T34,T35
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T34,T35
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T34,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T34,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T166,T136
StableSt	-	-	-	-	-	-	0	Covered	T6,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	64	0	0
CntIncr_A	7934265	22643	0	0
CntNoWrap_A	7934265	7269500	0	0
DetectStDropOut_A	7934265	0	0	0
DetectedOut_A	7934265	2719	0	0
DetectedPulseOut_A	7934265	32	0	0
DisabledIdleSt_A	7934265	7210716	0	0
DisabledNoDetection_A	7934265	7213122	0	0
EnterDebounceSt_A	7934265	32	0	0
EnterDetectSt_A	7934265	32	0	0
EnterStableSt_A	7934265	32	0	0
PulseIsPulse_A	7934265	32	0	0
StayInStableSt	7934265	2669	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7934265	6867	0	0
gen_low_level_sva.LowLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	64	0	0
T6	7052	2	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	2	0	0
T136	0	4	0	0
T157	0	2	0	0
T166	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	22643	0	0
T6	7052	52	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	11	0	0
T35	0	4010	0	0
T37	0	65	0	0
T39	0	41	0	0
T40	0	25	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	16780	0	0
T136	0	196	0	0
T157	0	49	0	0
T166	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7269500	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2719	0	0
T6	7052	38	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	37	0	0
T35	0	46	0	0
T37	0	41	0	0
T39	0	1	0	0
T40	0	49	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	41	0	0
T136	0	408	0	0
T157	0	121	0	0
T166	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T157	0	1	0	0
T166	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7210716	0	0
T1	20664	20249	0	0
T2	10916	4157	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7213122	0	0
T1	20664	20257	0	0
T2	10916	4175	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T157	0	1	0	0
T166	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T157	0	1	0	0
T166	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T157	0	1	0	0
T166	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	32	0	0
T6	7052	1	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T157	0	1	0	0
T166	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	2669	0	0
T6	7052	36	0	0
T7	1660	0	0	0
T8	10736	0	0	0
T9	621	0	0	0
T10	5402	0	0	0
T11	2172	0	0	0
T34	0	35	0	0
T35	0	44	0	0
T37	0	39	0	0
T40	0	47	0	0
T45	656	0	0	0
T46	599	0	0	0
T52	401	0	0	0
T61	507	0	0	0
T135	0	39	0	0
T136	0	405	0	0
T137	0	116	0	0
T157	0	119	0	0
T166	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6867	0	0
T1	20664	13	0	0
T2	10916	51	0	0
T3	6381	12	0	0
T4	2743	7	0	0
T5	0	36	0	0
T12	336610	5	0	0
T13	423	1	0	0
T14	675	0	0	0
T15	423	3	0	0
T16	442	4	0	0
T17	502	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	12	0	0
T93	336562	0	0	0
T96	538	0	0	0
T108	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T160	0	1	0	0
T163	1125	0	0	0
T166	887	2	0	0
T167	634	0	0	0
T168	671	0	0	0
T169	663	0	0	0
T170	422	0	0	0
T171	501	0	0	0
T172	788	0	0	0
T210	0	1	0	0
T217	0	1	0	0
T219	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0