Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T25,T8
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T8
1	0	Covered	T5,T25,T8
1	1	Covered	T5,T25,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T8
0	1	Covered	T25,T8,T30
1	0	Covered	T25,T8,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T32
0	1	Covered	T5,T31,T32
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T32
1	-	Covered	T5,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T25,T8
DetectSt	168	Covered	T5,T25,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T25,T8
DebounceSt->IdleSt	163	Covered	T39,T229,T230
DetectSt->IdleSt	186	Covered	T25,T8,T30
DetectSt->StableSt	191	Covered	T5,T31,T32
IdleSt->DebounceSt	148	Covered	T5,T25,T8
StableSt->IdleSt	206	Covered	T5,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T25,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T25,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T25,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T25,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	1	-	-	Covered	T25,T8,T30
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T32
DetectSt	-	-	-	-	0	0	-	Covered	T5,T25,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	3025	0	0
CntIncr_A	7934265	98543	0	0
CntNoWrap_A	7934265	7266539	0	0
DetectStDropOut_A	7934265	445	0	0
DetectedOut_A	7934265	70854	0	0
DetectedPulseOut_A	7934265	849	0	0
DisabledIdleSt_A	7934265	6825192	0	0
DisabledNoDetection_A	7934265	6827395	0	0
EnterDebounceSt_A	7934265	1525	0	0
EnterDetectSt_A	7934265	1502	0	0
EnterStableSt_A	7934265	849	0	0
PulseIsPulse_A	7934265	849	0	0
StayInStableSt	7934265	69853	0	0
gen_high_event_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	696	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3025	0	0
T5	33553	16	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	32	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	48	0	0
T30	0	50	0	0
T31	0	34	0	0
T32	0	34	0	0
T33	0	22	0	0
T39	0	16	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	54	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	98543	0	0
T5	33553	352	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	918	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	2190	0	0
T30	0	1107	0	0
T31	0	986	0	0
T32	0	1088	0	0
T33	0	495	0	0
T39	0	492	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	2052	0	0
T64	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7266539	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	445	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	10736	11	0	0
T9	621	0	0	0
T25	7939	22	0	0
T30	0	19	0	0
T39	0	1	0	0
T45	656	0	0	0
T46	599	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T90	0	4	0	0
T98	0	3	0	0
T99	0	6	0	0
T100	0	9	0	0
T231	0	14	0	0
T232	0	28	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	70854	0	0
T5	33553	976	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	2182	0	0
T32	0	2289	0	0
T33	0	656	0	0
T39	0	429	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	1585	0	0
T64	0	77	0	0
T65	0	2044	0	0
T211	0	1123	0	0
T212	0	2734	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	849	0	0
T5	33553	8	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	17	0	0
T32	0	17	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	27	0	0
T64	0	1	0	0
T65	0	20	0	0
T211	0	11	0	0
T212	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6825192	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6827395	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1525	0	0
T5	33553	8	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	16	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	24	0	0
T30	0	25	0	0
T31	0	17	0	0
T32	0	17	0	0
T33	0	11	0	0
T39	0	9	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	27	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1502	0	0
T5	33553	8	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	16	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	24	0	0
T30	0	25	0	0
T31	0	17	0	0
T32	0	17	0	0
T33	0	11	0	0
T39	0	7	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	27	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	849	0	0
T5	33553	8	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	17	0	0
T32	0	17	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	27	0	0
T64	0	1	0	0
T65	0	20	0	0
T211	0	11	0	0
T212	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	849	0	0
T5	33553	8	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	17	0	0
T32	0	17	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	27	0	0
T64	0	1	0	0
T65	0	20	0	0
T211	0	11	0	0
T212	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	69853	0	0
T5	33553	965	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	2158	0	0
T32	0	2263	0	0
T33	0	645	0	0
T39	0	424	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	1555	0	0
T64	0	75	0	0
T65	0	2016	0	0
T211	0	1111	0	0
T212	0	2719	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	696	0	0
T5	33553	5	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T31	0	10	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	4	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	24	0	0
T65	0	12	0	0
T211	0	10	0	0
T212	0	9	0	0
T233	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T4,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T38,T97,T41
1	0	Covered	T39,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T2
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T4,T1,T23
DetectSt->IdleSt	186	Covered	T38,T39,T97
DetectSt->StableSt	191	Covered	T1,T2,T5
IdleSt->DebounceSt	148	Covered	T4,T1,T2
StableSt->IdleSt	206	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T1,T23
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T38,T39,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	921	0	0
CntIncr_A	7934265	45923	0	0
CntNoWrap_A	7934265	7268643	0	0
DetectStDropOut_A	7934265	48	0	0
DetectedOut_A	7934265	14913	0	0
DetectedPulseOut_A	7934265	366	0	0
DisabledIdleSt_A	7934265	6894988	0	0
DisabledNoDetection_A	7934265	6896626	0	0
EnterDebounceSt_A	7934265	505	0	0
EnterDetectSt_A	7934265	418	0	0
EnterStableSt_A	7934265	366	0	0
PulseIsPulse_A	7934265	366	0	0
StayInStableSt	7934265	14510	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	921	0	0
T1	20664	11	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	6	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T23	0	1	0	0
T29	0	8	0	0
T31	0	14	0	0
T32	0	16	0	0
T38	0	6	0	0
T47	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	45923	0	0
T1	20664	768	0	0
T2	10916	25	0	0
T3	6381	0	0	0
T4	2743	20	0	0
T5	0	225	0	0
T10	0	20	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T23	0	20	0	0
T29	0	492	0	0
T31	0	490	0	0
T38	0	409	0	0
T47	0	282	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7268643	0	0
T1	20664	20238	0	0
T2	10916	4420	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	48	0	0
T30	5499	0	0	0
T32	29183	0	0	0
T38	28370	3	0	0
T41	0	1	0	0
T44	11608	0	0	0
T48	657	0	0	0
T56	491	0	0	0
T62	522	0	0	0
T75	0	5	0	0
T80	405	0	0	0
T81	402	0	0	0
T97	0	5	0	0
T101	0	2	0	0
T102	0	1	0	0
T104	0	2	0	0
T105	0	9	0	0
T106	0	5	0	0
T107	0	1	0	0
T110	445	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14913	0	0
T1	20664	75	0	0
T2	10916	3	0	0
T3	6381	0	0	0
T5	33553	163	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	43	0	0
T31	0	404	0	0
T32	0	749	0	0
T34	0	33	0	0
T39	0	69	0	0
T47	0	129	0	0
T111	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	366	0	0
T1	20664	5	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	4	0	0
T31	0	7	0	0
T32	0	8	0	0
T34	0	6	0	0
T39	0	1	0	0
T47	0	2	0	0
T111	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6894988	0	0
T1	20664	16114	0	0
T2	10916	4317	0	0
T3	6381	2014	0	0
T4	2743	468	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6896626	0	0
T1	20664	16114	0	0
T2	10916	4335	0	0
T3	6381	2014	0	0
T4	2743	473	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	505	0	0
T1	20664	6	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T4	2743	1	0	0
T5	0	3	0	0
T10	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T23	0	1	0	0
T29	0	4	0	0
T31	0	7	0	0
T38	0	3	0	0
T47	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	418	0	0
T1	20664	5	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	4	0	0
T31	0	7	0	0
T32	0	8	0	0
T34	0	6	0	0
T38	0	3	0	0
T47	0	2	0	0
T111	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	366	0	0
T1	20664	5	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	4	0	0
T31	0	7	0	0
T32	0	8	0	0
T34	0	6	0	0
T39	0	1	0	0
T47	0	2	0	0
T111	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	366	0	0
T1	20664	5	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	4	0	0
T31	0	7	0	0
T32	0	8	0	0
T34	0	6	0	0
T39	0	1	0	0
T47	0	2	0	0
T111	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14510	0	0
T1	20664	70	0	0
T2	10916	2	0	0
T3	6381	0	0	0
T5	33553	160	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	39	0	0
T31	0	397	0	0
T32	0	741	0	0
T34	0	27	0	0
T39	0	68	0	0
T47	0	127	0	0
T111	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	326	0	0
T1	20664	5	0	0
T2	10916	1	0	0
T3	6381	0	0	0
T5	33553	3	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T29	0	4	0	0
T31	0	7	0	0
T32	0	8	0	0
T34	0	6	0	0
T47	0	2	0	0
T63	0	2	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T25,T8
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T8
1	0	Covered	T5,T25,T8
1	1	Covered	T5,T25,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T8
0	1	Covered	T25,T8,T100
1	0	Covered	T25,T8,T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T32
0	1	Covered	T5,T31,T32
1	0	Covered	T39

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T31,T32
1	-	Covered	T5,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T25,T8
DetectSt	168	Covered	T5,T25,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T25,T8
DebounceSt->IdleSt	163	Covered	T39,T229,T230
DetectSt->IdleSt	186	Covered	T25,T8,T39
DetectSt->StableSt	191	Covered	T5,T31,T32
IdleSt->DebounceSt	148	Covered	T5,T25,T8
StableSt->IdleSt	206	Covered	T5,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T25,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T25,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T25,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T25,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	1	-	-	Covered	T25,T8,T39
DetectSt	-	-	-	-	0	1	-	Covered	T5,T31,T32
DetectSt	-	-	-	-	0	0	-	Covered	T5,T25,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T5,T31,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	3055	0	0
CntIncr_A	7934265	100601	0	0
CntNoWrap_A	7934265	7266509	0	0
DetectStDropOut_A	7934265	347	0	0
DetectedOut_A	7934265	87791	0	0
DetectedPulseOut_A	7934265	1006	0	0
DisabledIdleSt_A	7934265	6814586	0	0
DisabledNoDetection_A	7934265	6816800	0	0
EnterDebounceSt_A	7934265	1545	0	0
EnterDetectSt_A	7934265	1511	0	0
EnterStableSt_A	7934265	1006	0	0
PulseIsPulse_A	7934265	1006	0	0
StayInStableSt	7934265	86644	0	0
gen_high_event_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	863	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3055	0	0
T5	33553	26	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	32	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	16	0	0
T30	0	18	0	0
T31	0	34	0	0
T32	0	16	0	0
T33	0	22	0	0
T39	0	15	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	20	0	0
T65	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	100601	0	0
T5	33553	962	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	918	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	722	0	0
T30	0	342	0	0
T31	0	782	0	0
T32	0	528	0	0
T33	0	440	0	0
T39	0	451	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	830	0	0
T65	0	539	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7266509	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	347	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	10736	11	0	0
T9	621	0	0	0
T25	7939	7	0	0
T45	656	0	0	0
T46	599	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T100	0	11	0	0
T230	0	16	0	0
T231	0	8	0	0
T232	0	28	0	0
T234	0	7	0	0
T235	0	18	0	0
T236	0	11	0	0
T237	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	87791	0	0
T5	33553	2169	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	727	0	0
T31	0	2386	0	0
T32	0	475	0	0
T33	0	711	0	0
T39	0	354	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	275	0	0
T65	0	1043	0	0
T211	0	415	0	0
T212	0	1591	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1006	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	9	0	0
T31	0	17	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	11	0	0
T211	0	2	0	0
T212	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6814586	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6816800	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1545	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	16	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	8	0	0
T30	0	9	0	0
T31	0	17	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	9	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1511	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	16	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	8	0	0
T30	0	9	0	0
T31	0	17	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1006	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	9	0	0
T31	0	17	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	11	0	0
T211	0	2	0	0
T212	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1006	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	9	0	0
T31	0	17	0	0
T32	0	8	0	0
T33	0	11	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	11	0	0
T211	0	2	0	0
T212	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	86644	0	0
T5	33553	2147	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	718	0	0
T31	0	2362	0	0
T32	0	464	0	0
T33	0	700	0	0
T39	0	349	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	265	0	0
T65	0	1028	0	0
T211	0	412	0	0
T212	0	1578	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	863	0	0
T5	33553	4	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T30	0	9	0	0
T31	0	10	0	0
T32	0	5	0	0
T33	0	11	0	0
T39	0	4	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	10	0	0
T65	0	7	0	0
T211	0	1	0	0
T212	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T89,T41,T238
1	0	Covered	T39,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T31
1	0	Covered	T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T5
1	-	Covered	T1,T3,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T5
DetectSt	168	Covered	T1,T3,T5
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T5
DebounceSt->IdleSt	163	Covered	T1,T3,T22
DetectSt->IdleSt	186	Covered	T22,T39,T89
DetectSt->StableSt	191	Covered	T1,T3,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T5
StableSt->IdleSt	206	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T39,T89,T41
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	950	0	0
CntIncr_A	7934265	53238	0	0
CntNoWrap_A	7934265	7268614	0	0
DetectStDropOut_A	7934265	42	0	0
DetectedOut_A	7934265	16411	0	0
DetectedPulseOut_A	7934265	406	0	0
DisabledIdleSt_A	7934265	6882878	0	0
DisabledNoDetection_A	7934265	6884613	0	0
EnterDebounceSt_A	7934265	498	0	0
EnterDetectSt_A	7934265	454	0	0
EnterStableSt_A	7934265	406	0	0
PulseIsPulse_A	7934265	406	0	0
StayInStableSt	7934265	15970	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	369	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	950	0	0
T1	20664	7	0	0
T2	10916	0	0	0
T3	6381	15	0	0
T5	33553	14	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	8	0	0
T29	0	8	0	0
T30	0	4	0	0
T31	0	14	0	0
T32	0	6	0	0
T38	0	4	0	0
T111	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	53238	0	0
T1	20664	510	0	0
T2	10916	0	0	0
T3	6381	571	0	0
T5	33553	378	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	489	0	0
T29	0	300	0	0
T30	0	114	0	0
T31	0	476	0	0
T32	0	186	0	0
T38	0	182	0	0
T111	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7268614	0	0
T1	20664	20242	0	0
T2	10916	4422	0	0
T3	6381	5965	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	42	0	0
T41	6717	8	0	0
T89	20050	6	0	0
T98	13012	0	0	0
T99	22297	0	0	0
T151	21037	0	0	0
T152	521	0	0	0
T153	403	0	0	0
T154	450	0	0	0
T155	413	0	0	0
T184	0	3	0	0
T218	425	0	0	0
T238	0	3	0	0
T239	0	1	0	0
T240	0	8	0	0
T241	0	2	0	0
T242	0	1	0	0
T243	0	5	0	0
T244	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	16411	0	0
T1	20664	27	0	0
T2	10916	0	0	0
T3	6381	508	0	0
T5	33553	514	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	37	0	0
T29	0	235	0	0
T30	0	132	0	0
T31	0	418	0	0
T32	0	230	0	0
T38	0	92	0	0
T111	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	406	0	0
T1	20664	3	0	0
T2	10916	0	0	0
T3	6381	7	0	0
T5	33553	7	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6882878	0	0
T1	20664	16114	0	0
T2	10916	4422	0	0
T3	6381	2014	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6884613	0	0
T1	20664	16114	0	0
T2	10916	4441	0	0
T3	6381	2014	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	498	0	0
T1	20664	4	0	0
T2	10916	0	0	0
T3	6381	8	0	0
T5	33553	7	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	5	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	454	0	0
T1	20664	3	0	0
T2	10916	0	0	0
T3	6381	7	0	0
T5	33553	7	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	4	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	406	0	0
T1	20664	3	0	0
T2	10916	0	0	0
T3	6381	7	0	0
T5	33553	7	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	406	0	0
T1	20664	3	0	0
T2	10916	0	0	0
T3	6381	7	0	0
T5	33553	7	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	15970	0	0
T1	20664	24	0	0
T2	10916	0	0	0
T3	6381	501	0	0
T5	33553	500	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	34	0	0
T29	0	231	0	0
T30	0	130	0	0
T31	0	411	0	0
T32	0	227	0	0
T38	0	90	0	0
T111	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	369	0	0
T1	20664	3	0	0
T2	10916	0	0	0
T3	6381	7	0	0
T5	33553	0	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	3	0	0
T29	0	4	0	0
T30	0	2	0	0
T31	0	7	0	0
T32	0	3	0	0
T34	0	3	0	0
T38	0	2	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T25,T8
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T8
1	0	Covered	T5,T25,T8
1	1	Covered	T5,T25,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
1	0	Covered	T5,T25,T8

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
1	0	Covered	T90,T91

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T31,T32,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T25,T8
DetectSt	168	Covered	T5,T25,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T25,T8
DebounceSt->IdleSt	163	Covered	T39,T229,T230
DetectSt->IdleSt	186	Covered	T5,T25,T8
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T5,T25,T8
StableSt->IdleSt	206	Covered	T31,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T25,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T25,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T25,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T25,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	1	-	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Covered	T5,T25,T8
StableSt	-	-	-	-	-	-	1	Covered	T31,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	3126	0	0
CntIncr_A	7934265	114611	0	0
CntNoWrap_A	7934265	7266438	0	0
DetectStDropOut_A	7934265	456	0	0
DetectedOut_A	7934265	73817	0	0
DetectedPulseOut_A	7934265	837	0	0
DisabledIdleSt_A	7934265	6827204	0	0
DisabledNoDetection_A	7934265	6829419	0	0
EnterDebounceSt_A	7934265	1582	0	0
EnterDetectSt_A	7934265	1546	0	0
EnterStableSt_A	7934265	837	0	0
PulseIsPulse_A	7934265	837	0	0
StayInStableSt	7934265	72842	0	0
gen_high_event_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	683	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3126	0	0
T5	33553	44	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	46	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	22	0	0
T30	0	26	0	0
T31	0	16	0	0
T32	0	32	0	0
T33	0	16	0	0
T39	0	16	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	18	0	0
T65	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	114611	0	0
T5	33553	1724	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	1328	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1002	0	0
T30	0	576	0	0
T31	0	464	0	0
T32	0	768	0	0
T33	0	336	0	0
T39	0	491	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	567	0	0
T65	0	720	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7266438	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	456	0	0
T5	33553	14	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	12	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	9	0	0
T30	0	4	0	0
T39	0	1	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T100	0	13	0	0
T212	0	7	0	0
T232	0	19	0	0
T235	0	22	0	0
T245	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	73817	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	1083	0	0
T32	29183	1369	0	0
T33	0	483	0	0
T38	28370	0	0	0
T39	0	414	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	735	0	0
T65	0	2144	0	0
T80	405	0	0	0
T81	402	0	0	0
T90	0	14	0	0
T98	0	935	0	0
T99	0	2077	0	0
T109	772	0	0	0
T211	0	649	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	837	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	8	0	0
T32	29183	16	0	0
T33	0	8	0	0
T38	28370	0	0	0
T39	0	5	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	9	0	0
T65	0	20	0	0
T80	405	0	0	0
T81	402	0	0	0
T90	0	14	0	0
T98	0	5	0	0
T99	0	25	0	0
T109	772	0	0	0
T211	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6827204	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6829419	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1582	0	0
T5	33553	22	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	23	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	11	0	0
T30	0	13	0	0
T31	0	8	0	0
T32	0	16	0	0
T33	0	8	0	0
T39	0	9	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	9	0	0
T65	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1546	0	0
T5	33553	22	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	23	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	11	0	0
T30	0	13	0	0
T31	0	8	0	0
T32	0	16	0	0
T33	0	8	0	0
T39	0	7	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	9	0	0
T65	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	837	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	8	0	0
T32	29183	16	0	0
T33	0	8	0	0
T38	28370	0	0	0
T39	0	5	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	9	0	0
T65	0	20	0	0
T80	405	0	0	0
T81	402	0	0	0
T90	0	14	0	0
T98	0	5	0	0
T99	0	25	0	0
T109	772	0	0	0
T211	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	837	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	8	0	0
T32	29183	16	0	0
T33	0	8	0	0
T38	28370	0	0	0
T39	0	5	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	9	0	0
T65	0	20	0	0
T80	405	0	0	0
T81	402	0	0	0
T90	0	14	0	0
T98	0	5	0	0
T99	0	25	0	0
T109	772	0	0	0
T211	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	72842	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	1071	0	0
T32	29183	1349	0	0
T33	0	475	0	0
T38	28370	0	0	0
T39	0	409	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	725	0	0
T65	0	2116	0	0
T80	405	0	0	0
T81	402	0	0	0
T98	0	929	0	0
T99	0	2048	0	0
T109	772	0	0	0
T211	0	642	0	0
T233	0	5592	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	683	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T31	31361	4	0	0
T32	29183	12	0	0
T33	0	8	0	0
T38	28370	0	0	0
T39	0	5	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T63	0	8	0	0
T65	0	12	0	0
T80	405	0	0	0
T81	402	0	0	0
T98	0	4	0	0
T99	0	21	0	0
T109	772	0	0	0
T211	0	5	0	0
T233	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T38,T34,T39
1	0	Covered	T39,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T33,T39,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T29,T47,T111
DetectSt->IdleSt	186	Covered	T38,T34,T39
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T47,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T38,T34,T39
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	927	0	0
CntIncr_A	7934265	50161	0	0
CntNoWrap_A	7934265	7268637	0	0
DetectStDropOut_A	7934265	88	0	0
DetectedOut_A	7934265	17254	0	0
DetectedPulseOut_A	7934265	349	0	0
DisabledIdleSt_A	7934265	6894604	0	0
DisabledNoDetection_A	7934265	6896325	0	0
EnterDebounceSt_A	7934265	488	0	0
EnterDetectSt_A	7934265	440	0	0
EnterStableSt_A	7934265	349	0	0
PulseIsPulse_A	7934265	349	0	0
StayInStableSt	7934265	16897	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	335	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	927	0	0
T1	20664	4	0	0
T2	10916	0	0	0
T3	6381	8	0	0
T5	33553	0	0	0
T6	0	2	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	4	0	0
T29	0	21	0	0
T31	0	8	0	0
T32	0	8	0	0
T38	0	16	0	0
T47	0	14	0	0
T111	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	50161	0	0
T1	20664	218	0	0
T2	10916	0	0	0
T3	6381	400	0	0
T5	33553	0	0	0
T6	0	150	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	133	0	0
T29	0	1050	0	0
T31	0	188	0	0
T32	0	220	0	0
T38	0	1096	0	0
T47	0	1112	0	0
T111	0	1028	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7268637	0	0
T1	20664	20245	0	0
T2	10916	4422	0	0
T3	6381	5972	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	88	0	0
T30	5499	0	0	0
T32	29183	0	0	0
T34	0	2	0	0
T38	28370	8	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	11608	0	0	0
T48	657	0	0	0
T56	491	0	0	0
T62	522	0	0	0
T80	405	0	0	0
T81	402	0	0	0
T101	0	1	0	0
T110	445	0	0	0
T238	0	4	0	0
T246	0	2	0	0
T247	0	9	0	0
T248	0	6	0	0
T249	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	17254	0	0
T1	20664	87	0	0
T2	10916	0	0	0
T3	6381	176	0	0
T5	33553	0	0	0
T6	0	19	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	71	0	0
T29	0	345	0	0
T31	0	327	0	0
T32	0	335	0	0
T33	0	112	0	0
T47	0	52	0	0
T111	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	349	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T47	0	6	0	0
T111	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6894604	0	0
T1	20664	16114	0	0
T2	10916	4422	0	0
T3	6381	2014	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6896325	0	0
T1	20664	16114	0	0
T2	10916	4441	0	0
T3	6381	2014	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	488	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	11	0	0
T31	0	4	0	0
T32	0	4	0	0
T38	0	8	0	0
T47	0	8	0	0
T111	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	440	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	4	0	0
T38	0	8	0	0
T47	0	6	0	0
T111	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	349	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T47	0	6	0	0
T111	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	349	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T47	0	6	0	0
T111	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	16897	0	0
T1	20664	85	0	0
T2	10916	0	0	0
T3	6381	172	0	0
T5	33553	0	0	0
T6	0	18	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	69	0	0
T29	0	335	0	0
T31	0	323	0	0
T32	0	331	0	0
T33	0	110	0	0
T47	0	46	0	0
T111	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	335	0	0
T1	20664	2	0	0
T2	10916	0	0	0
T3	6381	4	0	0
T5	33553	0	0	0
T6	0	1	0	0
T12	336610	0	0	0
T13	423	0	0	0
T14	675	0	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T29	0	10	0	0
T31	0	4	0	0
T32	0	4	0	0
T47	0	6	0	0
T111	0	8	0	0
T123	0	6	0	0