Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T25,T8
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T25,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T8
1	0	Covered	T5,T8,T31
1	1	Covered	T5,T25,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T8
0	1	Covered	T31,T30,T39
1	0	Covered	T31,T30,T39

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
1	0	Covered	T250

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T25,T8
1	-	Covered	T5,T25,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T25,T8
DetectSt	168	Covered	T5,T25,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T25,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T25,T8
DebounceSt->IdleSt	163	Covered	T39,T229,T230
DetectSt->IdleSt	186	Covered	T31,T30,T39
DetectSt->StableSt	191	Covered	T5,T25,T8
IdleSt->DebounceSt	148	Covered	T5,T25,T8
StableSt->IdleSt	206	Covered	T5,T25,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T25,T8
0	1	Covered	T5,T25,T8
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T25,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T25,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T25,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T25,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	1	-	-	Covered	T31,T30,T39
DetectSt	-	-	-	-	0	1	-	Covered	T5,T25,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T25,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T25,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T25,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	3061	0	0
CntIncr_A	7934265	100334	0	0
CntNoWrap_A	7934265	7266503	0	0
DetectStDropOut_A	7934265	382	0	0
DetectedOut_A	7934265	89092	0	0
DetectedPulseOut_A	7934265	972	0	0
DisabledIdleSt_A	7934265	6815906	0	0
DisabledNoDetection_A	7934265	6818135	0	0
EnterDebounceSt_A	7934265	1546	0	0
EnterDetectSt_A	7934265	1515	0	0
EnterStableSt_A	7934265	972	0	0
PulseIsPulse_A	7934265	972	0	0
StayInStableSt	7934265	87996	0	0
gen_high_event_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	845	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	3061	0	0
T5	33553	26	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	50	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	6	0	0
T30	0	24	0	0
T31	0	60	0	0
T32	0	26	0	0
T33	0	32	0	0
T39	0	17	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	58	0	0
T65	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	100334	0	0
T5	33553	559	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	1100	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	258	0	0
T30	0	530	0	0
T31	0	2203	0	0
T32	0	598	0	0
T33	0	656	0	0
T39	0	514	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	2030	0	0
T65	0	1254	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7266503	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	382	0	0
T22	25963	0	0	0
T29	34575	0	0	0
T30	0	6	0	0
T31	31361	14	0	0
T32	29183	0	0	0
T38	28370	0	0	0
T39	0	1	0	0
T47	23254	0	0	0
T54	1546	0	0	0
T65	0	14	0	0
T80	405	0	0	0
T81	402	0	0	0
T91	0	18	0	0
T100	0	7	0	0
T109	772	0	0	0
T230	0	13	0	0
T232	0	13	0	0
T235	0	21	0	0
T251	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	89092	0	0
T5	33553	2572	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	1552	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	686	0	0
T32	0	892	0	0
T33	0	1174	0	0
T39	0	447	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	2911	0	0
T90	0	708	0	0
T211	0	3772	0	0
T212	0	1351	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	972	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	25	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T32	0	13	0	0
T33	0	16	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	29	0	0
T90	0	24	0	0
T211	0	25	0	0
T212	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6815906	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5980	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6818135	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1546	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	25	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T30	0	12	0	0
T31	0	30	0	0
T32	0	13	0	0
T33	0	16	0	0
T39	0	10	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	29	0	0
T65	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	1515	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	25	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T30	0	12	0	0
T31	0	30	0	0
T32	0	13	0	0
T33	0	16	0	0
T39	0	7	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	29	0	0
T65	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	972	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	25	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T32	0	13	0	0
T33	0	16	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	29	0	0
T90	0	24	0	0
T211	0	25	0	0
T212	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	972	0	0
T5	33553	13	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	25	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T32	0	13	0	0
T33	0	16	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	29	0	0
T90	0	24	0	0
T211	0	25	0	0
T212	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	87996	0	0
T5	33553	2550	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	1525	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	683	0	0
T32	0	877	0	0
T33	0	1158	0	0
T39	0	442	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	2881	0	0
T90	0	684	0	0
T211	0	3742	0	0
T212	0	1338	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	845	0	0
T5	33553	4	0	0
T6	7052	0	0	0
T7	1660	0	0	0
T8	0	23	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	3	0	0
T32	0	11	0	0
T33	0	16	0	0
T39	0	5	0	0
T49	805	0	0	0
T50	426	0	0	0
T51	524	0	0	0
T52	401	0	0	0
T63	0	28	0	0
T90	0	24	0	0
T211	0	20	0	0
T212	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T25
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T25
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T5,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T25
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T25
0	1	Covered	T123,T247,T248
1	0	Covered	T39,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T25
0	1	Covered	T3,T8,T29
1	0	Covered	T25,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T25
1	-	Covered	T3,T8,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T25
DetectSt	168	Covered	T3,T5,T25
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T5,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T25
DebounceSt->IdleSt	163	Covered	T8,T22,T39
DetectSt->IdleSt	186	Covered	T39,T123,T247
DetectSt->StableSt	191	Covered	T3,T5,T25
IdleSt->DebounceSt	148	Covered	T3,T5,T25
StableSt->IdleSt	206	Covered	T3,T5,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T25
0	1	Covered	T3,T5,T25
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T25
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T39,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T22,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T25
DetectSt	-	-	-	-	1	-	-	Covered	T39,T123,T247
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T25
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T25
StableSt	-	-	-	-	-	-	1	Covered	T3,T25,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7934265	886	0	0
CntIncr_A	7934265	45985	0	0
CntNoWrap_A	7934265	7268678	0	0
DetectStDropOut_A	7934265	38	0	0
DetectedOut_A	7934265	15196	0	0
DetectedPulseOut_A	7934265	378	0	0
DisabledIdleSt_A	7934265	6882818	0	0
DisabledNoDetection_A	7934265	6884562	0	0
EnterDebounceSt_A	7934265	466	0	0
EnterDetectSt_A	7934265	420	0	0
EnterStableSt_A	7934265	378	0	0
PulseIsPulse_A	7934265	378	0	0
StayInStableSt	7934265	14771	0	0
gen_high_level_sva.HighLevelEvent_A	7934265	7272007	0	0
gen_not_sticky_sva.StableStDropOut_A	7934265	326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	886	0	0
T3	6381	22	0	0
T5	33553	10	0	0
T8	0	5	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	3	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	2	0	0
T29	0	10	0	0
T32	0	4	0	0
T38	0	18	0	0
T47	0	12	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	45985	0	0
T3	6381	1507	0	0
T5	33553	235	0	0
T8	0	124	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	122	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	83	0	0
T29	0	515	0	0
T32	0	112	0	0
T38	0	1035	0	0
T47	0	522	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	186	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7268678	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	5958	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	38	0	0
T37	971	0	0	0
T64	502	0	0	0
T67	1362	0	0	0
T97	8843	0	0	0
T101	0	6	0	0
T104	0	3	0	0
T107	0	1	0	0
T108	0	2	0	0
T123	25338	6	0	0
T124	502	0	0	0
T125	524	0	0	0
T126	499	0	0	0
T127	19207	0	0	0
T202	0	3	0	0
T247	0	4	0	0
T248	0	2	0	0
T252	0	2	0	0
T253	0	4	0	0
T254	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	15196	0	0
T3	6381	88	0	0
T5	33553	401	0	0
T8	0	85	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	32	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	75	0	0
T29	0	153	0	0
T32	0	166	0	0
T38	0	200	0	0
T47	0	502	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	179	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	378	0	0
T3	6381	11	0	0
T5	33553	5	0	0
T8	0	2	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6882818	0	0
T1	20664	20249	0	0
T2	10916	4422	0	0
T3	6381	2014	0	0
T4	2743	495	0	0
T12	336610	336209	0	0
T13	423	22	0	0
T14	675	274	0	0
T15	423	22	0	0
T16	442	41	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	6884562	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	2014	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	466	0	0
T3	6381	11	0	0
T5	33553	5	0	0
T8	0	3	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	2	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	420	0	0
T3	6381	11	0	0
T5	33553	5	0	0
T8	0	2	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	378	0	0
T3	6381	11	0	0
T5	33553	5	0	0
T8	0	2	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	378	0	0
T3	6381	11	0	0
T5	33553	5	0	0
T8	0	2	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	14771	0	0
T3	6381	77	0	0
T5	33553	391	0	0
T8	0	83	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	31	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	74	0	0
T29	0	148	0	0
T32	0	164	0	0
T38	0	191	0	0
T47	0	496	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	176	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	7272007	0	0
T1	20664	20257	0	0
T2	10916	4441	0	0
T3	6381	5981	0	0
T4	2743	501	0	0
T12	336610	336210	0	0
T13	423	23	0	0
T14	675	275	0	0
T15	423	23	0	0
T16	442	42	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7934265	326	0	0
T3	6381	11	0	0
T5	33553	0	0	0
T8	0	2	0	0
T15	423	0	0	0
T16	442	0	0	0
T17	502	0	0	0
T22	0	1	0	0
T23	6124	0	0	0
T24	22008	0	0	0
T25	7939	0	0	0
T29	0	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	3	0	0
T38	0	9	0	0
T47	0	6	0	0
T49	805	0	0	0
T50	426	0	0	0
T111	0	3	0	0