Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1143256603	11266	0	0
auto_block_debounce_ctl_rd_A	1143256603	1348	0	0
auto_block_out_ctl_rd_A	1143256603	1420	0	0
com_det_ctl_0_rd_A	1143256603	2865	0	0
com_det_ctl_1_rd_A	1143256603	2886	0	0
com_det_ctl_2_rd_A	1143256603	2945	0	0
com_det_ctl_3_rd_A	1143256603	2992	0	0
com_out_ctl_0_rd_A	1143256603	3273	0	0
com_out_ctl_1_rd_A	1143256603	3105	0	0
com_out_ctl_2_rd_A	1143256603	3226	0	0
com_out_ctl_3_rd_A	1143256603	3215	0	0
com_pre_det_ctl_0_rd_A	1143256603	669	0	0
com_pre_det_ctl_1_rd_A	1143256603	718	0	0
com_pre_det_ctl_2_rd_A	1143256603	743	0	0
com_pre_det_ctl_3_rd_A	1143256603	736	0	0
com_pre_sel_ctl_0_rd_A	1143256603	3466	0	0
com_pre_sel_ctl_1_rd_A	1143256603	3451	0	0
com_pre_sel_ctl_2_rd_A	1143256603	3242	0	0
com_pre_sel_ctl_3_rd_A	1143256603	3136	0	0
com_sel_ctl_0_rd_A	1143256603	3379	0	0
com_sel_ctl_1_rd_A	1143256603	3298	0	0
com_sel_ctl_2_rd_A	1143256603	3413	0	0
com_sel_ctl_3_rd_A	1143256603	3593	0	0
ec_rst_ctl_rd_A	1143256603	1736	0	0
intr_enable_rd_A	1143256603	1258	0	0
key_intr_ctl_rd_A	1143256603	2208	0	0
key_intr_debounce_ctl_rd_A	1143256603	805	0	0
key_invert_ctl_rd_A	1143256603	3680	0	0
pin_allowed_ctl_rd_A	1143256603	4794	0	0
pin_out_ctl_rd_A	1143256603	3651	0	0
pin_out_value_rd_A	1143256603	3699	0	0
regwen_rd_A	1143256603	822	0	0
ulp_ac_debounce_ctl_rd_A	1143256603	863	0	0
ulp_ctl_rd_A	1143256603	914	0	0
ulp_lid_debounce_ctl_rd_A	1143256603	820	0	0
ulp_pwrb_debounce_ctl_rd_A	1143256603	883	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	11266	0	0
T1	258303	0	0	0
T2	499018	2	0	0
T3	765738	0	0	0
T4	134389	11	0	0
T6	0	4	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T22	0	7	0	0
T23	0	7	0	0
T34	0	4	0	0
T35	0	14	0	0
T36	0	6	0	0
T44	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	1348	0	0
T2	499018	16	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	18	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	24	0	0
T40	0	23	0	0
T45	0	15	0	0
T49	100696	0	0	0
T66	0	40	0	0
T92	0	19	0	0
T122	0	15	0	0
T263	0	24	0	0
T264	0	15	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	1420	0	0
T2	499018	14	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	18	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	11	0	0
T40	0	24	0	0
T45	0	9	0	0
T49	100696	0	0	0
T66	0	30	0	0
T92	0	21	0	0
T122	0	29	0	0
T263	0	12	0	0
T264	0	11	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	2865	0	0
T2	499018	11	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	33	0	0
T36	0	7	0	0
T40	0	12	0	0
T49	100696	0	0	0
T65	0	90	0	0
T66	0	46	0	0
T111	0	75	0	0
T122	0	21	0	0
T123	0	52	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	2886	0	0
T2	499018	17	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	9	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	16	0	0
T40	0	3	0	0
T49	100696	0	0	0
T65	0	58	0	0
T66	0	34	0	0
T111	0	66	0	0
T122	0	34	0	0
T123	0	44	0	0
T247	0	45	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	2945	0	0
T2	499018	23	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	6	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	22	0	0
T40	0	11	0	0
T49	100696	0	0	0
T65	0	55	0	0
T66	0	51	0	0
T111	0	79	0	0
T122	0	30	0	0
T123	0	63	0	0
T247	0	61	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	2992	0	0
T2	499018	9	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	9	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	28	0	0
T36	0	4	0	0
T40	0	1	0	0
T49	100696	0	0	0
T65	0	65	0	0
T66	0	40	0	0
T111	0	79	0	0
T122	0	34	0	0
T123	0	40	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3273	0	0
T2	499018	14	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	15	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	18	0	0
T36	0	6	0	0
T40	0	2	0	0
T49	100696	0	0	0
T65	0	42	0	0
T66	0	33	0	0
T111	0	78	0	0
T122	0	16	0	0
T123	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3105	0	0
T2	499018	12	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	10	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	18	0	0
T36	0	11	0	0
T40	0	15	0	0
T49	100696	0	0	0
T65	0	70	0	0
T66	0	44	0	0
T111	0	79	0	0
T122	0	28	0	0
T123	0	48	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3226	0	0
T2	499018	6	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	11	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	23	0	0
T36	0	8	0	0
T40	0	9	0	0
T49	100696	0	0	0
T65	0	66	0	0
T66	0	17	0	0
T111	0	94	0	0
T122	0	18	0	0
T123	0	35	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3215	0	0
T2	499018	10	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	5	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	26	0	0
T40	0	7	0	0
T49	100696	0	0	0
T65	0	47	0	0
T66	0	36	0	0
T111	0	67	0	0
T122	0	8	0	0
T123	0	41	0	0
T247	0	84	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	669	0	0
T2	499018	9	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	10	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	4	0	0
T40	0	7	0	0
T49	100696	0	0	0
T66	0	29	0	0
T92	0	18	0	0
T122	0	24	0	0
T173	0	16	0	0
T263	0	10	0	0
T265	0	9	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	718	0	0
T2	499018	12	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	9	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	3	0	0
T40	0	8	0	0
T49	100696	0	0	0
T66	0	36	0	0
T92	0	2	0	0
T122	0	19	0	0
T173	0	13	0	0
T263	0	15	0	0
T265	0	14	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	743	0	0
T2	499018	12	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	6	0	0
T40	0	11	0	0
T49	100696	0	0	0
T66	0	36	0	0
T92	0	1	0	0
T122	0	24	0	0
T173	0	19	0	0
T242	0	34	0	0
T263	0	10	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	736	0	0
T2	499018	11	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	3	0	0
T40	0	24	0	0
T49	100696	0	0	0
T66	0	35	0	0
T92	0	16	0	0
T122	0	17	0	0
T173	0	8	0	0
T263	0	7	0	0
T265	0	11	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3466	0	0
T2	499018	8	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	15	0	0
T36	0	9	0	0
T40	0	9	0	0
T49	100696	0	0	0
T65	0	74	0	0
T66	0	41	0	0
T111	0	74	0	0
T122	0	31	0	0
T123	0	32	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3451	0	0
T2	499018	16	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	9	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	33	0	0
T36	0	3	0	0
T40	0	22	0	0
T49	100696	0	0	0
T65	0	56	0	0
T66	0	31	0	0
T111	0	66	0	0
T122	0	20	0	0
T123	0	42	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3242	0	0
T2	499018	11	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	11	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	13	0	0
T36	0	15	0	0
T40	0	8	0	0
T49	100696	0	0	0
T65	0	67	0	0
T66	0	52	0	0
T111	0	74	0	0
T122	0	27	0	0
T123	0	27	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3136	0	0
T2	499018	7	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	10	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	27	0	0
T36	0	5	0	0
T40	0	10	0	0
T49	100696	0	0	0
T65	0	54	0	0
T66	0	18	0	0
T111	0	71	0	0
T122	0	25	0	0
T123	0	43	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3379	0	0
T2	499018	16	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	5	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	16	0	0
T36	0	1	0	0
T40	0	11	0	0
T49	100696	0	0	0
T65	0	63	0	0
T66	0	33	0	0
T111	0	76	0	0
T122	0	18	0	0
T123	0	31	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3298	0	0
T2	499018	10	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	10	0	0
T36	0	1	0	0
T40	0	16	0	0
T49	100696	0	0	0
T65	0	80	0	0
T66	0	49	0	0
T111	0	80	0	0
T122	0	21	0	0
T123	0	37	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3413	0	0
T2	499018	13	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	5	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	13	0	0
T40	0	7	0	0
T49	100696	0	0	0
T65	0	75	0	0
T66	0	28	0	0
T111	0	76	0	0
T122	0	17	0	0
T123	0	6	0	0
T247	0	72	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3593	0	0
T2	499018	18	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	3	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	14	0	0
T36	0	9	0	0
T40	0	17	0	0
T49	100696	0	0	0
T65	0	53	0	0
T66	0	34	0	0
T111	0	101	0	0
T122	0	13	0	0
T123	0	34	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	1736	0	0
T2	499018	27	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	2	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	1	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T25	0	7	0	0
T36	0	2	0	0
T49	100696	3	0	0
T66	0	39	0	0
T111	0	42	0	0
T122	0	48	0	0
T141	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	1258	0	0
T2	499018	18	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	19	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	42	0	0
T40	0	19	0	0
T49	100696	0	0	0
T66	0	18	0	0
T92	0	48	0	0
T111	0	5	0	0
T122	0	58	0	0
T263	0	17	0	0
T266	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	2208	0	0
T2	499018	15	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	7	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	7	0	0
T40	0	9	0	0
T49	100696	0	0	0
T66	0	43	0	0
T92	0	11	0	0
T122	0	17	0	0
T158	0	9	0	0
T164	0	3	0	0
T263	0	8	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	805	0	0
T2	499018	9	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	13	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	14	0	0
T40	0	2	0	0
T49	100696	0	0	0
T66	0	35	0	0
T92	0	5	0	0
T122	0	16	0	0
T173	0	16	0	0
T263	0	7	0	0
T265	0	20	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3680	0	0
T2	499018	148	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	5	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T40	0	8	0	0
T49	100696	0	0	0
T57	0	41	0	0
T59	0	44	0	0
T66	0	88	0	0
T92	0	12	0	0
T122	0	131	0	0
T263	0	15	0	0
T267	0	40	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	4794	0	0
T2	499018	77	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	97	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	70	0	0
T40	0	79	0	0
T49	100696	0	0	0
T66	0	114	0	0
T111	0	53	0	0
T122	0	25	0	0
T224	0	77	0	0
T268	0	47	0	0
T269	0	43	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3651	0	0
T2	499018	60	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	58	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	62	0	0
T40	0	82	0	0
T49	100696	0	0	0
T66	0	107	0	0
T111	0	54	0	0
T122	0	18	0	0
T224	0	79	0	0
T268	0	25	0	0
T269	0	85	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	3699	0	0
T2	499018	92	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	70	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	38	0	0
T40	0	109	0	0
T49	100696	0	0	0
T66	0	75	0	0
T111	0	76	0	0
T122	0	27	0	0
T224	0	53	0	0
T268	0	27	0	0
T269	0	47	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	822	0	0
T2	499018	11	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	8	0	0
T12	98009	0	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T40	0	3	0	0
T49	100696	0	0	0
T66	0	41	0	0
T92	0	23	0	0
T122	0	28	0	0
T173	0	19	0	0
T242	0	40	0	0
T263	0	10	0	0
T265	0	14	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	863	0	0
T2	499018	24	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	10	0	0
T12	98009	7	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	6	0	0
T40	0	14	0	0
T49	100696	0	0	0
T66	0	44	0	0
T113	0	5	0	0
T114	0	13	0	0
T122	0	34	0	0
T263	0	14	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	914	0	0
T2	499018	22	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	13	0	0
T12	98009	7	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T36	0	11	0	0
T40	0	13	0	0
T49	100696	0	0	0
T66	0	41	0	0
T113	0	10	0	0
T114	0	16	0	0
T122	0	29	0	0
T263	0	11	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	820	0	0
T2	499018	37	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	7	0	0
T12	98009	8	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T40	0	3	0	0
T49	100696	0	0	0
T55	0	1	0	0
T66	0	43	0	0
T113	0	3	0	0
T114	0	11	0	0
T122	0	28	0	0
T263	0	16	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143256603	883	0	0
T2	499018	19	0	0
T3	765738	0	0	0
T5	922699	0	0	0
T10	0	11	0	0
T12	98009	5	0	0
T13	101655	0	0	0
T14	334136	0	0	0
T15	145863	0	0	0
T16	53006	0	0	0
T17	238546	0	0	0
T40	0	13	0	0
T49	100696	0	0	0
T66	0	45	0	0
T113	0	1	0	0
T114	0	13	0	0
T115	0	15	0	0
T122	0	13	0	0
T263	0	14	0	0