Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2218

1

T1

6

T2

20

T3

23

auto[1]

603

1

T1

9

T2

3

T3

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2091

1

T1

9

T2

6

T3

26

auto[1]

730

1

T1

6

T2

17

T3

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T1

9

T2

17

T3

28

auto[1]

746

1

T1

6

T2

6

T5

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2164

1

T1

13

T2

14

T3

28

auto[1]

657

1

T1

2

T2

9

T5

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2529

1

T1

15

T2

23

T3

26

auto[1]

292

1

T3

2

T7

14

T25

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2571

1

T1

15

T2

23

T3

23

auto[1]

250

1

T3

5

T11

3

T29

7

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2586

1

T1

15

T2

23

T3

26

auto[1]

235

1

T3

2

T25

2

T11

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2551

1

T1

15

T2

23

T3

21

auto[1]

270

1

T3

7

T11

6

T38

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T1

15

T2

23

T3

23

auto[1]

348

1

T3

5

T7

8

T25

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2257

1

T1

9

T2

20

T3

28

auto[1]

564

1

T1

6

T2

3

T5

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

816

1

T1

15

T2

23

T5

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

63

1

T7

8

T11

6

T44

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

135

1

T7

6

T29

8

T39

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T314

2

T315

2

T196

19

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T302

1

T316

3

T195

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T256

3

T314

4

T73

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T173

5

T85

1

T256

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T314

2

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T29

7

T317

1

T318

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T302

3

T73

1

T319

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T320

2

T321

14

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T11

6

T100

5

T256

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T3

2

T193

8

T322

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

81

1

T29

7

T99

1

T311

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T11

1

T319

6

T190

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

8

1

T323

1

T324

3

T310

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T39

1

T325

3

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20

1

T38

2

T326

1

T315

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T256

1

T327

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T3

5

T39

4

T328

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T100

6

T311

7

T195

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T329

3

T311

2

T72

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T11

2

T312

2

T330

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T100

4

T193

9

T331

2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

128

1

T1

9

T3

5

T11

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T99

1

T78

7

T93

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

66

1

T29

7

T32

2

T100

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

103

1

T5

2

T100

6

T83

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T20

1

T83

2

T173

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

75

1

T163

4

T219

4

T167

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T32

4

T332

3

T195

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

140

1

T20

2

T256

1

T236

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

55

1

T80

4

T83

5

T173

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T11

1

T29

7

T83

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

30

1

T38

2

T55

2

T157

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T2

6

T7

6

T39

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T71

1

T333

2

T236

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T76

2

T221

4

T152

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T32

1

T218

1

T226

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

151

1

T2

14

T3

2

T7

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

54

1

T311

6

T94

6

T73

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T5

2

T7

4

T87

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T88

2

T307

1

T305

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T89

7

T334

2

T328

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T80

2

T81

6

T32

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T71

1

T163

3

T90

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T2

3

T80

2

T81

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

98

1

T29

8

T99

3

T85

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T224

1

T332

2

T226

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T1

4

T83

3

T256

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T224

1

T167

1

T170

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T83

3

T90

4

T167

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T5

1

T44

2

T83

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T1

2

T301

1

T152

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T221

3

T304

1

T335

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded