Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121681

1

T1

263

T4

1

T2

282

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146779	1			T1	411		T4	2		T2	420
values[0x0]	66919	1			T1	61		T4	1		T2	74
values[0x1]	67342	1			T1	50		T2	91		T3	341

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151937

1

T1

316

T4

1

T2

344

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	963	1			T1	2		T3	7		T5	12
valid_sources[0x01]	832	1			T1	2		T3	3		T5	6
valid_sources[0x02]	1680	1			T1	3		T3	4		T7	3
valid_sources[0x03]	1024	1			T1	3		T3	1		T7	2
valid_sources[0x04]	1171	1			T1	1		T3	2		T5	3
valid_sources[0x05]	771	1			T1	1		T3	4		T25	1
valid_sources[0x06]	1063	1			T1	2		T3	1		T16	1
valid_sources[0x07]	1047	1			T1	2		T3	2		T5	18
valid_sources[0x08]	776	1			T1	7		T7	7		T25	7
valid_sources[0x09]	833	1			T1	1		T3	2		T16	1
valid_sources[0x0a]	840	1			T1	2		T3	5		T7	2
valid_sources[0x0b]	967	1			T1	2		T3	2		T5	20
valid_sources[0x0c]	828	1			T3	2		T5	16		T7	2
valid_sources[0x0d]	926	1			T1	2		T3	5		T16	1
valid_sources[0x0e]	790	1			T1	1		T3	1		T16	1
valid_sources[0x0f]	1283	1			T1	1		T3	6		T5	2
valid_sources[0x10]	1545	1			T1	6		T3	4		T5	1
valid_sources[0x11]	948	1			T1	3		T3	8		T7	5
valid_sources[0x12]	855	1			T1	1		T3	3		T5	6
valid_sources[0x13]	999	1			T1	3		T3	5		T5	2
valid_sources[0x14]	836	1			T1	4		T3	7		T5	13
valid_sources[0x15]	995	1			T1	1		T3	3		T5	7
valid_sources[0x16]	1970	1			T1	8		T4	1		T5	11
valid_sources[0x17]	1441	1			T3	3		T5	25		T7	1
valid_sources[0x18]	1010	1			T1	1		T3	3		T7	3
valid_sources[0x19]	850	1			T1	1		T3	7		T7	4
valid_sources[0x1a]	957	1			T1	2		T3	3		T5	11
valid_sources[0x1b]	1179	1			T1	2		T3	4		T16	3
valid_sources[0x1c]	1893	1			T1	2		T3	7		T5	2
valid_sources[0x1d]	1104	1			T1	4		T3	5		T5	19
valid_sources[0x1e]	1473	1			T1	2		T3	5		T5	2
valid_sources[0x1f]	1314	1			T1	3		T3	6		T45	2
valid_sources[0x20]	1067	1			T1	1		T3	5		T5	12
valid_sources[0x21]	1219	1			T3	2		T7	2		T25	7
valid_sources[0x22]	942	1			T1	1		T3	6		T5	28
valid_sources[0x23]	1116	1			T1	1		T3	2		T5	13
valid_sources[0x24]	968	1			T3	1		T5	15		T7	1
valid_sources[0x25]	901	1			T1	3		T3	7		T7	8
valid_sources[0x26]	1056	1			T1	5		T3	5		T5	13
valid_sources[0x27]	748	1			T1	3		T3	4		T5	7
valid_sources[0x28]	1044	1			T1	1		T3	4		T5	5
valid_sources[0x29]	823	1			T1	1		T3	8		T5	6
valid_sources[0x2a]	911	1			T1	3		T3	1		T5	14
valid_sources[0x2b]	752	1			T1	2		T3	9		T5	2
valid_sources[0x2c]	848	1			T1	3		T3	4		T7	2
valid_sources[0x2d]	1074	1			T1	4		T3	1		T5	1
valid_sources[0x2e]	860	1			T1	2		T3	1		T7	5
valid_sources[0x2f]	1092	1			T1	2		T3	5		T7	8
valid_sources[0x30]	1162	1			T3	3		T16	1		T25	2
valid_sources[0x31]	858	1			T1	5		T3	6		T7	5
valid_sources[0x32]	890	1			T1	1		T3	3		T7	2
valid_sources[0x33]	1006	1			T1	4		T3	2		T5	30
valid_sources[0x34]	1165	1			T1	4		T3	3		T15	1
valid_sources[0x35]	1797	1			T3	5		T15	4		T7	2
valid_sources[0x36]	701	1			T5	2		T7	5		T25	3
valid_sources[0x37]	2251	1			T1	2		T3	6		T5	1
valid_sources[0x38]	848	1			T3	4		T25	6		T30	1
valid_sources[0x39]	1543	1			T3	3		T7	7		T25	1
valid_sources[0x3a]	928	1			T3	7		T5	3		T7	3
valid_sources[0x3b]	954	1			T1	1		T3	6		T5	6
valid_sources[0x3c]	815	1			T1	1		T3	4		T5	4
valid_sources[0x3d]	957	1			T1	3		T3	8		T5	14
valid_sources[0x3e]	780	1			T3	2		T7	5		T25	3
valid_sources[0x3f]	842	1			T1	1		T3	3		T7	5
valid_sources[0x40]	1240	1			T4	2		T3	5		T5	1
valid_sources[0x41]	1044	1			T1	5		T3	7		T12	2
valid_sources[0x42]	814	1			T1	1		T3	2		T7	1
valid_sources[0x43]	2013	1			T1	3		T3	2		T5	3
valid_sources[0x44]	1118	1			T1	2		T3	4		T7	1
valid_sources[0x45]	1142	1			T1	2		T3	3		T12	1
valid_sources[0x46]	949	1			T1	3		T3	2		T5	11
valid_sources[0x47]	973	1			T1	6		T3	6		T5	2
valid_sources[0x48]	891	1			T3	6		T7	6		T25	6
valid_sources[0x49]	888	1			T1	2		T3	3		T7	5
valid_sources[0x4a]	1062	1			T5	9		T7	3		T25	4
valid_sources[0x4b]	932	1			T1	4		T3	2		T5	1
valid_sources[0x4c]	941	1			T1	2		T3	1		T7	4
valid_sources[0x4d]	750	1			T1	1		T3	3		T5	6
valid_sources[0x4e]	871	1			T1	2		T3	3		T5	15
valid_sources[0x4f]	1231	1			T1	4		T3	3		T5	19
valid_sources[0x50]	1047	1			T1	2		T3	3		T5	3
valid_sources[0x51]	1142	1			T3	3		T5	8		T7	2
valid_sources[0x52]	876	1			T1	1		T3	5		T5	5
valid_sources[0x53]	1948	1			T1	3		T3	2		T5	10
valid_sources[0x54]	1423	1			T1	1		T3	5		T5	1
valid_sources[0x55]	819	1			T1	1		T3	6		T5	5
valid_sources[0x56]	1107	1			T1	1		T3	3		T5	5
valid_sources[0x57]	877	1			T1	2		T3	5		T5	1
valid_sources[0x58]	901	1			T1	3		T3	6		T12	1
valid_sources[0x59]	1087	1			T1	2		T3	1		T12	1
valid_sources[0x5a]	977	1			T1	2		T5	1		T7	7
valid_sources[0x5b]	826	1			T1	3		T3	5		T5	7
valid_sources[0x5c]	933	1			T1	1		T3	9		T5	4
valid_sources[0x5d]	943	1			T1	4		T3	2		T5	8
valid_sources[0x5e]	981	1			T1	2		T2	66		T3	2
valid_sources[0x5f]	979	1			T1	2		T3	3		T7	6
valid_sources[0x60]	965	1			T1	1		T3	2		T5	4
valid_sources[0x61]	1733	1			T1	3		T3	3		T5	11
valid_sources[0x62]	1450	1			T3	4		T5	9		T7	3
valid_sources[0x63]	894	1			T1	2		T3	5		T5	9
valid_sources[0x64]	880	1			T1	1		T3	4		T7	3
valid_sources[0x65]	1090	1			T1	2		T3	6		T16	1
valid_sources[0x66]	957	1			T1	2		T3	5		T5	3
valid_sources[0x67]	1128	1			T1	1		T3	3		T12	2
valid_sources[0x68]	1474	1			T1	1		T3	8		T5	3
valid_sources[0x69]	1744	1			T1	3		T3	6		T5	7
valid_sources[0x6a]	1278	1			T1	3		T3	9		T16	1
valid_sources[0x6b]	933	1			T1	2		T3	1		T5	5
valid_sources[0x6c]	924	1			T1	1		T3	5		T5	6
valid_sources[0x6d]	1072	1			T1	1		T3	2		T15	4
valid_sources[0x6e]	2193	1			T3	5		T5	5		T7	4
valid_sources[0x6f]	898	1			T1	1		T3	4		T16	1
valid_sources[0x70]	1210	1			T1	1		T3	2		T5	4
valid_sources[0x71]	923	1			T1	3		T2	150		T3	1
valid_sources[0x72]	1134	1			T1	2		T3	5		T5	3
valid_sources[0x73]	871	1			T3	1		T5	6		T7	4
valid_sources[0x74]	836	1			T3	3		T12	1		T7	6
valid_sources[0x75]	995	1			T1	1		T3	1		T5	5
valid_sources[0x76]	1352	1			T1	4		T3	2		T5	1
valid_sources[0x77]	903	1			T1	2		T3	5		T5	3
valid_sources[0x78]	902	1			T5	5		T7	5		T25	3
valid_sources[0x79]	1160	1			T1	1		T3	5		T16	1
valid_sources[0x7a]	869	1			T1	2		T7	5		T46	1
valid_sources[0x7b]	958	1			T1	4		T3	2		T12	1
valid_sources[0x7c]	830	1			T1	7		T3	4		T5	15
valid_sources[0x7d]	1433	1			T1	2		T3	5		T5	12
valid_sources[0x7e]	1131	1			T1	3		T3	1		T5	4
valid_sources[0x7f]	996	1			T1	1		T3	2		T5	3
valid_sources[0x80]	969	1			T1	2		T3	2		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66431

1

T1

210

T4

1

T2

214

values[0x0]

all_enables

biggest_size

32510

1

T1

31

T2

32

T3

144

values[0x1]

all_enables

biggest_size

22740

1

T1

22

T2

36

T3

82