Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T14,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T12,T14,T5

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T14,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T12,T14,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T5
0	1	Covered	T70,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T5
0	1	Covered	T12,T14,T5
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T14,T5
1	-	Covered	T12,T14,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T14,T5
DetectSt	168	Covered	T12,T14,T5
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T12,T14,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T14,T5
DebounceSt->IdleSt	163	Covered	T41,T32,T68
DetectSt->IdleSt	186	Covered	T70,T95
DetectSt->StableSt	191	Covered	T12,T14,T5
IdleSt->DebounceSt	148	Covered	T12,T14,T5
StableSt->IdleSt	206	Covered	T12,T14,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T14,T5
0	1	Covered	T12,T14,T5
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T14,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T14,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T32,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T14,T5
DetectSt	-	-	-	-	1	-	-	Covered	T70,T95
DetectSt	-	-	-	-	0	1	-	Covered	T12,T14,T5
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T14,T5
StableSt	-	-	-	-	-	-	0	Covered	T12,T14,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	328	0	0
CntIncr_A	6837408	115736	0	0
CntNoWrap_A	6837408	6132916	0	0
DetectStDropOut_A	6837408	2	0	0
DetectedOut_A	6837408	1052	0	0
DetectedPulseOut_A	6837408	149	0	0
DisabledIdleSt_A	6837408	6009778	0	0
DisabledNoDetection_A	6837408	6012190	0	0
EnterDebounceSt_A	6837408	182	0	0
EnterDetectSt_A	6837408	151	0	0
EnterStableSt_A	6837408	149	0	0
PulseIsPulse_A	6837408	149	0	0
StayInStableSt	6837408	903	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	7242	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	148	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	328	0	0
T5	34049	12	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	4	0	0
T12	728	2	0	0
T13	404	0	0	0
T14	50329	4	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	2	0	0
T43	0	4	0	0
T45	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	115736	0	0
T5	34049	335	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	107	0	0
T12	728	31	0	0
T13	404	0	0	0
T14	50329	49689	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	29	0	0
T24	503	0	0	0
T36	0	84	0	0
T40	0	51	0	0
T41	0	142	0	0
T42	0	99	0	0
T43	0	132	0	0
T45	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6132916	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21222	0	0
T12	728	325	0	0
T13	404	3	0	0
T14	50329	49924	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2	0	0
T33	544	0	0	0
T54	2530	0	0	0
T55	36567	0	0	0
T59	499	0	0	0
T60	501	0	0	0
T67	977	0	0	0
T70	26434	1	0	0
T95	0	1	0	0
T96	526	0	0	0
T97	546	0	0	0
T98	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1052	0	0
T5	34049	41	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	10	0	0
T12	728	8	0	0
T13	404	0	0	0
T14	50329	20	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	9	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	9	0	0
T41	0	21	0	0
T42	0	5	0	0
T43	0	10	0	0
T45	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	149	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6009778	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20624	0	0
T12	728	248	0	0
T13	404	3	0	0
T14	50329	147	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6012190	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20660	0	0
T12	728	249	0	0
T13	404	4	0	0
T14	50329	148	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	182	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	151	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	149	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	149	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	903	0	0
T5	34049	35	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	8	0	0
T12	728	7	0	0
T13	404	0	0	0
T14	50329	18	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	8	0	0
T24	503	0	0	0
T32	0	12	0	0
T40	0	8	0	0
T41	0	19	0	0
T42	0	4	0	0
T43	0	8	0	0
T45	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	7242	0	0
T1	15813	16	0	0
T2	20694	15	0	0
T3	20692	23	0	0
T4	422	2	0	0
T5	34049	72	0	0
T6	0	4	0	0
T12	728	3	0	0
T13	404	0	0	0
T14	50329	3	0	0
T15	402	0	0	0
T16	435	4	0	0
T24	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	148	0	0
T5	34049	6	0	0
T6	874	0	0	0
T7	17686	0	0	0
T10	0	2	0	0
T12	728	1	0	0
T13	404	0	0	0
T14	50329	2	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T21
0	1	Covered	T52,T67,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T21
0	1	Unreachable
1	0	Covered	T6,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T20,T21
DetectSt	168	Covered	T6,T20,T21
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T20,T21
DebounceSt->IdleSt	163	Covered	T32,T52,T67
DetectSt->IdleSt	186	Covered	T52,T67,T79
DetectSt->StableSt	191	Covered	T6,T20,T21
IdleSt->DebounceSt	148	Covered	T6,T20,T21
StableSt->IdleSt	206	Covered	T6,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T20,T21
0	1	Covered	T6,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T20,T21
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T52,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T52,T67,T79
DetectSt	-	-	-	-	0	1	-	Covered	T6,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	190	0	0
CntIncr_A	6837408	166383	0	0
CntNoWrap_A	6837408	6133054	0	0
DetectStDropOut_A	6837408	18	0	0
DetectedOut_A	6837408	30193	0	0
DetectedPulseOut_A	6837408	50	0	0
DisabledIdleSt_A	6837408	5447631	0	0
DisabledNoDetection_A	6837408	5450103	0	0
EnterDebounceSt_A	6837408	123	0	0
EnterDetectSt_A	6837408	68	0	0
EnterStableSt_A	6837408	50	0	0
PulseIsPulse_A	6837408	50	0	0
StayInStableSt	6837408	30143	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	7242	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_sticky_sva.StableStDropOut_A	6837408	392993	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	190	0	0
T6	874	2	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T25	13358	0	0	0
T32	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	5	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T67	0	5	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	166383	0	0
T6	874	72	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	35	0	0
T21	0	94	0	0
T25	13358	0	0	0
T32	0	168	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	168	0	0
T53	0	46	0	0
T54	0	34	0	0
T55	0	86	0	0
T67	0	56	0	0
T68	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133054	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	18	0	0
T44	17801	0	0	0
T52	1191	2	0	0
T53	1433	0	0	0
T57	2716	0	0	0
T58	489	0	0	0
T66	6725	0	0	0
T67	0	1	0	0
T79	0	1	0	0
T99	13897	0	0	0
T102	9897	0	0	0
T108	0	2	0	0
T109	0	5	0	0
T110	0	2	0	0
T111	0	3	0	0
T112	0	2	0	0
T113	424	0	0	0
T114	633	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	30193	0	0
T6	874	242	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	85	0	0
T21	0	159	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	232	0	0
T54	0	79	0	0
T55	0	490	0	0
T68	0	230	0	0
T104	0	22	0	0
T105	0	76	0	0
T106	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5447631	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5450103	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	123	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T32	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	4	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	68	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	30143	0	0
T6	874	241	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	84	0	0
T21	0	158	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	231	0	0
T54	0	78	0	0
T55	0	489	0	0
T68	0	229	0	0
T104	0	20	0	0
T105	0	75	0	0
T106	0	157	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	7242	0	0
T1	15813	16	0	0
T2	20694	15	0	0
T3	20692	23	0	0
T4	422	2	0	0
T5	34049	72	0	0
T6	0	4	0	0
T12	728	3	0	0
T13	404	0	0	0
T14	50329	3	0	0
T15	402	0	0	0
T16	435	4	0	0
T24	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	392993	0	0
T6	874	109	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	132	0	0
T21	0	108	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T53	0	279	0	0
T54	0	197	0	0
T55	0	88	0	0
T68	0	359	0	0
T104	0	62	0	0
T105	0	234	0	0
T106	0	130290	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T16,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T16,T5
1	1	Covered	T4,T16,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T4,T16,T5
1	1	Covered	T6,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T21
0	1	Covered	T6,T68,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T20,T21
0	1	Unreachable
1	0	Covered	T6,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T20,T21
DetectSt	168	Covered	T6,T20,T21
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T20,T21
DebounceSt->IdleSt	163	Covered	T32,T103,T75
DetectSt->IdleSt	186	Covered	T6,T68,T78
DetectSt->StableSt	191	Covered	T6,T20,T21
IdleSt->DebounceSt	148	Covered	T6,T20,T21
StableSt->IdleSt	206	Covered	T6,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T20,T21
0	1	Covered	T6,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T20,T21
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T16,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T103,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T6,T68,T78
DetectSt	-	-	-	-	0	1	-	Covered	T6,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T6,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	182	0	0
CntIncr_A	6837408	25073	0	0
CntNoWrap_A	6837408	6133062	0	0
DetectStDropOut_A	6837408	16	0	0
DetectedOut_A	6837408	9958	0	0
DetectedPulseOut_A	6837408	55	0	0
DisabledIdleSt_A	6837408	5447631	0	0
DisabledNoDetection_A	6837408	5450103	0	0
EnterDebounceSt_A	6837408	112	0	0
EnterDetectSt_A	6837408	71	0	0
EnterStableSt_A	6837408	55	0	0
PulseIsPulse_A	6837408	55	0	0
StayInStableSt	6837408	9903	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_sticky_sva.StableStDropOut_A	6837408	315782	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	182	0	0
T6	874	8	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T25	13358	0	0	0
T32	0	3	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T67	0	2	0	0
T68	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	25073	0	0
T6	874	248	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	93	0	0
T21	0	98	0	0
T25	13358	0	0	0
T32	0	171	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	69	0	0
T53	0	53	0	0
T54	0	51	0	0
T55	0	64	0	0
T67	0	79	0	0
T68	0	210	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133062	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	16	0	0
T6	874	3	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T68	0	4	0	0
T78	0	1	0	0
T115	0	2	0	0
T116	0	4	0	0
T117	0	1	0	0
T118	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	9958	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	113	0	0
T21	0	220	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	241	0	0
T53	0	401	0	0
T54	0	213	0	0
T55	0	409	0	0
T67	0	353	0	0
T68	0	1	0	0
T104	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	55	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5447631	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5450103	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	112	0	0
T6	874	4	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T32	0	3	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	71	0	0
T6	874	4	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	5	0	0
T104	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	55	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	55	0	0
T6	874	1	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T104	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	9903	0	0
T20	22644	112	0	0
T21	2411	219	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	240	0	0
T53	0	400	0	0
T54	0	212	0	0
T55	0	408	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	352	0	0
T79	0	95	0	0
T80	16770	0	0	0
T104	0	21	0	0
T107	407	0	0	0
T119	0	228	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	315782	0	0
T6	874	42	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	50	0	0
T21	0	44	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	144	0	0
T53	0	97	0	0
T54	0	54	0	0
T55	0	208	0	0
T67	0	96	0	0
T68	0	78	0	0
T104	0	117	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T20,T21,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T52
0	1	Covered	T32,T75,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T52
0	1	Unreachable
1	0	Covered	T20,T21,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T20,T21
DetectSt	168	Covered	T20,T21,T32
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T20,T21,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T32
DebounceSt->IdleSt	163	Covered	T6,T32,T79
DetectSt->IdleSt	186	Covered	T32,T75,T76
DetectSt->StableSt	191	Covered	T20,T21,T52
IdleSt->DebounceSt	148	Covered	T6,T20,T21
StableSt->IdleSt	206	Covered	T20,T21,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T20,T21
0	1	Covered	T6,T20,T21
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T32
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T32,T79
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T32,T75,T76
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T52
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	179	0	0
CntIncr_A	6837408	276183	0	0
CntNoWrap_A	6837408	6133065	0	0
DetectStDropOut_A	6837408	10	0	0
DetectedOut_A	6837408	197717	0	0
DetectedPulseOut_A	6837408	56	0	0
DisabledIdleSt_A	6837408	5447631	0	0
DisabledNoDetection_A	6837408	5450103	0	0
EnterDebounceSt_A	6837408	114	0	0
EnterDetectSt_A	6837408	66	0	0
EnterStableSt_A	6837408	56	0	0
PulseIsPulse_A	6837408	56	0	0
StayInStableSt	6837408	197661	0	0
gen_high_event_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_sticky_sva.StableStDropOut_A	6837408	207308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	179	0	0
T6	874	4	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T25	13358	0	0	0
T32	0	5	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	276183	0	0
T6	874	256	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	91	0	0
T21	0	65	0	0
T25	13358	0	0	0
T32	0	291	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	85	0	0
T53	0	43	0	0
T54	0	36	0	0
T55	0	28	0	0
T67	0	65	0	0
T68	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133065	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	10	0	0
T32	39299	2	0	0
T44	17801	0	0	0
T52	1191	0	0	0
T53	1433	0	0	0
T56	489	0	0	0
T57	2716	0	0	0
T66	6725	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T78	0	1	0	0
T112	0	2	0	0
T113	424	0	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	408	0	0	0
T123	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	197717	0	0
T20	22644	93	0	0
T21	2411	168	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	336	0	0
T53	0	349	0	0
T54	0	138	0	0
T55	0	165	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	236	0	0
T68	0	512	0	0
T80	16770	0	0	0
T103	0	4	0	0
T104	0	14	0	0
T107	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	56	0	0
T20	22644	1	0	0
T21	2411	1	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T80	16770	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T107	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5447631	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5450103	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	114	0	0
T6	874	4	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	13358	0	0	0
T32	0	3	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	66	0	0
T20	22644	1	0	0
T21	2411	1	0	0
T31	627	0	0	0
T32	0	2	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T80	16770	0	0	0
T103	0	1	0	0
T107	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	56	0	0
T20	22644	1	0	0
T21	2411	1	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T80	16770	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T107	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	56	0	0
T20	22644	1	0	0
T21	2411	1	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T80	16770	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T107	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	197661	0	0
T20	22644	92	0	0
T21	2411	167	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	335	0	0
T53	0	348	0	0
T54	0	137	0	0
T55	0	164	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	235	0	0
T68	0	511	0	0
T80	16770	0	0	0
T103	0	3	0	0
T104	0	12	0	0
T107	407	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	207308	0	0
T20	22644	87	0	0
T21	2411	137	0	0
T31	627	0	0	0
T41	668	0	0	0
T42	821	0	0	0
T51	1427	0	0	0
T52	0	36	0	0
T53	0	168	0	0
T54	0	148	0	0
T55	0	489	0	0
T62	522	0	0	0
T63	504	0	0	0
T67	0	244	0	0
T68	0	52	0	0
T80	16770	0	0	0
T103	0	8465	0	0
T104	0	129	0	0
T107	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T9,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T9,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T9,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T30
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T9,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T30
0	1	Covered	T30,T35,T32
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T30
1	-	Covered	T30,T35,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T30
DetectSt	168	Covered	T5,T9,T30
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T9,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T30
DebounceSt->IdleSt	163	Covered	T120,T124,T125
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T5,T9,T30
IdleSt->DebounceSt	148	Covered	T5,T9,T30
StableSt->IdleSt	206	Covered	T5,T30,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T9,T30
0	1	Covered	T5,T9,T30
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T30
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T120,T124,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T35,T32
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	84	0	0
CntIncr_A	6837408	43042	0	0
CntNoWrap_A	6837408	6133160	0	0
DetectStDropOut_A	6837408	0	0	0
DetectedOut_A	6837408	2436	0	0
DetectedPulseOut_A	6837408	40	0	0
DisabledIdleSt_A	6837408	5936196	0	0
DisabledNoDetection_A	6837408	5938610	0	0
EnterDebounceSt_A	6837408	44	0	0
EnterDetectSt_A	6837408	40	0	0
EnterStableSt_A	6837408	40	0	0
PulseIsPulse_A	6837408	40	0	0
StayInStableSt	6837408	2377	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	84	0	0
T5	34049	4	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	4	0	0
T32	0	6	0	0
T35	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T71	0	4	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	43042	0	0
T5	34049	86	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	34	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	134	0	0
T32	0	177	0	0
T35	0	63	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	35	0	0
T71	0	62	0	0
T126	0	15	0	0
T127	0	59	0	0
T128	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133160	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21230	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2436	0	0
T5	34049	94	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	41	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	56	0	0
T32	0	124	0	0
T35	0	114	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	61	0	0
T71	0	79	0	0
T126	0	38	0	0
T127	0	36	0	0
T128	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	40	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	3	0	0
T35	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5936196	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20743	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5938610	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20780	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	44	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	3	0	0
T35	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	40	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	3	0	0
T35	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	40	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	3	0	0
T35	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	40	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	3	0	0
T35	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2377	0	0
T5	34049	90	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T9	0	39	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	54	0	0
T32	0	120	0	0
T35	0	113	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	60	0	0
T71	0	76	0	0
T126	0	36	0	0
T127	0	35	0	0
T128	0	9	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	20	0	0
T29	25007	0	0	0
T30	1066	2	0	0
T32	0	2	0	0
T34	985	0	0	0
T35	771	1	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T55	0	1	0	0
T64	600	0	0	0
T71	0	1	0	0
T76	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	402	0	0	0
T132	785	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T30,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T30,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T34,T35
1	0	Covered	T1,T4,T2
1	1	Covered	T30,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T34,T35
0	1	Covered	T71,T133
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T34,T35
0	1	Covered	T30,T34,T35
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T34,T35
1	-	Covered	T30,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T34,T35
DetectSt	168	Covered	T30,T34,T35
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T30,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T34,T35
DebounceSt->IdleSt	163	Covered	T134,T135,T136
DetectSt->IdleSt	186	Covered	T71,T133
DetectSt->StableSt	191	Covered	T30,T34,T35
IdleSt->DebounceSt	148	Covered	T30,T34,T35
StableSt->IdleSt	206	Covered	T30,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T34,T35
0	1	Covered	T30,T34,T35
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T34,T35
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T135,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T71,T133
DetectSt	-	-	-	-	0	1	-	Covered	T30,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T30,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	134	0	0
CntIncr_A	6837408	44689	0	0
CntNoWrap_A	6837408	6133110	0	0
DetectStDropOut_A	6837408	2	0	0
DetectedOut_A	6837408	11173	0	0
DetectedPulseOut_A	6837408	62	0	0
DisabledIdleSt_A	6837408	5936288	0	0
DisabledNoDetection_A	6837408	5938707	0	0
EnterDebounceSt_A	6837408	70	0	0
EnterDetectSt_A	6837408	64	0	0
EnterStableSt_A	6837408	62	0	0
PulseIsPulse_A	6837408	62	0	0
StayInStableSt	6837408	11080	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	2812	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	134	0	0
T20	0	2	0	0
T29	25007	0	0	0
T30	1066	6	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	985	4	0	0
T35	771	4	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	8	0	0
T77	0	2	0	0
T126	0	2	0	0
T127	0	4	0	0
T131	402	0	0	0
T132	785	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	44689	0	0
T20	0	80	0	0
T29	25007	0	0	0
T30	1066	201	0	0
T32	0	82	0	0
T33	0	39	0	0
T34	985	160	0	0
T35	771	126	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	210	0	0
T77	0	46	0	0
T126	0	15	0	0
T127	0	118	0	0
T131	402	0	0	0
T132	785	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133110	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2	0	0
T71	354397	1	0	0
T133	0	1	0	0
T137	524	0	0	0
T138	532	0	0	0
T139	2777	0	0	0
T140	715	0	0	0
T141	526	0	0	0
T142	422	0	0	0
T143	451	0	0	0
T144	423	0	0	0
T145	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	11173	0	0
T20	0	158	0	0
T29	25007	0	0	0
T30	1066	130	0	0
T32	0	126	0	0
T33	0	96	0	0
T34	985	88	0	0
T35	771	56	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	319	0	0
T77	0	89	0	0
T126	0	4	0	0
T127	0	87	0	0
T131	402	0	0	0
T132	785	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	62	0	0
T20	0	1	0	0
T29	25007	0	0	0
T30	1066	3	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	985	2	0	0
T35	771	2	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	3	0	0
T77	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T131	402	0	0	0
T132	785	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5936288	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5938707	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	70	0	0
T20	0	1	0	0
T29	25007	0	0	0
T30	1066	3	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	985	2	0	0
T35	771	2	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	4	0	0
T77	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T131	402	0	0	0
T132	785	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	64	0	0
T20	0	1	0	0
T29	25007	0	0	0
T30	1066	3	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	985	2	0	0
T35	771	2	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	4	0	0
T77	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T131	402	0	0	0
T132	785	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	62	0	0
T20	0	1	0	0
T29	25007	0	0	0
T30	1066	3	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	985	2	0	0
T35	771	2	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	3	0	0
T77	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T131	402	0	0	0
T132	785	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	62	0	0
T20	0	1	0	0
T29	25007	0	0	0
T30	1066	3	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	985	2	0	0
T35	771	2	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	3	0	0
T77	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T131	402	0	0	0
T132	785	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	11080	0	0
T20	0	156	0	0
T29	25007	0	0	0
T30	1066	126	0	0
T32	0	123	0	0
T33	0	94	0	0
T34	985	85	0	0
T35	771	53	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	315	0	0
T77	0	87	0	0
T126	0	3	0	0
T127	0	84	0	0
T131	402	0	0	0
T132	785	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2812	0	0
T2	20694	0	0	0
T3	20692	0	0	0
T4	422	2	0	0
T5	34049	45	0	0
T8	0	5	0	0
T9	0	1	0	0
T10	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	4	0	0
T24	503	5	0	0
T46	0	6	0	0
T47	0	3	0	0
T48	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	30	0	0
T29	25007	0	0	0
T30	1066	2	0	0
T32	0	1	0	0
T34	985	1	0	0
T35	771	1	0	0
T37	5466	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T64	600	0	0	0
T71	0	2	0	0
T104	0	2	0	0
T126	0	1	0	0
T127	0	1	0	0
T131	402	0	0	0
T132	785	0	0	0
T146	0	1	0	0
T147	0	1	0	0