Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T8,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T35
0	1	Covered	T34,T20,T71
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T34,T35
1	-	Covered	T34,T20,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T35
DetectSt	168	Covered	T8,T34,T35
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T34,T35
DebounceSt->IdleSt	163	Covered	T69,T148
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T34,T35
IdleSt->DebounceSt	148	Covered	T8,T34,T35
StableSt->IdleSt	206	Covered	T8,T34,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T35
0	1	Covered	T8,T34,T35
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T34,T35
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T20,T71
StableSt	-	-	-	-	-	-	0	Covered	T8,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	74	0	0
CntIncr_A	6837408	2031	0	0
CntNoWrap_A	6837408	6133170	0	0
DetectStDropOut_A	6837408	0	0	0
DetectedOut_A	6837408	2816	0	0
DetectedPulseOut_A	6837408	36	0	0
DisabledIdleSt_A	6837408	5936545	0	0
DisabledNoDetection_A	6837408	5938962	0	0
EnterDebounceSt_A	6837408	38	0	0
EnterDetectSt_A	6837408	36	0	0
EnterStableSt_A	6837408	36	0	0
PulseIsPulse_A	6837408	36	0	0
StayInStableSt	6837408	2756	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	74	0	0
T8	2078	2	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	2	0	0
T34	0	4	0	0
T35	0	2	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	4	0	0
T75	0	2	0	0
T101	8401	0	0	0
T104	0	4	0	0
T126	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	404	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2031	0	0
T8	2078	31	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	80	0	0
T34	0	160	0	0
T35	0	63	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	62	0	0
T75	0	77	0	0
T101	8401	0	0	0
T104	0	144	0	0
T126	0	15	0	0
T149	0	78	0	0
T150	0	20	0	0
T151	404	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133170	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2816	0	0
T8	2078	267	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	152	0	0
T34	0	170	0	0
T35	0	115	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	49	0	0
T75	0	44	0	0
T101	8401	0	0	0
T104	0	83	0	0
T126	0	37	0	0
T149	0	38	0	0
T150	0	48	0	0
T151	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	36	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T126	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5936545	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21126	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5938962	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21164	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	38	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T126	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	404	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	36	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T126	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	404	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	36	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T126	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	36	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T75	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T126	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2756	0	0
T8	2078	265	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	151	0	0
T34	0	167	0	0
T35	0	113	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	46	0	0
T75	0	42	0	0
T101	8401	0	0	0
T104	0	80	0	0
T126	0	35	0	0
T149	0	36	0	0
T150	0	46	0	0
T151	404	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	11	0	0
T20	0	1	0	0
T34	985	1	0	0
T35	771	0	0	0
T38	11428	0	0	0
T39	21720	0	0	0
T40	706	0	0	0
T64	600	0	0	0
T65	492	0	0	0
T71	0	1	0	0
T104	0	1	0	0
T131	402	0	0	0
T132	785	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T8,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T8,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T8,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T34
0	1	Covered	T5,T136
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T34
0	1	Covered	T8,T34,T20
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T8,T34
1	-	Covered	T8,T34,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T8,T34
DetectSt	168	Covered	T5,T8,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T8,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T8,T34
DebounceSt->IdleSt	163	Covered	T34,T157,T136
DetectSt->IdleSt	186	Covered	T5,T136
DetectSt->StableSt	191	Covered	T5,T8,T34
IdleSt->DebounceSt	148	Covered	T5,T8,T34
StableSt->IdleSt	206	Covered	T5,T8,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T8,T34
0	1	Covered	T5,T8,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T34
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T8,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T8,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T157,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T8,T34
DetectSt	-	-	-	-	1	-	-	Covered	T5,T136
DetectSt	-	-	-	-	0	1	-	Covered	T5,T8,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T34,T20
StableSt	-	-	-	-	-	-	0	Covered	T5,T8,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	113	0	0
CntIncr_A	6837408	9868	0	0
CntNoWrap_A	6837408	6133131	0	0
DetectStDropOut_A	6837408	2	0	0
DetectedOut_A	6837408	5364	0	0
DetectedPulseOut_A	6837408	52	0	0
DisabledIdleSt_A	6837408	6101193	0	0
DisabledNoDetection_A	6837408	6103614	0	0
EnterDebounceSt_A	6837408	59	0	0
EnterDetectSt_A	6837408	54	0	0
EnterStableSt_A	6837408	52	0	0
PulseIsPulse_A	6837408	52	0	0
StayInStableSt	6837408	5283	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	3218	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	113	0	0
T5	34049	4	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T20	0	6	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	2	0	0
T34	0	3	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T64	0	2	0	0
T71	0	6	0	0
T128	0	4	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	9868	0	0
T5	34049	128	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	31	0	0
T20	0	209	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	62	0	0
T34	0	160	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	35	0	0
T64	0	25	0	0
T71	0	136	0	0
T128	0	124	0	0
T146	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133131	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21230	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T24	503	0	0	0
T25	13358	0	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T136	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5364	0	0
T5	34049	111	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	7	0	0
T20	0	179	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	39	0	0
T34	0	42	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	172	0	0
T64	0	39	0	0
T71	0	342	0	0
T128	0	154	0	0
T146	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	52	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	0	3	0	0
T128	0	2	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6101193	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20678	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6103614	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20716	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	59	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	0	3	0	0
T128	0	2	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	54	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	0	3	0	0
T128	0	2	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	52	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	0	3	0	0
T128	0	2	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	52	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T71	0	3	0	0
T128	0	2	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5283	0	0
T5	34049	109	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	6	0	0
T20	0	175	0	0
T24	503	0	0	0
T25	13358	0	0	0
T31	0	37	0	0
T34	0	41	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	170	0	0
T64	0	37	0	0
T71	0	338	0	0
T128	0	151	0	0
T146	0	107	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3218	0	0
T5	34049	44	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	7	0	0
T10	0	23	0	0
T16	435	3	0	0
T24	503	5	0	0
T25	13358	0	0	0
T30	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	4	0	0
T47	0	2	0	0
T48	0	8	0	0
T49	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	22	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	2	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T128	0	1	0	0
T151	404	0	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T30,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T30,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T30,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T30,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T30,T34
0	1	Covered	T128,T154,T162
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T30,T34
0	1	Covered	T5,T30,T34
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T30,T34
1	-	Covered	T5,T30,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T30,T34
DetectSt	168	Covered	T5,T30,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T30,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T30,T34
DebounceSt->IdleSt	163	Covered	T124,T133,T162
DetectSt->IdleSt	186	Covered	T128,T154,T162
DetectSt->StableSt	191	Covered	T5,T30,T34
IdleSt->DebounceSt	148	Covered	T5,T30,T34
StableSt->IdleSt	206	Covered	T5,T30,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T30,T34
0	1	Covered	T5,T30,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T34
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T30,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T30,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T124,T133,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T30,T34
DetectSt	-	-	-	-	1	-	-	Covered	T128,T154,T162
DetectSt	-	-	-	-	0	1	-	Covered	T5,T30,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T30,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T30,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	132	0	0
CntIncr_A	6837408	91558	0	0
CntNoWrap_A	6837408	6133112	0	0
DetectStDropOut_A	6837408	3	0	0
DetectedOut_A	6837408	7621	0	0
DetectedPulseOut_A	6837408	60	0	0
DisabledIdleSt_A	6837408	5920443	0	0
DisabledNoDetection_A	6837408	5922860	0	0
EnterDebounceSt_A	6837408	69	0	0
EnterDetectSt_A	6837408	63	0	0
EnterStableSt_A	6837408	60	0	0
PulseIsPulse_A	6837408	60	0	0
StayInStableSt	6837408	7531	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	132	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	4	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	4	0	0
T65	0	2	0	0
T71	0	4	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	91558	0	0
T5	34049	57	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	116	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	134	0	0
T32	0	118	0	0
T33	0	39	0	0
T34	0	160	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	70	0	0
T65	0	16	0	0
T71	0	62	0	0
T77	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133112	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21232	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3	0	0
T79	670	0	0	0
T88	6090	0	0	0
T119	1555	0	0	0
T128	2819	1	0	0
T150	513	0	0	0
T154	0	1	0	0
T158	12926	0	0	0
T162	0	1	0	0
T163	22142	0	0	0
T164	584	0	0	0
T165	496	0	0	0
T166	4241	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	7621	0	0
T5	34049	102	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	49	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	157	0	0
T32	0	382	0	0
T33	0	95	0	0
T34	0	210	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	120	0	0
T65	0	66	0	0
T71	0	13	0	0
T77	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	60	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5920443	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20743	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5922860	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20780	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	69	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	63	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	60	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	60	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	2	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	7531	0	0
T5	34049	101	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	46	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	154	0	0
T32	0	379	0	0
T33	0	93	0	0
T34	0	207	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	117	0	0
T65	0	64	0	0
T71	0	11	0	0
T77	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	29	0	0
T5	34049	1	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T25	13358	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T55	0	1	0	0
T71	0	2	0	0
T104	0	1	0	0
T146	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T34,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T34,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T34,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T8,T34,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T20
0	1	Covered	T8,T34,T20
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T34,T20
1	-	Covered	T8,T34,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T20
DetectSt	168	Covered	T8,T34,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T34,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T34,T20
DebounceSt->IdleSt	163	Covered	T55,T69,T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T34,T20
IdleSt->DebounceSt	148	Covered	T8,T34,T20
StableSt->IdleSt	206	Covered	T8,T34,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T20
0	1	Covered	T8,T34,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T34,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T34,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T34,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T34,T20
StableSt	-	-	-	-	-	-	0	Covered	T8,T34,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	103	0	0
CntIncr_A	6837408	43662	0	0
CntNoWrap_A	6837408	6133141	0	0
DetectStDropOut_A	6837408	0	0	0
DetectedOut_A	6837408	9170	0	0
DetectedPulseOut_A	6837408	50	0	0
DisabledIdleSt_A	6837408	5933017	0	0
DisabledNoDetection_A	6837408	5935430	0	0
EnterDebounceSt_A	6837408	53	0	0
EnterDetectSt_A	6837408	50	0	0
EnterStableSt_A	6837408	50	0	0
PulseIsPulse_A	6837408	50	0	0
StayInStableSt	6837408	9097	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	7069	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	103	0	0
T8	2078	2	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	6	0	0
T32	0	2	0	0
T34	0	2	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T55	0	1	0	0
T71	0	6	0	0
T101	8401	0	0	0
T104	0	2	0	0
T127	0	2	0	0
T146	0	2	0	0
T151	404	0	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	43662	0	0
T8	2078	31	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	218	0	0
T32	0	41	0	0
T34	0	80	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T55	0	35	0	0
T71	0	136	0	0
T101	8401	0	0	0
T104	0	72	0	0
T127	0	59	0	0
T146	0	44	0	0
T151	404	0	0	0
T169	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133141	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	9170	0	0
T8	2078	16	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	230	0	0
T32	0	70	0	0
T34	0	124	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	225	0	0
T101	8401	0	0	0
T104	0	91	0	0
T127	0	45	0	0
T128	0	105	0	0
T146	0	39	0	0
T151	404	0	0	0
T169	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	3	0	0
T101	8401	0	0	0
T104	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5933017	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5935430	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	53	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T55	0	1	0	0
T71	0	3	0	0
T101	8401	0	0	0
T104	0	1	0	0
T127	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	3	0	0
T101	8401	0	0	0
T104	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	3	0	0
T101	8401	0	0	0
T104	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	50	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	3	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	3	0	0
T101	8401	0	0	0
T104	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	9097	0	0
T8	2078	15	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	226	0	0
T32	0	69	0	0
T34	0	123	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	220	0	0
T101	8401	0	0	0
T104	0	89	0	0
T127	0	43	0	0
T128	0	104	0	0
T146	0	38	0	0
T151	404	0	0	0
T169	0	45	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	7069	0	0
T1	15813	12	0	0
T2	20694	14	0	0
T3	20692	27	0	0
T4	422	2	0	0
T5	34049	62	0	0
T6	0	4	0	0
T7	0	23	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	3	0	0
T24	0	5	0	0
T25	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	26	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	1	0	0
T101	8401	0	0	0
T128	0	1	0	0
T129	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T161	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T77,T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T8,T20,T33
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T8,T9
1	-	Covered	T8,T20,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T8,T9
DetectSt	168	Covered	T5,T8,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T8,T9
DebounceSt->IdleSt	163	Covered	T71,T128,T157
DetectSt->IdleSt	186	Covered	T77,T71
DetectSt->StableSt	191	Covered	T5,T8,T9
IdleSt->DebounceSt	148	Covered	T5,T8,T9
StableSt->IdleSt	206	Covered	T5,T8,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T128,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T77,T71
DetectSt	-	-	-	-	0	1	-	Covered	T5,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T20,T33
StableSt	-	-	-	-	-	-	0	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	147	0	0
CntIncr_A	6837408	85447	0	0
CntNoWrap_A	6837408	6133097	0	0
DetectStDropOut_A	6837408	2	0	0
DetectedOut_A	6837408	62199	0	0
DetectedPulseOut_A	6837408	68	0	0
DisabledIdleSt_A	6837408	5934437	0	0
DisabledNoDetection_A	6837408	5936850	0	0
EnterDebounceSt_A	6837408	78	0	0
EnterDetectSt_A	6837408	70	0	0
EnterStableSt_A	6837408	68	0	0
PulseIsPulse_A	6837408	68	0	0
StayInStableSt	6837408	62098	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	147	0	0
T5	34049	4	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	4	0	0
T9	0	2	0	0
T20	0	6	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	2	0	0
T71	0	7	0	0
T77	0	2	0	0
T127	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	85447	0	0
T5	34049	86	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	62	0	0
T9	0	34	0	0
T20	0	209	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	59	0	0
T33	0	39	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	16	0	0
T71	0	263	0	0
T77	0	46	0	0
T127	0	118	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133097	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21230	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2	0	0
T71	0	1	0	0
T77	544	1	0	0
T83	56254	0	0	0
T103	8912	0	0	0
T127	723	0	0	0
T171	496	0	0	0
T172	422	0	0	0
T173	7577	0	0	0
T174	503	0	0	0
T175	489	0	0	0
T176	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	62199	0	0
T5	34049	182	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	153	0	0
T9	0	41	0	0
T20	0	353	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	249	0	0
T33	0	17	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	66	0	0
T71	0	253	0	0
T127	0	99	0	0
T146	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	68	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T9	0	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	1	0	0
T71	0	2	0	0
T127	0	2	0	0
T146	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5934437	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20743	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5936850	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20780	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	78	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T9	0	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	1	0	0
T71	0	4	0	0
T77	0	1	0	0
T127	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	70	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T9	0	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	1	0	0
T71	0	3	0	0
T77	0	1	0	0
T127	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	68	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T9	0	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	1	0	0
T71	0	2	0	0
T127	0	2	0	0
T146	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	68	0	0
T5	34049	2	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	2	0	0
T9	0	1	0	0
T20	0	3	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	1	0	0
T71	0	2	0	0
T127	0	2	0	0
T146	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	62098	0	0
T5	34049	178	0	0
T6	874	0	0	0
T7	17686	0	0	0
T8	2078	150	0	0
T9	0	39	0	0
T20	0	348	0	0
T24	503	0	0	0
T25	13358	0	0	0
T32	0	247	0	0
T33	0	16	0	0
T36	738	0	0	0
T45	402	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T65	0	64	0	0
T71	0	250	0	0
T127	0	96	0	0
T146	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	34	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T20	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	1	0	0
T76	0	1	0	0
T101	8401	0	0	0
T104	0	2	0	0
T127	0	1	0	0
T146	0	1	0	0
T151	404	0	0	0
T157	0	1	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T8,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T32,T33
0	1	Covered	T8,T127,T71
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T32,T33
1	-	Covered	T8,T127,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T32,T33
DetectSt	168	Covered	T8,T32,T33
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T32,T33
DebounceSt->IdleSt	163	Covered	T93,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T32,T33
IdleSt->DebounceSt	148	Covered	T8,T32,T33
StableSt->IdleSt	206	Covered	T8,T32,T127

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T32,T33
0	1	Covered	T8,T32,T33
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T32,T33
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T93
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T32,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T127,T71
StableSt	-	-	-	-	-	-	0	Covered	T8,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	80	0	0
CntIncr_A	6837408	42822	0	0
CntNoWrap_A	6837408	6133164	0	0
DetectStDropOut_A	6837408	0	0	0
DetectedOut_A	6837408	3943	0	0
DetectedPulseOut_A	6837408	39	0	0
DisabledIdleSt_A	6837408	5920741	0	0
DisabledNoDetection_A	6837408	5923157	0	0
EnterDebounceSt_A	6837408	41	0	0
EnterDetectSt_A	6837408	39	0	0
EnterStableSt_A	6837408	39	0	0
PulseIsPulse_A	6837408	39	0	0
StayInStableSt	6837408	3887	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6837408	6583	0	0
gen_low_level_sva.LowLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	80	0	0
T8	2078	2	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	4	0	0
T101	8401	0	0	0
T127	0	2	0	0
T147	0	2	0	0
T151	404	0	0	0
T157	0	4	0	0
T159	0	2	0	0
T167	0	4	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	42822	0	0
T8	2078	31	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	41	0	0
T33	0	39	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	59	0	0
T101	8401	0	0	0
T127	0	59	0	0
T147	0	13	0	0
T151	404	0	0	0
T157	0	118	0	0
T159	0	69	0	0
T167	0	168	0	0
T177	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6133164	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3943	0	0
T8	2078	90	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	93	0	0
T33	0	39	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	83	0	0
T101	8401	0	0	0
T127	0	36	0	0
T147	0	191	0	0
T151	404	0	0	0
T157	0	102	0	0
T159	0	218	0	0
T167	0	79	0	0
T177	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	39	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T127	0	1	0	0
T147	0	1	0	0
T151	404	0	0	0
T157	0	2	0	0
T159	0	1	0	0
T167	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5920741	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	20570	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5923157	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	20607	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	41	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T127	0	1	0	0
T147	0	1	0	0
T151	404	0	0	0
T157	0	2	0	0
T159	0	1	0	0
T167	0	2	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	39	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T127	0	1	0	0
T147	0	1	0	0
T151	404	0	0	0
T157	0	2	0	0
T159	0	1	0	0
T167	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	39	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T127	0	1	0	0
T147	0	1	0	0
T151	404	0	0	0
T157	0	2	0	0
T159	0	1	0	0
T167	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	39	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	2	0	0
T101	8401	0	0	0
T127	0	1	0	0
T147	0	1	0	0
T151	404	0	0	0
T157	0	2	0	0
T159	0	1	0	0
T167	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3887	0	0
T8	2078	89	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T32	0	91	0	0
T33	0	37	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	80	0	0
T101	8401	0	0	0
T127	0	35	0	0
T147	0	189	0	0
T151	404	0	0	0
T157	0	99	0	0
T159	0	216	0	0
T167	0	76	0	0
T177	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6583	0	0
T1	15813	8	0	0
T2	20694	10	0	0
T3	20692	27	0	0
T4	422	1	0	0
T5	34049	59	0	0
T7	0	23	0	0
T8	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	1	0	0
T24	0	7	0	0
T25	0	26	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	21	0	0
T8	2078	1	0	0
T9	520	0	0	0
T10	10150	0	0	0
T11	15424	0	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T71	0	1	0	0
T101	8401	0	0	0
T127	0	1	0	0
T151	404	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T167	0	1	0	0
T170	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0