Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T3,T7,T25
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T25
0	1	Covered	T3,T25,T37
1	0	Covered	T3,T25,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T29
0	1	Covered	T7,T11,T29
1	0	Covered	T209

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T29
1	-	Covered	T7,T11,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T7,T11,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T25
DebounceSt->IdleSt	163	Covered	T210,T211,T50
DetectSt->IdleSt	186	Covered	T3,T25,T37
DetectSt->StableSt	191	Covered	T7,T11,T29
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T7,T11,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T210,T211,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T3,T25,T37
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T29
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T25
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T29
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	2972	0	0
CntIncr_A	6837408	97072	0	0
CntNoWrap_A	6837408	6130272	0	0
DetectStDropOut_A	6837408	417	0	0
DetectedOut_A	6837408	60541	0	0
DetectedPulseOut_A	6837408	803	0	0
DisabledIdleSt_A	6837408	5688390	0	0
DisabledNoDetection_A	6837408	5690677	0	0
EnterDebounceSt_A	6837408	1507	0	0
EnterDetectSt_A	6837408	1466	0	0
EnterStableSt_A	6837408	803	0	0
PulseIsPulse_A	6837408	803	0	0
StayInStableSt	6837408	59646	0	0
gen_high_event_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	706	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2972	0	0
T3	20692	24	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	42	0	0
T11	0	54	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	26	0	0
T29	0	12	0	0
T37	0	14	0	0
T38	0	14	0	0
T39	0	16	0	0
T44	0	14	0	0
T45	402	0	0	0
T66	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	97072	0	0
T3	20692	717	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	1344	0	0
T11	0	891	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	2310	0	0
T29	0	360	0	0
T37	0	393	0	0
T38	0	371	0	0
T39	0	640	0	0
T44	0	581	0	0
T45	402	0	0	0
T66	0	697	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6130272	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20253	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	417	0	0
T3	20692	6	0	0
T5	34049	0	0	0
T6	874	0	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	10	0	0
T37	0	7	0	0
T45	402	0	0	0
T66	0	7	0	0
T82	0	22	0	0
T84	0	25	0	0
T85	0	3	0	0
T86	0	5	0	0
T89	0	9	0	0
T212	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	60541	0	0
T7	17686	1779	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	1974	0	0
T25	13358	0	0	0
T29	0	120	0	0
T36	738	0	0	0
T38	0	101	0	0
T39	0	533	0	0
T44	0	507	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	523	0	0
T100	0	2029	0	0
T101	8401	0	0	0
T102	0	2057	0	0
T213	0	1762	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	803	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	27	0	0
T25	13358	0	0	0
T29	0	6	0	0
T36	738	0	0	0
T38	0	7	0	0
T39	0	8	0	0
T44	0	7	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	24	0	0
T100	0	15	0	0
T101	8401	0	0	0
T102	0	28	0	0
T213	0	31	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5688390	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	17052	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5690677	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	17059	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1507	0	0
T3	20692	12	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	21	0	0
T11	0	27	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	13	0	0
T29	0	6	0	0
T37	0	7	0	0
T38	0	7	0	0
T39	0	8	0	0
T44	0	7	0	0
T45	402	0	0	0
T66	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1466	0	0
T3	20692	12	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	21	0	0
T11	0	27	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	13	0	0
T29	0	6	0	0
T37	0	7	0	0
T38	0	7	0	0
T39	0	8	0	0
T44	0	7	0	0
T45	402	0	0	0
T66	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	803	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	27	0	0
T25	13358	0	0	0
T29	0	6	0	0
T36	738	0	0	0
T38	0	7	0	0
T39	0	8	0	0
T44	0	7	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	24	0	0
T100	0	15	0	0
T101	8401	0	0	0
T102	0	28	0	0
T213	0	31	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	803	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	27	0	0
T25	13358	0	0	0
T29	0	6	0	0
T36	738	0	0	0
T38	0	7	0	0
T39	0	8	0	0
T44	0	7	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	24	0	0
T100	0	15	0	0
T101	8401	0	0	0
T102	0	28	0	0
T213	0	31	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	59646	0	0
T7	17686	1757	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	1946	0	0
T25	13358	0	0	0
T29	0	114	0	0
T36	738	0	0	0
T38	0	94	0	0
T39	0	522	0	0
T44	0	500	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	498	0	0
T100	0	2010	0	0
T101	8401	0	0	0
T102	0	2029	0	0
T213	0	1731	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	706	0	0
T7	17686	20	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	26	0	0
T25	13358	0	0	0
T29	0	6	0	0
T36	738	0	0	0
T38	0	7	0	0
T39	0	5	0	0
T44	0	7	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T99	0	23	0	0
T100	0	11	0	0
T101	8401	0	0	0
T102	0	28	0	0
T213	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T81,T83
1	0	Covered	T50,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T7
0	1	Covered	T2,T5,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T7
1	-	Covered	T2,T5,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T5
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T2,T5,T32
DetectSt->IdleSt	186	Covered	T1,T81,T83
DetectSt->StableSt	191	Covered	T2,T5,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T5
StableSt->IdleSt	206	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T5,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	1	-	-	Covered	T1,T81,T83
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	1	Covered	T2,T5,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	902	0	0
CntIncr_A	6837408	42263	0	0
CntNoWrap_A	6837408	6132342	0	0
DetectStDropOut_A	6837408	75	0	0
DetectedOut_A	6837408	12228	0	0
DetectedPulseOut_A	6837408	334	0	0
DisabledIdleSt_A	6837408	5772555	0	0
DisabledNoDetection_A	6837408	5774346	0	0
EnterDebounceSt_A	6837408	491	0	0
EnterDetectSt_A	6837408	413	0	0
EnterStableSt_A	6837408	334	0	0
PulseIsPulse_A	6837408	334	0	0
StayInStableSt	6837408	11874	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	312	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	902	0	0
T1	15813	4	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	12	0	0
T7	0	6	0	0
T10	0	2	0	0
T11	0	10	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T39	0	4	0	0
T80	0	8	0	0
T81	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	42263	0	0
T1	15813	373	0	0
T2	20694	1196	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	354	0	0
T7	0	234	0	0
T10	0	25	0	0
T11	0	260	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	77	0	0
T39	0	114	0	0
T80	0	328	0	0
T81	0	1390	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6132342	0	0
T1	15813	15400	0	0
T2	20694	20265	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21222	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	75	0	0
T1	15813	2	0	0
T2	20694	0	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	0	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T81	0	8	0	0
T83	0	4	0	0
T87	0	3	0	0
T88	0	5	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	6	0	0
T93	0	7	0	0
T94	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	12228	0	0
T2	20694	26	0	0
T3	20692	0	0	0
T5	34049	83	0	0
T6	874	0	0	0
T7	0	189	0	0
T10	0	4	0	0
T11	0	323	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	6	0	0
T24	503	0	0	0
T32	0	108	0	0
T39	0	129	0	0
T80	0	262	0	0
T100	0	155	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	334	0	0
T2	20694	6	0	0
T3	20692	0	0	0
T5	34049	5	0	0
T6	874	0	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T32	0	10	0	0
T39	0	2	0	0
T80	0	4	0	0
T100	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5772555	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	19225	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5774346	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	19255	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	491	0	0
T1	15813	2	0	0
T2	20694	8	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	7	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T80	0	4	0	0
T81	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	413	0	0
T1	15813	2	0	0
T2	20694	6	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	5	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T80	0	4	0	0
T81	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	334	0	0
T2	20694	6	0	0
T3	20692	0	0	0
T5	34049	5	0	0
T6	874	0	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T32	0	10	0	0
T39	0	2	0	0
T80	0	4	0	0
T100	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	334	0	0
T2	20694	6	0	0
T3	20692	0	0	0
T5	34049	5	0	0
T6	874	0	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T32	0	10	0	0
T39	0	2	0	0
T80	0	4	0	0
T100	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	11874	0	0
T2	20694	20	0	0
T3	20692	0	0	0
T5	34049	78	0	0
T6	874	0	0	0
T7	0	186	0	0
T10	0	3	0	0
T11	0	318	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	5	0	0
T24	503	0	0	0
T32	0	98	0	0
T39	0	125	0	0
T80	0	258	0	0
T100	0	152	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	312	0	0
T2	20694	6	0	0
T3	20692	0	0	0
T5	34049	5	0	0
T6	874	0	0	0
T7	0	3	0	0
T10	0	1	0	0
T11	0	5	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	1	0	0
T24	503	0	0	0
T32	0	10	0	0
T80	0	4	0	0
T83	0	4	0	0
T100	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T3,T7,T11
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T25
0	1	Covered	T3,T37,T66
1	0	Covered	T3,T66,T99

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T25,T11
0	1	Covered	T7,T25,T11
1	0	Covered	T73,T74,T214

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T25,T11
1	-	Covered	T7,T25,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T7,T25,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T25
DebounceSt->IdleSt	163	Covered	T210,T211,T50
DetectSt->IdleSt	186	Covered	T3,T37,T66
DetectSt->StableSt	191	Covered	T7,T25,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T7,T25,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T210,T211,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T3,T37,T66
DetectSt	-	-	-	-	0	1	-	Covered	T7,T25,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T25
StableSt	-	-	-	-	-	-	1	Covered	T7,T25,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T25,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	2978	0	0
CntIncr_A	6837408	97894	0	0
CntNoWrap_A	6837408	6130266	0	0
DetectStDropOut_A	6837408	303	0	0
DetectedOut_A	6837408	82966	0	0
DetectedPulseOut_A	6837408	1055	0	0
DisabledIdleSt_A	6837408	5671013	0	0
DisabledNoDetection_A	6837408	5673252	0	0
EnterDebounceSt_A	6837408	1499	0	0
EnterDetectSt_A	6837408	1479	0	0
EnterStableSt_A	6837408	1055	0	0
PulseIsPulse_A	6837408	1055	0	0
StayInStableSt	6837408	81771	0	0
gen_high_event_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	893	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	2978	0	0
T3	20692	16	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	42	0	0
T11	0	44	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	10	0	0
T29	0	52	0	0
T37	0	28	0	0
T38	0	20	0	0
T39	0	46	0	0
T44	0	34	0	0
T45	402	0	0	0
T66	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	97894	0	0
T3	20692	478	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	1764	0	0
T11	0	946	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	820	0	0
T29	0	1716	0	0
T37	0	791	0	0
T38	0	630	0	0
T39	0	1840	0	0
T44	0	1411	0	0
T45	402	0	0	0
T66	0	117	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6130266	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20261	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	303	0	0
T3	20692	4	0	0
T5	34049	0	0	0
T6	874	0	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T37	0	14	0	0
T45	402	0	0	0
T66	0	1	0	0
T82	0	8	0	0
T84	0	9	0	0
T193	0	24	0	0
T212	0	7	0	0
T215	0	10	0	0
T216	0	9	0	0
T217	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	82966	0	0
T7	17686	1359	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	1339	0	0
T25	13358	1908	0	0
T29	0	1833	0	0
T36	738	0	0	0
T38	0	46	0	0
T39	0	2485	0	0
T44	0	1453	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	1003	0	0
T101	8401	0	0	0
T102	0	116	0	0
T213	0	203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1055	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	22	0	0
T25	13358	5	0	0
T29	0	26	0	0
T36	738	0	0	0
T38	0	10	0	0
T39	0	23	0	0
T44	0	17	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	9	0	0
T101	8401	0	0	0
T102	0	7	0	0
T213	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5671013	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	17052	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5673252	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	17059	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1499	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	21	0	0
T11	0	22	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	5	0	0
T29	0	26	0	0
T37	0	14	0	0
T38	0	10	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1479	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	21	0	0
T11	0	22	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	5	0	0
T29	0	26	0	0
T37	0	14	0	0
T38	0	10	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1055	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	22	0	0
T25	13358	5	0	0
T29	0	26	0	0
T36	738	0	0	0
T38	0	10	0	0
T39	0	23	0	0
T44	0	17	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	9	0	0
T101	8401	0	0	0
T102	0	7	0	0
T213	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1055	0	0
T7	17686	21	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	22	0	0
T25	13358	5	0	0
T29	0	26	0	0
T36	738	0	0	0
T38	0	10	0	0
T39	0	23	0	0
T44	0	17	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	9	0	0
T101	8401	0	0	0
T102	0	7	0	0
T213	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	81771	0	0
T7	17686	1337	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	1314	0	0
T25	13358	1903	0	0
T29	0	1801	0	0
T36	738	0	0	0
T38	0	36	0	0
T39	0	2456	0	0
T44	0	1435	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	991	0	0
T101	8401	0	0	0
T102	0	109	0	0
T213	0	193	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	893	0	0
T7	17686	20	0	0
T8	2078	0	0	0
T9	520	0	0	0
T11	0	19	0	0
T25	13358	5	0	0
T29	0	20	0	0
T36	738	0	0	0
T38	0	10	0	0
T39	0	17	0	0
T44	0	16	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T100	0	6	0	0
T101	8401	0	0	0
T102	0	7	0	0
T213	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T80,T81,T218
1	0	Covered	T50,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T5
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T1,T5,T39
DetectSt->IdleSt	186	Covered	T80,T81,T218
DetectSt->StableSt	191	Covered	T1,T2,T5
IdleSt->DebounceSt	148	Covered	T1,T2,T5
StableSt->IdleSt	206	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T5,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	1	-	-	Covered	T80,T81,T218
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	951	0	0
CntIncr_A	6837408	48289	0	0
CntNoWrap_A	6837408	6132293	0	0
DetectStDropOut_A	6837408	95	0	0
DetectedOut_A	6837408	15022	0	0
DetectedPulseOut_A	6837408	347	0	0
DisabledIdleSt_A	6837408	5749979	0	0
DisabledNoDetection_A	6837408	5751790	0	0
EnterDebounceSt_A	6837408	507	0	0
EnterDetectSt_A	6837408	446	0	0
EnterStableSt_A	6837408	347	0	0
PulseIsPulse_A	6837408	347	0	0
StayInStableSt	6837408	14617	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	286	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	951	0	0
T1	15813	21	0	0
T2	20694	28	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	3	0	0
T7	0	6	0	0
T11	0	6	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	4	0	0
T29	0	12	0	0
T39	0	11	0	0
T80	0	18	0	0
T81	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	48289	0	0
T1	15813	1716	0	0
T2	20694	2240	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	202	0	0
T7	0	210	0	0
T11	0	123	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	368	0	0
T29	0	336	0	0
T39	0	354	0	0
T80	0	1314	0	0
T81	0	1215	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6132293	0	0
T1	15813	15383	0	0
T2	20694	20251	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	21231	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	95	0	0
T32	39299	0	0	0
T42	821	0	0	0
T43	735	0	0	0
T56	489	0	0	0
T76	0	4	0	0
T78	0	4	0	0
T80	16770	8	0	0
T81	21501	7	0	0
T88	0	4	0	0
T91	0	2	0	0
T94	0	1	0	0
T122	408	0	0	0
T123	402	0	0	0
T149	858	0	0	0
T152	0	5	0	0
T218	0	2	0	0
T219	0	4	0	0
T220	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	15022	0	0
T1	15813	245	0	0
T2	20694	169	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	5	0	0
T7	0	213	0	0
T11	0	223	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	84	0	0
T29	0	365	0	0
T32	0	5	0	0
T39	0	288	0	0
T55	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	347	0	0
T1	15813	9	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	1	0	0
T7	0	3	0	0
T11	0	3	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	6	0	0
T32	0	1	0	0
T39	0	5	0	0
T55	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5749979	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	20277	0	0
T4	422	21	0	0
T5	34049	19466	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5751790	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	19500	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	507	0	0
T1	15813	12	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	2	0	0
T7	0	3	0	0
T11	0	3	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	6	0	0
T39	0	6	0	0
T80	0	10	0	0
T81	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	446	0	0
T1	15813	9	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	1	0	0
T7	0	3	0	0
T11	0	3	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	6	0	0
T39	0	5	0	0
T80	0	8	0	0
T81	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	347	0	0
T1	15813	9	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	1	0	0
T7	0	3	0	0
T11	0	3	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	6	0	0
T32	0	1	0	0
T39	0	5	0	0
T55	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	347	0	0
T1	15813	9	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	1	0	0
T7	0	3	0	0
T11	0	3	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	6	0	0
T32	0	1	0	0
T39	0	5	0	0
T55	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	14617	0	0
T1	15813	236	0	0
T2	20694	155	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	4	0	0
T7	0	210	0	0
T11	0	218	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	82	0	0
T29	0	354	0	0
T32	0	4	0	0
T39	0	278	0	0
T55	0	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	286	0	0
T1	15813	9	0	0
T2	20694	14	0	0
T3	20692	0	0	0
T4	422	0	0	0
T5	34049	1	0	0
T7	0	3	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T25	0	2	0	0
T29	0	1	0	0
T32	0	1	0	0
T55	0	2	0	0
T100	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T3,T7,T25
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T25
0	1	Covered	T25,T37,T38
1	0	Covered	T25,T38,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Covered	T72,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T11
1	-	Covered	T3,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T25
DebounceSt->IdleSt	163	Covered	T210,T211,T50
DetectSt->IdleSt	186	Covered	T25,T37,T38
DetectSt->StableSt	191	Covered	T3,T7,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T3,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T210,T211,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T37,T38
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T25
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	3074	0	0
CntIncr_A	6837408	103213	0	0
CntNoWrap_A	6837408	6130170	0	0
DetectStDropOut_A	6837408	401	0	0
DetectedOut_A	6837408	79282	0	0
DetectedPulseOut_A	6837408	927	0	0
DisabledIdleSt_A	6837408	5674012	0	0
DisabledNoDetection_A	6837408	5676260	0	0
EnterDebounceSt_A	6837408	1549	0	0
EnterDetectSt_A	6837408	1525	0	0
EnterStableSt_A	6837408	927	0	0
PulseIsPulse_A	6837408	927	0	0
StayInStableSt	6837408	78223	0	0
gen_high_event_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	793	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3074	0	0
T3	20692	16	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	46	0	0
T11	0	26	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	54	0	0
T29	0	42	0	0
T37	0	12	0	0
T38	0	58	0	0
T39	0	12	0	0
T44	0	52	0	0
T45	402	0	0	0
T66	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	103213	0	0
T3	20692	472	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	1909	0	0
T11	0	624	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	4812	0	0
T29	0	861	0	0
T37	0	338	0	0
T38	0	1901	0	0
T39	0	378	0	0
T44	0	2418	0	0
T45	402	0	0	0
T66	0	1108	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6130170	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20261	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	401	0	0
T8	2078	0	0	0
T9	520	0	0	0
T25	13358	22	0	0
T36	738	0	0	0
T37	0	6	0	0
T38	0	10	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T66	0	18	0	0
T82	0	12	0	0
T84	0	27	0	0
T86	0	19	0	0
T89	0	11	0	0
T101	8401	0	0	0
T151	404	0	0	0
T212	0	11	0	0
T213	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	79282	0	0
T3	20692	362	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	1832	0	0
T11	0	505	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	1715	0	0
T39	0	347	0	0
T44	0	3004	0	0
T45	402	0	0	0
T85	0	141	0	0
T100	0	1692	0	0
T102	0	648	0	0
T173	0	392	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	927	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	23	0	0
T11	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	21	0	0
T39	0	6	0	0
T44	0	26	0	0
T45	402	0	0	0
T85	0	5	0	0
T100	0	15	0	0
T102	0	13	0	0
T173	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5674012	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	16691	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5676260	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	16696	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1549	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	23	0	0
T11	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	27	0	0
T29	0	21	0	0
T37	0	6	0	0
T38	0	29	0	0
T39	0	6	0	0
T44	0	26	0	0
T45	402	0	0	0
T66	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1525	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	23	0	0
T11	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	27	0	0
T29	0	21	0	0
T37	0	6	0	0
T38	0	29	0	0
T39	0	6	0	0
T44	0	26	0	0
T45	402	0	0	0
T66	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	927	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	23	0	0
T11	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	21	0	0
T39	0	6	0	0
T44	0	26	0	0
T45	402	0	0	0
T85	0	5	0	0
T100	0	15	0	0
T102	0	13	0	0
T173	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	927	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	23	0	0
T11	0	13	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	21	0	0
T39	0	6	0	0
T44	0	26	0	0
T45	402	0	0	0
T85	0	5	0	0
T100	0	15	0	0
T102	0	13	0	0
T173	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	78223	0	0
T3	20692	352	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	1805	0	0
T11	0	491	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	1691	0	0
T39	0	340	0	0
T44	0	2975	0	0
T45	402	0	0	0
T85	0	135	0	0
T100	0	1674	0	0
T102	0	635	0	0
T173	0	381	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	793	0	0
T3	20692	6	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	19	0	0
T11	0	12	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	18	0	0
T39	0	5	0	0
T44	0	23	0	0
T45	402	0	0	0
T85	0	4	0	0
T100	0	12	0	0
T102	0	13	0	0
T173	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T218
1	0	Covered	T50,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T50,T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T32,T44
DetectSt->IdleSt	186	Covered	T2,T5,T218
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T32,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T5,T218
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	849	0	0
CntIncr_A	6837408	40985	0	0
CntNoWrap_A	6837408	6132395	0	0
DetectStDropOut_A	6837408	56	0	0
DetectedOut_A	6837408	15619	0	0
DetectedPulseOut_A	6837408	339	0	0
DisabledIdleSt_A	6837408	5756340	0	0
DisabledNoDetection_A	6837408	5758170	0	0
EnterDebounceSt_A	6837408	453	0	0
EnterDetectSt_A	6837408	399	0	0
EnterStableSt_A	6837408	339	0	0
PulseIsPulse_A	6837408	339	0	0
StayInStableSt	6837408	15243	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	298	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	849	0	0
T1	15813	8	0	0
T2	20694	28	0	0
T3	20692	4	0	0
T4	422	0	0	0
T5	34049	4	0	0
T7	0	8	0	0
T11	0	2	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	4	0	0
T29	0	4	0	0
T39	0	2	0	0
T80	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	40985	0	0
T1	15813	416	0	0
T2	20694	2430	0	0
T3	20692	114	0	0
T4	422	0	0	0
T5	34049	218	0	0
T7	0	284	0	0
T11	0	69	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	110	0	0
T29	0	86	0	0
T39	0	76	0	0
T80	0	266	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6132395	0	0
T1	15813	15396	0	0
T2	20694	20251	0	0
T3	20692	20273	0	0
T4	422	21	0	0
T5	34049	21230	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	56	0	0
T2	20694	13	0	0
T3	20692	0	0	0
T5	34049	2	0	0
T6	874	0	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T90	0	3	0	0
T91	0	1	0	0
T124	0	1	0	0
T133	0	2	0	0
T152	0	5	0	0
T218	0	1	0	0
T221	0	4	0	0
T222	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	15619	0	0
T1	15813	329	0	0
T2	20694	0	0	0
T3	20692	94	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	275	0	0
T11	0	46	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	58	0	0
T29	0	151	0	0
T32	0	446	0	0
T39	0	46	0	0
T80	0	29	0	0
T81	0	16	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	339	0	0
T1	15813	4	0	0
T2	20694	0	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	4	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T32	0	6	0	0
T39	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5756340	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	19917	0	0
T4	422	21	0	0
T5	34049	19466	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5758170	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	19923	0	0
T4	422	22	0	0
T5	34049	19500	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	453	0	0
T1	15813	4	0	0
T2	20694	15	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	2	0	0
T7	0	4	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T39	0	1	0	0
T80	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	399	0	0
T1	15813	4	0	0
T2	20694	13	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	2	0	0
T7	0	4	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T39	0	1	0	0
T80	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	339	0	0
T1	15813	4	0	0
T2	20694	0	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	4	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T32	0	6	0	0
T39	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	339	0	0
T1	15813	4	0	0
T2	20694	0	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	4	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T32	0	6	0	0
T39	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	15243	0	0
T1	15813	325	0	0
T2	20694	0	0	0
T3	20692	92	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	268	0	0
T11	0	44	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	56	0	0
T29	0	149	0	0
T32	0	440	0	0
T39	0	44	0	0
T80	0	27	0	0
T81	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	298	0	0
T1	15813	4	0	0
T2	20694	0	0	0
T3	20692	2	0	0
T4	422	0	0	0
T5	34049	0	0	0
T7	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T20	0	2	0	0
T29	0	2	0	0
T32	0	6	0	0
T44	0	3	0	0
T55	0	3	0	0
T80	0	2	0	0
T81	0	2	0	0