Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T25
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T7,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T25
1	0	Covered	T3,T7,T25
1	1	Covered	T3,T7,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T25
0	1	Covered	T25,T37,T82
1	0	Covered	T25,T100,T213

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T11
1	-	Covered	T3,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T25
DetectSt	168	Covered	T3,T7,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T25
DebounceSt->IdleSt	163	Covered	T210,T211,T50
DetectSt->IdleSt	186	Covered	T25,T37,T82
DetectSt->StableSt	191	Covered	T3,T7,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T25
StableSt->IdleSt	206	Covered	T3,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T25
0	1	Covered	T3,T7,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T25
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T210,T211,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T25
DetectSt	-	-	-	-	1	-	-	Covered	T25,T37,T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T25
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	3012	0	0
CntIncr_A	6837408	95588	0	0
CntNoWrap_A	6837408	6130232	0	0
DetectStDropOut_A	6837408	367	0	0
DetectedOut_A	6837408	75659	0	0
DetectedPulseOut_A	6837408	925	0	0
DisabledIdleSt_A	6837408	5679789	0	0
DisabledNoDetection_A	6837408	5682054	0	0
EnterDebounceSt_A	6837408	1511	0	0
EnterDetectSt_A	6837408	1501	0	0
EnterStableSt_A	6837408	925	0	0
PulseIsPulse_A	6837408	925	0	0
StayInStableSt	6837408	74620	0	0
gen_high_event_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	811	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	3012	0	0
T3	20692	16	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	6	0	0
T11	0	22	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	28	0	0
T29	0	48	0	0
T37	0	26	0	0
T38	0	34	0	0
T39	0	46	0	0
T44	0	34	0	0
T45	402	0	0	0
T66	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	95588	0	0
T3	20692	448	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	156	0	0
T11	0	583	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	2489	0	0
T29	0	1368	0	0
T37	0	734	0	0
T38	0	782	0	0
T39	0	1886	0	0
T44	0	1428	0	0
T45	402	0	0	0
T66	0	195	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6130232	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	20261	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	367	0	0
T8	2078	0	0	0
T9	520	0	0	0
T25	13358	11	0	0
T36	738	0	0	0
T37	0	13	0	0
T46	522	0	0	0
T47	427	0	0	0
T48	514	0	0	0
T49	521	0	0	0
T82	0	31	0	0
T84	0	29	0	0
T85	0	16	0	0
T86	0	14	0	0
T101	8401	0	0	0
T151	404	0	0	0
T173	0	8	0	0
T212	0	26	0	0
T215	0	14	0	0
T223	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	75659	0	0
T3	20692	621	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	141	0	0
T11	0	432	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	1340	0	0
T38	0	1807	0	0
T39	0	2439	0	0
T44	0	1436	0	0
T45	402	0	0	0
T66	0	1299	0	0
T99	0	2275	0	0
T102	0	255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	925	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	11	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	24	0	0
T38	0	17	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	5	0	0
T99	0	31	0	0
T102	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5679789	0	0
T1	15813	15404	0	0
T2	20694	20279	0	0
T3	20692	16462	0	0
T4	422	21	0	0
T5	34049	21234	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5682054	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	16464	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1511	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	11	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	14	0	0
T29	0	24	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	1501	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	11	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T25	0	14	0	0
T29	0	24	0	0
T37	0	13	0	0
T38	0	17	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	925	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	11	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	24	0	0
T38	0	17	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	5	0	0
T99	0	31	0	0
T102	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	925	0	0
T3	20692	8	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	11	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	24	0	0
T38	0	17	0	0
T39	0	23	0	0
T44	0	17	0	0
T45	402	0	0	0
T66	0	5	0	0
T99	0	31	0	0
T102	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	74620	0	0
T3	20692	608	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	138	0	0
T11	0	420	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	1313	0	0
T38	0	1788	0	0
T39	0	2410	0	0
T44	0	1418	0	0
T45	402	0	0	0
T66	0	1294	0	0
T99	0	2241	0	0
T102	0	249	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	811	0	0
T3	20692	3	0	0
T5	34049	0	0	0
T6	874	0	0	0
T7	0	3	0	0
T11	0	10	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T24	503	0	0	0
T29	0	21	0	0
T38	0	15	0	0
T39	0	17	0	0
T44	0	16	0	0
T45	402	0	0	0
T66	0	5	0	0
T99	0	28	0	0
T102	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T224,T152,T94
1	0	Covered	T50,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T5,T38,T32
DetectSt->IdleSt	186	Covered	T224,T152,T94
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T50,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T38,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T224,T152,T94
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6837408	931	0	0
CntIncr_A	6837408	47944	0	0
CntNoWrap_A	6837408	6132313	0	0
DetectStDropOut_A	6837408	30	0	0
DetectedOut_A	6837408	16289	0	0
DetectedPulseOut_A	6837408	402	0	0
DisabledIdleSt_A	6837408	5749118	0	0
DisabledNoDetection_A	6837408	5750957	0	0
EnterDebounceSt_A	6837408	497	0	0
EnterDetectSt_A	6837408	436	0	0
EnterStableSt_A	6837408	402	0	0
PulseIsPulse_A	6837408	402	0	0
StayInStableSt	6837408	15866	0	0
gen_high_level_sva.HighLevelEvent_A	6837408	6135718	0	0
gen_not_sticky_sva.StableStDropOut_A	6837408	376	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	931	0	0
T1	15813	4	0	0
T2	20694	6	0	0
T3	20692	10	0	0
T4	422	0	0	0
T5	34049	3	0	0
T11	0	2	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	10	0	0
T38	0	5	0	0
T39	0	12	0	0
T80	0	4	0	0
T81	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	47944	0	0
T1	15813	360	0	0
T2	20694	474	0	0
T3	20692	340	0	0
T4	422	0	0	0
T5	34049	213	0	0
T11	0	48	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	195	0	0
T38	0	128	0	0
T39	0	492	0	0
T80	0	282	0	0
T81	0	966	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6132313	0	0
T1	15813	15400	0	0
T2	20694	20273	0	0
T3	20692	20267	0	0
T4	422	21	0	0
T5	34049	21231	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	30	0	0
T78	34563	0	0	0
T94	0	6	0	0
T108	665	0	0	0
T152	0	2	0	0
T212	5416	0	0	0
T224	311821	1	0	0
T225	0	1	0	0
T226	0	3	0	0
T227	0	1	0	0
T228	0	11	0	0
T229	0	1	0	0
T230	0	4	0	0
T231	445	0	0	0
T232	426	0	0	0
T233	522	0	0	0
T234	601	0	0	0
T235	665	0	0	0
T236	16134	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	16289	0	0
T1	15813	13	0	0
T2	20694	40	0	0
T3	20692	180	0	0
T4	422	0	0	0
T5	34049	20	0	0
T11	0	68	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	397	0	0
T38	0	131	0	0
T39	0	242	0	0
T80	0	13	0	0
T81	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	402	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	1	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	2	0	0
T39	0	6	0	0
T80	0	2	0	0
T81	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5749118	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	19661	0	0
T4	422	21	0	0
T5	34049	19466	0	0
T12	728	327	0	0
T13	404	3	0	0
T14	50329	49928	0	0
T15	402	1	0	0
T16	435	34	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	5750957	0	0
T1	15813	10072	0	0
T2	20694	16117	0	0
T3	20692	19664	0	0
T4	422	22	0	0
T5	34049	19500	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	497	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	2	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	3	0	0
T39	0	6	0	0
T80	0	2	0	0
T81	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	436	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	1	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	2	0	0
T39	0	6	0	0
T80	0	2	0	0
T81	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	402	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	1	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	2	0	0
T39	0	6	0	0
T80	0	2	0	0
T81	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	402	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	1	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	2	0	0
T39	0	6	0	0
T80	0	2	0	0
T81	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	15866	0	0
T1	15813	11	0	0
T2	20694	37	0	0
T3	20692	175	0	0
T4	422	0	0	0
T5	34049	19	0	0
T11	0	67	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	392	0	0
T38	0	129	0	0
T39	0	234	0	0
T80	0	11	0	0
T81	0	70	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	6135718	0	0
T1	15813	15409	0	0
T2	20694	20287	0	0
T3	20692	20285	0	0
T4	422	22	0	0
T5	34049	21273	0	0
T12	728	328	0	0
T13	404	4	0	0
T14	50329	49929	0	0
T15	402	2	0	0
T16	435	35	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6837408	376	0	0
T1	15813	2	0	0
T2	20694	3	0	0
T3	20692	5	0	0
T4	422	0	0	0
T5	34049	1	0	0
T11	0	1	0	0
T12	728	0	0	0
T13	404	0	0	0
T14	50329	0	0	0
T15	402	0	0	0
T16	435	0	0	0
T29	0	5	0	0
T38	0	2	0	0
T39	0	4	0	0
T80	0	2	0	0
T81	0	6	0	0