Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1214831190	10301	0	0
auto_block_debounce_ctl_rd_A	1214831190	1656	0	0
auto_block_out_ctl_rd_A	1214831190	2453	0	0
com_det_ctl_0_rd_A	1214831190	3578	0	0
com_det_ctl_1_rd_A	1214831190	3626	0	0
com_det_ctl_2_rd_A	1214831190	3766	0	0
com_det_ctl_3_rd_A	1214831190	3758	0	0
com_out_ctl_0_rd_A	1214831190	3988	0	0
com_out_ctl_1_rd_A	1214831190	4341	0	0
com_out_ctl_2_rd_A	1214831190	3937	0	0
com_out_ctl_3_rd_A	1214831190	4192	0	0
com_pre_det_ctl_0_rd_A	1214831190	1205	0	0
com_pre_det_ctl_1_rd_A	1214831190	1193	0	0
com_pre_det_ctl_2_rd_A	1214831190	1225	0	0
com_pre_det_ctl_3_rd_A	1214831190	1127	0	0
com_pre_sel_ctl_0_rd_A	1214831190	4441	0	0
com_pre_sel_ctl_1_rd_A	1214831190	4464	0	0
com_pre_sel_ctl_2_rd_A	1214831190	4445	0	0
com_pre_sel_ctl_3_rd_A	1214831190	4426	0	0
com_sel_ctl_0_rd_A	1214831190	4549	0	0
com_sel_ctl_1_rd_A	1214831190	4290	0	0
com_sel_ctl_2_rd_A	1214831190	4514	0	0
com_sel_ctl_3_rd_A	1214831190	4430	0	0
ec_rst_ctl_rd_A	1214831190	2113	0	0
intr_enable_rd_A	1214831190	1598	0	0
key_intr_ctl_rd_A	1214831190	3735	0	0
key_intr_debounce_ctl_rd_A	1214831190	1213	0	0
key_invert_ctl_rd_A	1214831190	4776	0	0
pin_allowed_ctl_rd_A	1214831190	5551	0	0
pin_out_ctl_rd_A	1214831190	3976	0	0
pin_out_value_rd_A	1214831190	3834	0	0
regwen_rd_A	1214831190	1306	0	0
ulp_ac_debounce_ctl_rd_A	1214831190	1277	0	0
ulp_ctl_rd_A	1214831190	1295	0	0
ulp_lid_debounce_ctl_rd_A	1214831190	1260	0	0
ulp_pwrb_debounce_ctl_rd_A	1214831190	1225	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	10301	0	0
T5	387856	18	0	0
T6	53973	0	0	0
T7	433320	0	0	0
T8	918645	0	0	0
T10	0	11	0	0
T20	0	20	0	0
T24	120955	0	0	0
T25	534376	0	0	0
T32	0	7	0	0
T36	25837	0	0	0
T45	199180	0	0	0
T46	211668	0	0	0
T47	51251	0	0	0
T68	0	13	0	0
T71	0	9	0	0
T83	0	14	0	0
T104	0	5	0	0
T158	0	6	0	0
T254	0	3	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1656	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T7	433320	0	0	0
T10	0	57	0	0
T14	244105	10	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	534376	0	0	0
T36	25837	0	0	0
T42	0	5	0	0
T45	199180	0	0	0
T70	0	12	0	0
T83	0	18	0	0
T105	0	16	0	0
T140	0	19	0	0
T157	0	26	0	0
T166	0	35	0	0
T255	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	2453	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T7	433320	0	0	0
T10	0	71	0	0
T12	25494	14	0	0
T13	97165	0	0	0
T14	244105	6	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T42	0	6	0	0
T45	199180	0	0	0
T70	0	17	0	0
T83	0	18	0	0
T140	0	20	0	0
T157	0	17	0	0
T166	0	27	0	0
T255	0	11	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3578	0	0
T2	258676	53	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	37	0	0
T11	0	115	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	19	0	0
T39	0	99	0	0
T80	0	62	0	0
T83	0	90	0	0
T157	0	30	0	0
T166	0	14	0	0
T256	0	68	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3626	0	0
T2	258676	70	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	17	0	0
T11	0	96	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	22	0	0
T39	0	54	0	0
T80	0	66	0	0
T83	0	52	0	0
T157	0	37	0	0
T166	0	19	0	0
T256	0	73	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3766	0	0
T2	258676	72	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	41	0	0
T11	0	94	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	12	0	0
T39	0	67	0	0
T80	0	68	0	0
T83	0	99	0	0
T157	0	6	0	0
T166	0	11	0	0
T256	0	100	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3758	0	0
T2	258676	67	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	20	0	0
T11	0	82	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	16	0	0
T39	0	72	0	0
T80	0	79	0	0
T83	0	124	0	0
T157	0	38	0	0
T166	0	11	0	0
T256	0	93	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3988	0	0
T2	258676	83	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	27	0	0
T11	0	104	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	33	0	0
T39	0	59	0	0
T80	0	88	0	0
T83	0	103	0	0
T157	0	28	0	0
T166	0	12	0	0
T256	0	52	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4341	0	0
T2	258676	61	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	38	0	0
T11	0	103	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	27	0	0
T39	0	78	0	0
T80	0	93	0	0
T83	0	113	0	0
T157	0	31	0	0
T166	0	14	0	0
T256	0	76	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3937	0	0
T2	258676	59	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	28	0	0
T11	0	115	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	27	0	0
T39	0	108	0	0
T80	0	81	0	0
T83	0	94	0	0
T157	0	29	0	0
T166	0	12	0	0
T256	0	56	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4192	0	0
T2	258676	78	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	23	0	0
T11	0	97	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	18	0	0
T39	0	50	0	0
T80	0	62	0	0
T83	0	80	0	0
T157	0	8	0	0
T166	0	4	0	0
T256	0	92	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1205	0	0
T10	502448	35	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	25	0	0
T105	0	10	0	0
T131	192911	0	0	0
T152	0	13	0	0
T161	0	28	0	0
T166	0	10	0	0
T170	0	10	0	0
T242	0	14	0	0
T257	0	11	0	0
T258	0	15	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1193	0	0
T10	502448	28	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	10	0	0
T105	0	18	0	0
T131	192911	0	0	0
T152	0	18	0	0
T157	0	4	0	0
T161	0	22	0	0
T166	0	14	0	0
T170	0	21	0	0
T257	0	9	0	0
T258	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1225	0	0
T10	502448	28	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	11	0	0
T105	0	17	0	0
T131	192911	0	0	0
T152	0	2	0	0
T161	0	22	0	0
T166	0	13	0	0
T170	0	26	0	0
T242	0	16	0	0
T257	0	13	0	0
T258	0	7	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1127	0	0
T10	502448	32	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	16	0	0
T105	0	12	0	0
T131	192911	0	0	0
T152	0	12	0	0
T157	0	8	0	0
T161	0	18	0	0
T166	0	10	0	0
T170	0	27	0	0
T257	0	8	0	0
T258	0	9	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4441	0	0
T2	258676	66	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	30	0	0
T11	0	107	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	15	0	0
T39	0	66	0	0
T80	0	65	0	0
T83	0	92	0	0
T157	0	29	0	0
T166	0	13	0	0
T256	0	79	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4464	0	0
T2	258676	59	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	31	0	0
T11	0	110	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	26	0	0
T39	0	72	0	0
T80	0	80	0	0
T83	0	79	0	0
T157	0	28	0	0
T166	0	4	0	0
T256	0	68	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4445	0	0
T2	258676	49	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	31	0	0
T11	0	103	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	25	0	0
T39	0	88	0	0
T80	0	79	0	0
T83	0	122	0	0
T157	0	24	0	0
T166	0	15	0	0
T256	0	65	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4426	0	0
T2	258676	79	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	30	0	0
T11	0	70	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	9	0	0
T39	0	81	0	0
T80	0	68	0	0
T83	0	111	0	0
T157	0	19	0	0
T166	0	10	0	0
T256	0	41	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4549	0	0
T2	258676	70	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	33	0	0
T11	0	105	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	29	0	0
T39	0	73	0	0
T80	0	58	0	0
T83	0	91	0	0
T157	0	22	0	0
T166	0	13	0	0
T256	0	59	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4290	0	0
T2	258676	78	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	28	0	0
T11	0	89	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	20	0	0
T39	0	63	0	0
T80	0	61	0	0
T83	0	87	0	0
T157	0	27	0	0
T166	0	17	0	0
T256	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4514	0	0
T2	258676	41	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	40	0	0
T11	0	113	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	22	0	0
T39	0	76	0	0
T80	0	51	0	0
T83	0	98	0	0
T157	0	19	0	0
T166	0	8	0	0
T256	0	57	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4430	0	0
T2	258676	82	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	39	0	0
T11	0	99	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	18	0	0
T39	0	86	0	0
T80	0	53	0	0
T83	0	81	0	0
T157	0	36	0	0
T166	0	10	0	0
T256	0	78	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	2113	0	0
T2	258676	37	0	0
T3	496608	0	0	0
T5	387856	0	0	0
T6	53973	0	0	0
T10	0	41	0	0
T11	0	14	0	0
T12	25494	0	0	0
T13	97165	0	0	0
T14	244105	0	0	0
T15	193059	0	0	0
T16	54485	0	0	0
T24	120955	0	0	0
T25	0	3	0	0
T39	0	22	0	0
T54	0	4	0	0
T57	0	1	0	0
T80	0	32	0	0
T132	0	4	0	0
T259	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1598	0	0
T10	502448	41	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T54	0	19	0	0
T64	284936	0	0	0
T83	0	22	0	0
T105	0	9	0	0
T131	192911	0	0	0
T152	0	18	0	0
T157	0	6	0	0
T161	0	37	0	0
T166	0	17	0	0
T170	0	12	0	0
T260	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3735	0	0
T10	502448	20	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	2	0	0
T83	0	6	0	0
T105	0	29	0	0
T131	192911	0	0	0
T147	0	1	0	0
T152	0	20	0	0
T157	0	14	0	0
T161	0	37	0	0
T166	0	21	0	0
T170	0	24	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1213	0	0
T10	502448	39	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	20	0	0
T105	0	12	0	0
T131	192911	0	0	0
T152	0	16	0	0
T161	0	21	0	0
T166	0	22	0	0
T170	0	24	0	0
T242	0	17	0	0
T257	0	5	0	0
T258	0	7	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	4776	0	0
T10	502448	45	0	0
T11	925451	0	0	0
T23	0	71	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T56	0	46	0	0
T57	0	47	0	0
T64	284936	0	0	0
T83	0	79	0	0
T131	192911	0	0	0
T147	0	71	0	0
T171	0	65	0	0
T175	0	52	0	0
T260	0	132	0	0
T261	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	5551	0	0
T9	110100	0	0	0
T10	502448	137	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T37	259658	0	0	0
T48	25742	30	0	0
T49	245120	0	0	0
T83	0	114	0	0
T101	403266	0	0	0
T105	0	96	0	0
T151	97005	0	0	0
T157	0	127	0	0
T166	0	19	0	0
T260	0	151	0	0
T262	0	67	0	0
T263	0	59	0	0
T264	0	51	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3976	0	0
T9	110100	0	0	0
T10	502448	91	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T37	259658	0	0	0
T48	25742	25	0	0
T49	245120	0	0	0
T83	0	150	0	0
T101	403266	0	0	0
T105	0	109	0	0
T151	97005	0	0	0
T157	0	147	0	0
T166	0	20	0	0
T260	0	150	0	0
T262	0	74	0	0
T263	0	80	0	0
T264	0	47	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	3834	0	0
T9	110100	0	0	0
T10	502448	113	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T37	259658	0	0	0
T48	25742	62	0	0
T49	245120	0	0	0
T83	0	160	0	0
T101	403266	0	0	0
T105	0	123	0	0
T151	97005	0	0	0
T157	0	116	0	0
T166	0	17	0	0
T260	0	152	0	0
T262	0	54	0	0
T263	0	44	0	0
T264	0	72	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1306	0	0
T10	502448	32	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T83	0	8	0	0
T105	0	24	0	0
T131	192911	0	0	0
T152	0	14	0	0
T157	0	3	0	0
T161	0	18	0	0
T166	0	27	0	0
T170	0	31	0	0
T257	0	9	0	0
T258	0	8	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1277	0	0
T10	502448	40	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T67	0	1	0	0
T83	0	11	0	0
T105	0	16	0	0
T119	0	4	0	0
T131	192911	0	0	0
T152	0	16	0	0
T157	0	4	0	0
T166	0	22	0	0
T265	0	8	0	0
T266	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1295	0	0
T10	502448	36	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T54	0	6	0	0
T64	284936	0	0	0
T67	0	7	0	0
T83	0	24	0	0
T105	0	14	0	0
T119	0	12	0	0
T131	192911	0	0	0
T157	0	7	0	0
T166	0	18	0	0
T265	0	15	0	0
T267	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1260	0	0
T10	502448	32	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T54	0	9	0	0
T64	284936	0	0	0
T67	0	9	0	0
T83	0	18	0	0
T105	0	35	0	0
T131	192911	0	0	0
T152	0	7	0	0
T157	0	9	0	0
T166	0	15	0	0
T170	0	16	0	0
T266	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1214831190	1225	0	0
T10	502448	37	0	0
T11	925451	0	0	0
T29	122537	0	0	0
T30	253406	0	0	0
T34	63692	0	0	0
T37	259658	0	0	0
T38	548565	0	0	0
T39	260649	0	0	0
T64	284936	0	0	0
T67	0	1	0	0
T83	0	26	0	0
T105	0	29	0	0
T119	0	8	0	0
T131	192911	0	0	0
T152	0	6	0	0
T157	0	4	0	0
T166	0	24	0	0
T170	0	31	0	0
T265	0	9	0	0