Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1817

1

T7

9

T8

1

T44

8

auto[1]

757

1

T7

1

T8

2

T43

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T7

3

T8

2

T44

6

auto[1]

762

1

T7

7

T8

1

T44

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T7

6

T8

1

T44

6

auto[1]

631

1

T7

4

T8

2

T44

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2013

1

T7

7

T8

3

T44

8

auto[1]

561

1

T7

3

T43

4

T42

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2447

1

T7

10

T8

3

T44

6

auto[1]

127

1

T44

2

T42

6

T45

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2314

1

T7

10

T8

3

T44

8

auto[1]

260

1

T41

1

T35

7

T33

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2321

1

T7

10

T8

3

T44

8

auto[1]

253

1

T42

2

T35

14

T45

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2270

1

T7

10

T8

3

T44

6

auto[1]

304

1

T44

2

T42

13

T125

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2288

1

T7

10

T8

3

T44

8

auto[1]

286

1

T35

7

T36

4

T33

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T7

4

T8

2

T44

8

auto[1]

702

1

T7

6

T8

1

T43

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

902

1

T7

10

T8

3

T43

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T45

8

T255

3

T103

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

74

1

T33

8

T253

2

T256

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T36

2

T257

2

T269

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T42

3

T125

5

T258

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T44

2

T42

3

T255

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

66

1

T101

3

T386

33

T269

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T253

1

T387

1

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

80

1

T42

1

T45

8

T33

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T125

1

T369

1

T388

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T35

7

T36

2

T382

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T389

2

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T101

3

T179

12

T258

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T390

6

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

99

1

T41

1

T125

5

T253

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T254

7

T103

3

T377

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T254

7

T257

3

T223

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T33

1

T101

1

T193

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T179

8

T372

6

T391

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T392

1

T393

3

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T394

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

15

1

T35

7

T254

1

T392

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T33

3

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

104

1

T8

1

T266

10

T101

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

107

1

T261

9

T125

4

T179

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

81

1

T254

1

T179

6

T127

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T35

7

T255

3

T264

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

61

1

T35

7

T261

4

T64

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T45

8

T33

3

T125

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T43

2

T125

5

T253

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T8

1

T33

1

T254

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

84

1

T260

10

T253

1

T98

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T41

1

T45

8

T124

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T42

3

T127

2

T368

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T7

3

T254

7

T395

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T99

2

T312

2

T396

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

34

1

T32

1

T267

1

T103

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T202

2

T371

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

128

1

T99

10

T104

12

T370

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

115

1

T36

2

T33

8

T124

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

79

1

T7

6

T33

6

T261

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T43

4

T262

1

T383

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

77

1

T36

1

T395

12

T263

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T256

3

T263

4

T240

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T34

1

T261

3

T326

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T43

2

T42

1

T370

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T44

2

T42

3

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T7

1

T101

3

T370

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T397

4

T398

2

T396

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T8

1

T125

5

T102

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T34

1

T64

1

T395

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T32

2

T365

1

T374

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T364

1

T78

1

T399

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T364

1

T127

1

T400

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded