Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1191

1

T8

5

T70

8

T73

10

auto[1]

1166

1

T8

15

T70

12

T73

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T8

5

T70

4

T73

4

from_0to1

562

1

T8

4

T70

5

T73

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T8

10

T70

11

T73

15

auto[1]

1172

1

T8

10

T70

9

T73

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T8

10

T70

7

T73

9

auto[1]

1196

1

T8

10

T70

13

T73

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T8

1

T70

1

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T112

1

T114

1

T328

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T8

1

T70

1

T112

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T70

1

T114

1

T412

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T73

1

T112

1

T413

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T73

2

T112

1

T328

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T8

1

T412

1

T413

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T38

1

T81

2

T100

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T8

1

T73

2

T112

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T112

1

T328

1

T412

2

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T8

1

T114

2

T328

3

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T8

1

T70

1

T112

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T114

3

T328

1

T412

1

auto[1]

from_0to1

auto[0]

auto[1]

84

1

T8

1

T70

4

T73

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T73

1

T112

1

T114

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T8

2

T70

1

T112

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T8

11

T70

10

T73

11

auto[1]

1185

1

T8

9

T70

10

T73

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

566

1

T8

6

T70

2

T73

6

from_0to1

577

1

T8

6

T70

3

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T8

10

T70

10

T73

12

auto[1]

1209

1

T8

10

T70

10

T73

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1204

1

T8

9

T70

7

T73

11

auto[1]

1153

1

T8

11

T70

13

T73

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T8

1

T70

1

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T8

3

T73

2

T328

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T112

1

T412

1

T278

1

auto[0]

from_1to0

auto[1]

auto[1]

84

1

T73

1

T412

1

T413

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T70

1

T112

1

T328

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T8

1

T70

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T8

1

T73

1

T114

2

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T8

1

T412

2

T278

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T8

1

T114

3

T412

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T8

1

T112

1

T278

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T112

2

T114

1

T81

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T70

1

T73

1

T114

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T8

1

T73

2

T112

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T70

1

T112

1

T114

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T73

2

T114

2

T81

3

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T8

2

T112

2

T328

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T8

4

T70

11

T73

14

auto[1]

1197

1

T8

16

T70

9

T73

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

563

1

T8

4

T70

5

T73

6

from_0to1

555

1

T8

5

T70

5

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1175

1

T8

9

T70

6

T73

5

auto[1]

1182

1

T8

11

T70

14

T73

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T8

7

T70

11

T73

14

auto[1]

1186

1

T8

13

T70

9

T73

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T70

1

T112

1

T328

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T8

1

T70

1

T278

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T70

2

T73

3

T328

2

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T114

1

T412

2

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T413

1

T278

1

T81

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T73

2

T38

1

T81

1

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T70

1

T73

2

T112

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T8

1

T70

2

T73

2

auto[1]

from_1to0

auto[0]

auto[0]

84

1

T112

1

T413

3

T278

2

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T8

2

T73

1

T112

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T8

1

T73

2

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T70

1

T112

2

T114

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T412

2

T278

1

T81

1

auto[1]

from_0to1

auto[0]

auto[1]

89

1

T8

1

T70

1

T112

3

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T8

2

T70

1

T112

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T8

1

T114

2

T81

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T8

11

T70

6

T73

10

auto[1]

1226

1

T8

9

T70

14

T73

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T8

3

T70

3

T73

6

from_0to1

557

1

T8

3

T70

3

T73

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T8

9

T70

11

T73

13

auto[1]

1196

1

T8

11

T70

9

T73

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T8

8

T70

10

T73

11

auto[1]

1191

1

T8

12

T70

10

T73

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T8

1

T70

1

T114

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T8

2

T70

1

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T73

1

T114

1

T328

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T112

1

T412

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T70

1

T73

2

T328

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T8

1

T73

1

T112

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

1

T114

1

T278

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T328

3

T412

2

T413

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T70

1

T73

2

T112

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T73

2

T114

3

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T114

1

T413

1

T278

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T328

3

T38

1

T322

3

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T70

1

T73

1

T114

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T73

1

T413

2

T278

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T8

1

T70

1

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T73

1

T112

2

T114

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T8

9

T70

9

T73

12

auto[1]

1177

1

T8

11

T70

11

T73

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

556

1

T8

4

T70

6

T73

6

from_0to1

546

1

T8

5

T70

5

T73

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T8

12

T70

8

T73

9

auto[1]

1228

1

T8

8

T70

12

T73

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T8

8

T70

11

T73

8

auto[1]

1164

1

T8

12

T70

9

T73

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T8

1

T70

1

T73

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T8

2

T73

1

T114

2

auto[0]

from_1to0

auto[1]

auto[0]

84

1

T8

1

T70

2

T328

2

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T73

3

T114

1

T412

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T112

1

T114

1

T328

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T73

1

T112

1

T328

1

auto[0]

from_0to1

auto[1]

auto[0]

87

1

T70

1

T73

1

T112

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T8

1

T70

1

T413

2

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T70

1

T112

2

T328

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T328

2

T412

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T70

1

T73

1

T112

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T70

1

T413

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T70

1

T73

2

T112

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T8

1

T70

2

T328

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T8

3

T114

1

T328

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T73

1

T328

1

T412

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T8

10

T70

9

T73

13

auto[1]

1157

1

T8

10

T70

11

T73

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T8

6

T70

3

T73

6

from_0to1

584

1

T8

6

T70

4

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1156

1

T8

5

T70

10

T73

10

auto[1]

1201

1

T8

15

T70

10

T73

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1213

1

T8

14

T70

9

T73

7

auto[1]

1144

1

T8

6

T70

11

T73

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

87

1

T112

1

T328

2

T413

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T70

2

T73

2

T112

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T8

1

T412

2

T413

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T8

1

T73

1

T112

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T8

1

T73

1

T112

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T8

1

T70

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T8

2

T328

1

T412

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T73

1

T112

2

T114

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T412

1

T278

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T112

1

T114

1

T328

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T8

2

T70

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

86

1

T8

2

T73

2

T112

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T73

1

T112

1

T328

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T8

1

T70

1

T114

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T8

1

T73

1

T112

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T70

2

T73

1

T114

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T8

11

T70

10

T73

11

auto[1]

1176

1

T8

9

T70

10

T73

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

553

1

T8

4

T70

5

T73

5

from_0to1

546

1

T8

4

T70

4

T73

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T8

13

T70

9

T73

10

auto[1]

1217

1

T8

7

T70

11

T73

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T8

11

T70

7

T73

12

auto[1]

1195

1

T8

9

T70

13

T73

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T8

1

T73

1

T412

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T8

1

T70

1

T112

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T73

1

T112

1

T412

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T8

1

T70

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T8

2

T73

1

T114

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T70

1

T73

2

T112

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T73

1

T112

1

T114

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T70

2

T112

1

T413

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T8

1

T73

1

T114

3

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T70

2

T112

1

T328

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T70

1

T38

1

T80

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T73

1

T112

2

T114

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T412

1

T38

1

T81

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T112

1

T114

2

T328

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T112

1

T413

1

T80

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T8

2

T70

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199

1

T8

14

T70

6

T73

11

auto[1]

1158

1

T8

6

T70

14

T73

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

564

1

T8

4

T70

4

T73

6

from_0to1

559

1

T8

5

T70

5

T73

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T8

10

T70

11

T73

9

auto[1]

1151

1

T8

10

T70

9

T73

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T8

9

T70

12

T73

10

auto[1]

1162

1

T8

11

T70

8

T73

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T70

1

T112

1

T328

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T8

3

T114

1

T328

1

auto[0]

from_1to0

auto[1]

auto[0]

84

1

T8

1

T73

2

T112

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T73

1

T81

3

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

83

1

T70

1

T73

1

T114

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T413

1

T278

1

T38

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T8

1

T70

2

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

81

1

T8

3

T73

2

T112

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T70

1

T73

1

T328

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T70

1

T413

1

T278

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T70

1

T73

1

T112

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T73

1

T114

1

T412

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T73

1

T278

1

T80

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T70

1

T412

1

T278

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T112

1

T114

1

T328

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T8

1

T70

1

T73

1