Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119920

1

T4

3

T1

10

T5

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144319	1			T4	2		T1	15		T5	8
values[0x0]	65367	1			T4	9		T1	4		T5	2
values[0x1]	66536	1			T4	12		T1	4		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149634

1

T4

4

T1

17

T5

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1235	1			T10	3		T73	1		T43	4
valid_sources[0x01]	908	1			T17	4		T28	5		T43	3
valid_sources[0x02]	955	1			T7	3		T61	8		T28	2
valid_sources[0x03]	939	1			T16	1		T17	6		T28	1
valid_sources[0x04]	858	1			T17	2		T52	3		T73	3
valid_sources[0x05]	1056	1			T7	3		T28	2		T73	2
valid_sources[0x06]	1102	1			T17	5		T7	2		T73	1
valid_sources[0x07]	840	1			T17	1		T28	1		T41	2
valid_sources[0x08]	1053	1			T17	9		T73	3		T43	4
valid_sources[0x09]	801	1			T16	1		T28	1		T73	1
valid_sources[0x0a]	870	1			T7	5		T8	4		T28	1
valid_sources[0x0b]	809	1			T13	1		T17	4		T28	3
valid_sources[0x0c]	953	1			T15	4		T28	5		T47	1
valid_sources[0x0d]	991	1			T28	4		T73	2		T41	3
valid_sources[0x0e]	1065	1			T7	4		T73	1		T43	1
valid_sources[0x0f]	864	1			T7	9		T26	7		T60	2
valid_sources[0x10]	963	1			T73	1		T43	1		T41	3
valid_sources[0x11]	992	1			T28	1		T73	1		T43	5
valid_sources[0x12]	1050	1			T7	8		T28	3		T73	1
valid_sources[0x13]	1068	1			T7	1		T73	1		T41	1
valid_sources[0x14]	1658	1			T53	1		T55	5		T73	1
valid_sources[0x15]	1142	1			T17	15		T28	2		T43	1
valid_sources[0x16]	732	1			T15	2		T7	1		T8	1
valid_sources[0x17]	1190	1			T26	18		T28	3		T73	1
valid_sources[0x18]	782	1			T17	5		T8	1		T66	8
valid_sources[0x19]	1091	1			T8	5		T28	1		T43	1
valid_sources[0x1a]	969	1			T8	11		T28	1		T43	1
valid_sources[0x1b]	1077	1			T7	1		T8	14		T28	2
valid_sources[0x1c]	1115	1			T16	1		T28	1		T73	1
valid_sources[0x1d]	895	1			T28	2		T73	1		T43	1
valid_sources[0x1e]	842	1			T8	5		T28	3		T43	1
valid_sources[0x1f]	821	1			T28	1		T43	7		T41	2
valid_sources[0x20]	940	1			T8	4		T43	2		T41	3
valid_sources[0x21]	1091	1			T7	16		T8	9		T28	2
valid_sources[0x22]	1569	1			T15	8		T28	1		T47	1
valid_sources[0x23]	841	1			T16	1		T26	3		T28	1
valid_sources[0x24]	924	1			T17	16		T72	2		T41	3
valid_sources[0x25]	941	1			T52	1		T7	1		T26	9
valid_sources[0x26]	1137	1			T1	1		T16	1		T17	1
valid_sources[0x27]	1060	1			T7	19		T28	2		T47	3
valid_sources[0x28]	1399	1			T26	38		T73	1		T43	1
valid_sources[0x29]	1350	1			T7	1		T28	1		T46	1
valid_sources[0x2a]	909	1			T7	2		T8	10		T28	2
valid_sources[0x2b]	1134	1			T28	1		T46	1		T47	1
valid_sources[0x2c]	1217	1			T17	3		T7	3		T26	5
valid_sources[0x2d]	989	1			T7	5		T8	5		T28	1
valid_sources[0x2e]	1600	1			T2	2		T26	9		T72	1
valid_sources[0x2f]	3077	1			T8	1		T28	3		T41	2
valid_sources[0x30]	1695	1			T16	1		T17	3		T28	3
valid_sources[0x31]	1041	1			T17	19		T46	1		T73	2
valid_sources[0x32]	1198	1			T52	5		T7	1		T8	26
valid_sources[0x33]	832	1			T47	6		T43	1		T41	3
valid_sources[0x34]	1121	1			T17	20		T8	7		T28	1
valid_sources[0x35]	870	1			T7	8		T28	2		T177	9
valid_sources[0x36]	903	1			T17	1		T26	7		T8	38
valid_sources[0x37]	1589	1			T17	1		T73	1		T43	1
valid_sources[0x38]	1112	1			T28	2		T73	1		T43	2
valid_sources[0x39]	1298	1			T53	1		T28	2		T73	1
valid_sources[0x3a]	978	1			T1	3		T7	9		T28	2
valid_sources[0x3b]	1175	1			T28	1		T43	3		T41	4
valid_sources[0x3c]	938	1			T17	2		T7	6		T8	17
valid_sources[0x3d]	728	1			T61	1		T28	2		T73	1
valid_sources[0x3e]	1178	1			T8	19		T28	5		T73	2
valid_sources[0x3f]	939	1			T2	5		T70	122		T28	4
valid_sources[0x40]	896	1			T7	7		T26	1		T28	1
valid_sources[0x41]	901	1			T7	13		T28	1		T41	2
valid_sources[0x42]	857	1			T7	44		T28	8		T73	1
valid_sources[0x43]	956	1			T7	8		T8	1		T66	4
valid_sources[0x44]	1800	1			T28	3		T72	1		T43	3
valid_sources[0x45]	964	1			T17	7		T52	4		T28	3
valid_sources[0x46]	800	1			T8	6		T28	1		T41	2
valid_sources[0x47]	859	1			T16	2		T17	4		T8	29
valid_sources[0x48]	932	1			T16	1		T341	1		T28	4
valid_sources[0x49]	2138	1			T17	6		T28	6		T41	9
valid_sources[0x4a]	1165	1			T8	8		T43	2		T35	9
valid_sources[0x4b]	1166	1			T7	8		T28	1		T41	3
valid_sources[0x4c]	757	1			T15	1		T17	4		T7	1
valid_sources[0x4d]	936	1			T7	4		T28	4		T46	1
valid_sources[0x4e]	925	1			T8	4		T66	2		T28	1
valid_sources[0x4f]	1765	1			T5	1		T8	2		T28	3
valid_sources[0x50]	879	1			T7	5		T8	1		T28	2
valid_sources[0x51]	860	1			T7	1		T73	3		T41	1
valid_sources[0x52]	992	1			T28	2		T72	1		T41	5
valid_sources[0x53]	1064	1			T17	2		T8	30		T66	1
valid_sources[0x54]	810	1			T7	2		T8	3		T28	1
valid_sources[0x55]	1161	1			T7	3		T28	2		T41	5
valid_sources[0x56]	910	1			T1	3		T26	12		T8	13
valid_sources[0x57]	1013	1			T28	6		T43	1		T41	7
valid_sources[0x58]	888	1			T15	6		T17	4		T8	19
valid_sources[0x59]	1203	1			T17	11		T7	4		T28	5
valid_sources[0x5a]	1026	1			T16	1		T17	15		T28	2
valid_sources[0x5b]	750	1			T8	10		T28	4		T43	3
valid_sources[0x5c]	1882	1			T17	7		T341	1		T28	2
valid_sources[0x5d]	929	1			T17	3		T7	20		T26	66
valid_sources[0x5e]	784	1			T7	5		T28	1		T43	1
valid_sources[0x5f]	980	1			T7	6		T28	2		T43	3
valid_sources[0x60]	1370	1			T17	15		T7	5		T8	31
valid_sources[0x61]	931	1			T7	2		T53	2		T28	2
valid_sources[0x62]	1077	1			T28	4		T41	2		T35	2
valid_sources[0x63]	1090	1			T52	9		T8	37		T73	1
valid_sources[0x64]	950	1			T52	1		T8	5		T28	1
valid_sources[0x65]	927	1			T1	2		T13	3		T28	3
valid_sources[0x66]	851	1			T17	10		T52	1		T8	5
valid_sources[0x67]	2018	1			T17	4		T28	2		T43	2
valid_sources[0x68]	860	1			T7	5		T177	1		T43	2
valid_sources[0x69]	952	1			T66	2		T73	1		T41	3
valid_sources[0x6a]	888	1			T8	15		T28	3		T43	3
valid_sources[0x6b]	1138	1			T7	4		T28	2		T41	3
valid_sources[0x6c]	827	1			T7	1		T28	2		T73	2
valid_sources[0x6d]	821	1			T17	3		T53	1		T43	2
valid_sources[0x6e]	905	1			T17	7		T52	1		T66	1
valid_sources[0x6f]	1266	1			T53	1		T28	1		T43	1
valid_sources[0x70]	1146	1			T17	7		T7	8		T66	3
valid_sources[0x71]	1091	1			T3	90		T60	1		T28	4
valid_sources[0x72]	965	1			T1	1		T28	1		T43	2
valid_sources[0x73]	1121	1			T53	1		T43	4		T41	5
valid_sources[0x74]	834	1			T8	1		T61	3		T28	1
valid_sources[0x75]	1136	1			T28	1		T72	2		T43	6
valid_sources[0x76]	969	1			T41	4		T35	4		T114	1
valid_sources[0x77]	835	1			T43	5		T41	3		T35	8
valid_sources[0x78]	1160	1			T2	2		T61	4		T28	3
valid_sources[0x79]	949	1			T28	1		T73	1		T41	3
valid_sources[0x7a]	1085	1			T4	20		T15	12		T17	10
valid_sources[0x7b]	1187	1			T7	5		T28	2		T72	1
valid_sources[0x7c]	2179	1			T17	5		T7	4		T28	4
valid_sources[0x7d]	870	1			T28	1		T35	4		T111	1
valid_sources[0x7e]	965	1			T73	2		T41	3		T35	4
valid_sources[0x7f]	1059	1			T7	8		T8	2		T27	2
valid_sources[0x80]	754	1			T16	2		T7	1		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65434

1

T1

6

T5

6

T2

3

values[0x0]

all_enables

biggest_size

31871

1

T4

2

T1

4

T5

1

values[0x1]

all_enables

biggest_size

22615

1

T4

1

T5

1

T2

1