Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T8,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T16,T8,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T16,T8,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T8,T46
1	0	Covered	T1,T5,T2
1	1	Covered	T16,T8,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T46
0	1	Covered	T84,T85,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T8,T46
0	1	Covered	T16,T8,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T8,T46
1	-	Covered	T16,T8,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T8,T46
DetectSt	168	Covered	T16,T8,T46
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T16,T8,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T8,T46
DebounceSt->IdleSt	163	Covered	T16,T46,T80
DetectSt->IdleSt	186	Covered	T84,T85,T107
DetectSt->StableSt	191	Covered	T16,T8,T46
IdleSt->DebounceSt	148	Covered	T16,T8,T46
StableSt->IdleSt	206	Covered	T16,T8,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T8,T46
0	1	Covered	T16,T8,T46
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T8,T46
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T8,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T8,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T46,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T8,T46
DetectSt	-	-	-	-	1	-	-	Covered	T84,T85,T107
DetectSt	-	-	-	-	0	1	-	Covered	T16,T8,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T8,T46
StableSt	-	-	-	-	-	-	0	Covered	T16,T8,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	275	0	0
CntIncr_A	8285647	46314	0	0
CntNoWrap_A	8285647	7611640	0	0
DetectStDropOut_A	8285647	4	0	0
DetectedOut_A	8285647	825	0	0
DetectedPulseOut_A	8285647	124	0	0
DisabledIdleSt_A	8285647	7559227	0	0
DisabledNoDetection_A	8285647	7561560	0	0
EnterDebounceSt_A	8285647	153	0	0
EnterDetectSt_A	8285647	128	0	0
EnterStableSt_A	8285647	124	0	0
PulseIsPulse_A	8285647	124	0	0
StayInStableSt	8285647	701	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6881	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	124	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	275	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	2	0	0
T16	624	3	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	2	0	0
T40	0	4	0	0
T46	0	5	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	4	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	46314	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	15	0	0
T16	624	68	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	41	0	0
T46	0	135	0	0
T47	0	38	0	0
T48	0	20	0	0
T49	0	53	0	0
T51	0	160	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T80	0	772	0	0
T96	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611640	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	220	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	4	0	0
T84	7765	2	0	0
T85	0	1	0	0
T105	29258	0	0	0
T107	0	1	0	0
T115	13124	0	0	0
T116	14370	0	0	0
T117	660	0	0	0
T118	595	0	0	0
T119	748	0	0	0
T120	759	0	0	0
T121	506	0	0	0
T122	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	825	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	7	0	0
T16	624	3	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	7	0	0
T40	0	20	0	0
T46	0	9	0	0
T47	0	3	0	0
T48	0	4	0	0
T49	0	7	0	0
T51	0	18	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	1	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7559227	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	83	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7561560	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	83	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	153	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	2	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T80	0	1	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	128	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	1	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	1	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	1	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	701	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	6	0	0
T16	624	2	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	6	0	0
T40	0	18	0	0
T46	0	7	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	0	6	0	0
T51	0	16	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6881	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	10	0	0
T5	36896	3	0	0
T6	0	8	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	5	0	0
T16	624	3	0	0
T17	4766	21	0	0
T18	422	3	0	0
T52	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	1	0	0
T16	624	1	0	0
T17	4766	0	0	0
T18	422	0	0	0
T26	5166	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T5,T2
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T11,T94,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Unreachable
1	0	Covered	T3,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T11
DebounceSt->IdleSt	163	Covered	T9,T11,T64
DetectSt->IdleSt	186	Covered	T11,T94,T89
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T11,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T94,T89
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	190	0	0
CntIncr_A	8285647	5835	0	0
CntNoWrap_A	8285647	7611725	0	0
DetectStDropOut_A	8285647	21	0	0
DetectedOut_A	8285647	12722	0	0
DetectedPulseOut_A	8285647	56	0	0
DisabledIdleSt_A	8285647	5846619	0	0
DisabledNoDetection_A	8285647	5849008	0	0
EnterDebounceSt_A	8285647	113	0	0
EnterDetectSt_A	8285647	77	0	0
EnterStableSt_A	8285647	56	0	0
PulseIsPulse_A	8285647	56	0	0
StayInStableSt	8285647	12666	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6881	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_sticky_sva.StableStDropOut_A	8285647	1054191	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	190	0	0
T3	2393	2	0	0
T6	1307	4	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	11	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	4	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	4	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5835	0	0
T3	2393	25	0	0
T6	1307	22	0	0
T7	20110	0	0	0
T9	0	52	0	0
T11	0	354	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	126	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	48	0	0
T80	0	58	0	0
T81	0	79	0	0
T82	0	54	0	0
T83	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611725	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	788	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	21	0	0
T11	1438	4	0	0
T12	2687	0	0	0
T27	477	0	0	0
T28	5116	0	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T66	495	0	0	0
T72	521	0	0	0
T89	0	3	0	0
T94	0	1	0	0
T128	0	3	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	4	0	0
T135	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	12722	0	0
T3	2393	128	0	0
T6	1307	86	0	0
T7	20110	0	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	495	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	51	0	0
T81	0	659	0	0
T83	0	107	0	0
T87	0	6	0	0
T92	0	235	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	2	0	0
T87	0	1	0	0
T92	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5846619	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	463	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5849008	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	466	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	113	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	6	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T11	0	5	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	2	0	0
T87	0	1	0	0
T92	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	2	0	0
T87	0	1	0	0
T92	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	2	0	0
T87	0	1	0	0
T92	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	12666	0	0
T3	2393	127	0	0
T6	1307	84	0	0
T7	20110	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	493	0	0
T52	441	0	0	0
T53	415	0	0	0
T80	0	50	0	0
T81	0	658	0	0
T83	0	105	0	0
T87	0	5	0	0
T92	0	234	0	0
T95	0	607	0	0
T126	0	84	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6881	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	10	0	0
T5	36896	3	0	0
T6	0	8	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	5	0	0
T16	624	3	0	0
T17	4766	21	0	0
T18	422	3	0	0
T52	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1054191	0	0
T3	2393	158	0	0
T6	1307	696	0	0
T7	20110	0	0	0
T11	0	29	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	705	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	128	0	0
T80	0	26	0	0
T81	0	97	0	0
T83	0	345	0	0
T87	0	4570	0	0
T92	0	404	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T11,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Unreachable
1	0	Covered	T3,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T9
DebounceSt->IdleSt	163	Covered	T11,T38,T83
DetectSt->IdleSt	186	Covered	T11,T92,T93
DetectSt->StableSt	191	Covered	T3,T6,T9
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T38,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	193	0	0
CntIncr_A	8285647	208098	0	0
CntNoWrap_A	8285647	7611722	0	0
DetectStDropOut_A	8285647	17	0	0
DetectedOut_A	8285647	677913	0	0
DetectedPulseOut_A	8285647	51	0	0
DisabledIdleSt_A	8285647	5846619	0	0
DisabledNoDetection_A	8285647	5849008	0	0
EnterDebounceSt_A	8285647	125	0	0
EnterDetectSt_A	8285647	68	0	0
EnterStableSt_A	8285647	51	0	0
PulseIsPulse_A	8285647	51	0	0
StayInStableSt	8285647	677862	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_sticky_sva.StableStDropOut_A	8285647	576625	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	193	0	0
T3	2393	2	0	0
T6	1307	4	0	0
T7	20110	0	0	0
T9	0	2	0	0
T11	0	10	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	6	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	208098	0	0
T3	2393	31	0	0
T6	1307	74	0	0
T7	20110	0	0	0
T9	0	42	0	0
T11	0	336	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	431	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	32	0	0
T80	0	67	0	0
T81	0	54	0	0
T82	0	44	0	0
T83	0	312	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611722	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	788	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	17	0	0
T11	1438	4	0	0
T12	2687	0	0	0
T27	477	0	0	0
T28	5116	0	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T66	495	0	0	0
T72	521	0	0	0
T92	0	1	0	0
T93	0	2	0	0
T135	425	0	0	0
T136	0	7	0	0
T137	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	677913	0	0
T3	2393	191	0	0
T6	1307	324	0	0
T7	20110	0	0	0
T9	0	13	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	716	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	118	0	0
T80	0	1	0	0
T81	0	268	0	0
T82	0	3	0	0
T92	0	270	0	0
T126	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	51	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T92	0	1	0	0
T126	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5846619	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	463	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5849008	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	466	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	125	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	6	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	5	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	68	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	4	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T92	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	51	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T92	0	1	0	0
T126	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	51	0	0
T3	2393	1	0	0
T6	1307	2	0	0
T7	20110	0	0	0
T9	0	1	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T92	0	1	0	0
T126	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	677862	0	0
T3	2393	190	0	0
T6	1307	322	0	0
T7	20110	0	0	0
T9	0	12	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	715	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	117	0	0
T81	0	267	0	0
T82	0	2	0	0
T92	0	269	0	0
T94	0	352	0	0
T126	0	31	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	576625	0	0
T3	2393	87	0	0
T6	1307	418	0	0
T7	20110	0	0	0
T9	0	56	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	109	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	264	0	0
T80	0	63	0	0
T81	0	529	0	0
T82	0	71	0	0
T92	0	202	0	0
T126	0	201	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Unreachable
1	0	Covered	T3,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T6,T95,T57
DetectSt->IdleSt	186	Covered	T87,T88,T89
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T95,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T87,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	216	0	0
CntIncr_A	8285647	195901	0	0
CntNoWrap_A	8285647	7611699	0	0
DetectStDropOut_A	8285647	23	0	0
DetectedOut_A	8285647	685769	0	0
DetectedPulseOut_A	8285647	53	0	0
DisabledIdleSt_A	8285647	5846619	0	0
DisabledNoDetection_A	8285647	5849008	0	0
EnterDebounceSt_A	8285647	140	0	0
EnterDetectSt_A	8285647	76	0	0
EnterStableSt_A	8285647	53	0	0
PulseIsPulse_A	8285647	53	0	0
StayInStableSt	8285647	685716	0	0
gen_high_event_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_sticky_sva.StableStDropOut_A	8285647	807173	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	216	0	0
T3	2393	2	0	0
T6	1307	8	0	0
T7	20110	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	4	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	195901	0	0
T3	2393	16	0	0
T6	1307	568	0	0
T7	20110	0	0	0
T9	0	56	0	0
T11	0	20	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	99	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	75	0	0
T80	0	12	0	0
T81	0	76	0	0
T82	0	77	0	0
T83	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611699	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	788	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	23	0	0
T87	11543	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T104	35691	0	0	0
T133	0	1	0	0
T136	0	7	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	62521	0	0	0
T142	903	0	0	0
T143	861	0	0	0
T144	437	0	0	0
T145	402	0	0	0
T146	503	0	0	0
T147	5416	0	0	0
T148	662	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	685769	0	0
T3	2393	96	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	32	0	0
T11	0	62	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	590	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	312	0	0
T80	0	7	0	0
T81	0	432	0	0
T82	0	20	0	0
T83	0	187	0	0
T92	0	593	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T3	2393	1	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T92	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5846619	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	463	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	5849008	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	466	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	140	0	0
T3	2393	1	0	0
T6	1307	8	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	76	0	0
T3	2393	1	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T92	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T3	2393	1	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T92	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T3	2393	1	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T92	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	685716	0	0
T3	2393	95	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	31	0	0
T11	0	60	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	588	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	311	0	0
T80	0	6	0	0
T81	0	431	0	0
T82	0	19	0	0
T83	0	185	0	0
T92	0	592	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	807173	0	0
T3	2393	208	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T9	0	38	0	0
T11	0	449	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	668	0	0
T52	441	0	0	0
T53	415	0	0	0
T64	0	46	0	0
T80	0	128	0	0
T81	0	347	0	0
T82	0	39	0	0
T83	0	241	0	0
T92	0	43	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T12,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T2,T12,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T37
0	1	Covered	T2,T12,T39
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T37
1	-	Covered	T2,T12,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T37
DetectSt	168	Covered	T2,T12,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T12,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T37
DebounceSt->IdleSt	163	Covered	T149,T150
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T12,T37
IdleSt->DebounceSt	148	Covered	T2,T12,T37
StableSt->IdleSt	206	Covered	T2,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T37
0	1	Covered	T2,T12,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T150
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T12,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	82	0	0
CntIncr_A	8285647	112090	0	0
CntNoWrap_A	8285647	7611833	0	0
DetectStDropOut_A	8285647	0	0	0
DetectedOut_A	8285647	20234	0	0
DetectedPulseOut_A	8285647	40	0	0
DisabledIdleSt_A	8285647	7154969	0	0
DisabledNoDetection_A	8285647	7157293	0	0
EnterDebounceSt_A	8285647	43	0	0
EnterDetectSt_A	8285647	40	0	0
EnterStableSt_A	8285647	40	0	0
PulseIsPulse_A	8285647	40	0	0
StayInStableSt	8285647	20170	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	82	0	0
T2	669	2	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	4	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T52	441	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	112090	0	0
T2	669	34	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	87	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T39	0	54802	0	0
T40	0	41	0	0
T52	441	0	0	0
T151	0	23	0	0
T152	0	79	0	0
T153	0	47	0	0
T154	0	52	0	0
T155	0	15448	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611833	0	0
T1	990	589	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	20234	0	0
T2	669	31	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	81	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	149	0	0
T39	0	17310	0	0
T40	0	52	0	0
T52	441	0	0	0
T151	0	52	0	0
T152	0	39	0	0
T153	0	42	0	0
T154	0	389	0	0
T155	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	40	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7154969	0	0
T1	990	589	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7157293	0	0
T1	990	590	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	43	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	40	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	40	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	40	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	20170	0	0
T2	669	30	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	78	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	147	0	0
T39	0	17307	0	0
T40	0	51	0	0
T52	441	0	0	0
T151	0	50	0	0
T152	0	37	0	0
T153	0	40	0	0
T154	0	387	0	0
T155	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	14	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	441	0	0	0
T90	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T39,T40
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T40
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T40
0	1	Covered	T1,T39,T40
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T39,T40
1	-	Covered	T1,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T39,T40
DetectSt	168	Covered	T1,T39,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T39,T40
DebounceSt->IdleSt	163	Covered	T160,T161
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T1,T39,T40
IdleSt->DebounceSt	148	Covered	T1,T39,T40
StableSt->IdleSt	206	Covered	T1,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T39,T40
0	1	Covered	T1,T39,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T39,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T160,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	122	0	0
CntIncr_A	8285647	97608	0	0
CntNoWrap_A	8285647	7611793	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	80663	0	0
DetectedPulseOut_A	8285647	59	0	0
DisabledIdleSt_A	8285647	7300573	0	0
DisabledNoDetection_A	8285647	7302910	0	0
EnterDebounceSt_A	8285647	62	0	0
EnterDetectSt_A	8285647	60	0	0
EnterStableSt_A	8285647	59	0	0
PulseIsPulse_A	8285647	59	0	0
StayInStableSt	8285647	80575	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	2754	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	122	0	0
T1	990	6	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	4	0	0
T40	0	4	0	0
T77	0	2	0	0
T78	0	2	0	0
T151	0	2	0	0
T153	0	2	0	0
T154	0	2	0	0
T162	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	97608	0	0
T1	990	177	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	54802	0	0
T40	0	82	0	0
T77	0	43	0	0
T78	0	16	0	0
T151	0	23	0	0
T153	0	47	0	0
T154	0	52	0	0
T162	0	74	0	0
T163	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611793	0	0
T1	990	583	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T91	501	1	0	0
T138	1404	0	0	0
T164	416	0	0	0
T165	522	0	0	0
T166	498	0	0	0
T167	504	0	0	0
T168	89134	0	0	0
T169	149485	0	0	0
T170	428	0	0	0
T171	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	80663	0	0
T1	990	224	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	54804	0	0
T40	0	56	0	0
T77	0	86	0	0
T78	0	66	0	0
T151	0	44	0	0
T153	0	38	0	0
T154	0	1	0	0
T162	0	259	0	0
T163	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T1	990	3	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7300573	0	0
T1	990	3	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7302910	0	0
T1	990	3	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	62	0	0
T1	990	3	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	60	0	0
T1	990	3	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T1	990	3	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T1	990	3	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	80575	0	0
T1	990	220	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	54802	0	0
T40	0	53	0	0
T77	0	84	0	0
T78	0	64	0	0
T95	0	74	0	0
T151	0	43	0	0
T153	0	37	0	0
T162	0	257	0	0
T163	0	103	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2754	0	0
T1	990	3	0	0
T2	669	2	0	0
T3	2393	5	0	0
T5	36896	0	0	0
T8	0	47	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	3	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	2	0	0
T24	0	6	0	0
T25	0	6	0	0
T52	0	4	0	0
T56	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	28	0	0
T1	990	2	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0