Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T37,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T12,T37,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T39
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T39
0	1	Covered	T12,T39,T152
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T39
1	-	Covered	T12,T39,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T37,T39
DetectSt	168	Covered	T12,T37,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T37,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T37,T39
DebounceSt->IdleSt	163	Covered	T174
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T12,T37,T39
IdleSt->DebounceSt	148	Covered	T12,T37,T39
StableSt->IdleSt	206	Covered	T12,T37,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T37,T39
0	1	Covered	T12,T37,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T37,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T37,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T37,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T37,T39
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T39,T152
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	68	0	0
CntIncr_A	8285647	56263	0	0
CntNoWrap_A	8285647	7611847	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	73846	0	0
DetectedPulseOut_A	8285647	33	0	0
DisabledIdleSt_A	8285647	7400842	0	0
DisabledNoDetection_A	8285647	7403181	0	0
EnterDebounceSt_A	8285647	35	0	0
EnterDetectSt_A	8285647	34	0	0
EnterStableSt_A	8285647	33	0	0
PulseIsPulse_A	8285647	33	0	0
StayInStableSt	8285647	73795	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	68	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	2	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T154	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	428	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56263	0	0
T12	2687	87	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	23	0	0
T39	0	54802	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	16	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	16	0	0
T151	0	23	0	0
T152	0	79	0	0
T154	0	52	0	0
T175	0	65	0	0
T176	0	35	0	0
T177	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611847	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T78	10598	1	0	0
T102	5425	0	0	0
T151	598	0	0	0
T162	1007	0	0	0
T178	429	0	0	0
T179	20441	0	0	0
T180	440	0	0	0
T181	502	0	0	0
T182	406	0	0	0
T183	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	73846	0	0
T12	2687	84	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	149	0	0
T39	0	72027	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	12	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T151	0	53	0	0
T152	0	188	0	0
T154	0	44	0	0
T175	0	44	0	0
T176	0	41	0	0
T177	428	0	0	0
T184	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	33	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7400842	0	0
T1	990	589	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7403181	0	0
T1	990	590	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	35	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	33	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	33	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	73795	0	0
T12	2687	82	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	147	0	0
T39	0	72024	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	11	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T151	0	51	0	0
T152	0	187	0	0
T154	0	43	0	0
T175	0	42	0	0
T176	0	40	0	0
T177	428	0	0	0
T184	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	13	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T39	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T152	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T176	0	1	0	0
T177	428	0	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T37,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T37
1	0	Covered	T1,T2,T13
1	1	Covered	T12,T37,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T40
0	1	Covered	T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T40
0	1	Covered	T12,T37,T40
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T40
1	-	Covered	T12,T37,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T37,T40
DetectSt	168	Covered	T12,T37,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T37,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T37,T40
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T188
DetectSt->StableSt	191	Covered	T12,T37,T40
IdleSt->DebounceSt	148	Covered	T12,T37,T40
StableSt->IdleSt	206	Covered	T12,T37,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T37,T40
0	1	Covered	T12,T37,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T37,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T37,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T37,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T37,T40
DetectSt	-	-	-	-	1	-	-	Covered	T188
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T37,T40
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	108	0	0
CntIncr_A	8285647	68553	0	0
CntNoWrap_A	8285647	7611807	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	54963	0	0
DetectedPulseOut_A	8285647	53	0	0
DisabledIdleSt_A	8285647	7289267	0	0
DisabledNoDetection_A	8285647	7291605	0	0
EnterDebounceSt_A	8285647	54	0	0
EnterDetectSt_A	8285647	54	0	0
EnterStableSt_A	8285647	53	0	0
PulseIsPulse_A	8285647	53	0	0
StayInStableSt	8285647	54886	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	3185	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	108	0	0
T12	2687	8	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	2	0	0
T40	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	4	0	0
T95	0	2	0	0
T151	0	2	0	0
T154	0	4	0	0
T155	0	2	0	0
T162	0	4	0	0
T177	428	0	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	68553	0	0
T12	2687	174	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	23	0	0
T40	0	41	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	32	0	0
T95	0	22	0	0
T151	0	23	0	0
T154	0	104	0	0
T155	0	15448	0	0
T162	0	148	0	0
T177	428	0	0	0
T189	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611807	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T188	968	1	0	0
T190	21365	0	0	0
T191	402	0	0	0
T192	918	0	0	0
T193	14107	0	0	0
T194	497	0	0	0
T195	7227	0	0	0
T196	5765	0	0	0
T197	730	0	0	0
T198	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54963	0	0
T12	2687	222	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	3	0	0
T40	0	100	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	170	0	0
T95	0	77	0	0
T151	0	89	0	0
T154	0	142	0	0
T155	0	15489	0	0
T162	0	144	0	0
T177	428	0	0	0
T189	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T95	0	1	0	0
T151	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T162	0	2	0	0
T177	428	0	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7289267	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7291605	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T95	0	1	0	0
T151	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T162	0	2	0	0
T177	428	0	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T95	0	1	0	0
T151	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T162	0	2	0	0
T177	428	0	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T95	0	1	0	0
T151	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T162	0	2	0	0
T177	428	0	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T12	2687	4	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T95	0	1	0	0
T151	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T162	0	2	0	0
T177	428	0	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54886	0	0
T12	2687	216	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	2	0	0
T40	0	99	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	167	0	0
T95	0	75	0	0
T151	0	88	0	0
T154	0	139	0	0
T155	0	15488	0	0
T162	0	141	0	0
T177	428	0	0	0
T189	0	92	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	3185	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	6	0	0
T5	36896	0	0	0
T8	0	65	0	0
T13	941	5	0	0
T14	408	0	0	0
T15	525	5	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	2	0	0
T24	0	4	0	0
T52	0	3	0	0
T53	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	27	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T172	0	2	0	0
T177	428	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T3,T15,T17
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T12
1	-	Covered	T1,T2,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T77,T160,T199
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T2,T12
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T1,T2,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T160,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	112	0	0
CntIncr_A	8285647	18348	0	0
CntNoWrap_A	8285647	7611803	0	0
DetectStDropOut_A	8285647	0	0	0
DetectedOut_A	8285647	51163	0	0
DetectedPulseOut_A	8285647	54	0	0
DisabledIdleSt_A	8285647	7417043	0	0
DisabledNoDetection_A	8285647	7419375	0	0
EnterDebounceSt_A	8285647	58	0	0
EnterDetectSt_A	8285647	54	0	0
EnterStableSt_A	8285647	54	0	0
PulseIsPulse_A	8285647	54	0	0
StayInStableSt	8285647	51080	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	112	0	0
T1	990	6	0	0
T2	669	2	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T77	0	1	0	0
T78	0	4	0	0
T95	0	2	0	0
T153	0	2	0	0
T155	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	18348	0	0
T1	990	177	0	0
T2	669	34	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	28	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T77	0	43	0	0
T78	0	32	0	0
T95	0	22	0	0
T153	0	47	0	0
T155	0	15448	0	0
T200	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611803	0	0
T1	990	583	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	51163	0	0
T1	990	196	0	0
T2	669	152	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	176	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	150	0	0
T78	0	111	0	0
T95	0	14	0	0
T153	0	39	0	0
T155	0	45472	0	0
T200	0	41	0	0
T201	0	137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T78	0	2	0	0
T95	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7417043	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7419375	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	58	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T95	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T78	0	2	0	0
T95	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T78	0	2	0	0
T95	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T1	990	3	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T78	0	2	0	0
T95	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	51080	0	0
T1	990	192	0	0
T2	669	151	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	175	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	148	0	0
T78	0	108	0	0
T95	0	13	0	0
T153	0	38	0	0
T155	0	45470	0	0
T200	0	39	0	0
T201	0	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	23	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T78	0	1	0	0
T95	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T161	0	1	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T12,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T12
1	0	Covered	T1,T3,T15
1	1	Covered	T2,T12,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T38,T39
0	1	Covered	T78,T152,T160
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T38,T39
1	-	Covered	T78,T152,T160

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T38
DetectSt	168	Covered	T2,T38,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T38,T39
DebounceSt->IdleSt	163	Covered	T12,T174
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T38,T39
IdleSt->DebounceSt	148	Covered	T2,T12,T38
StableSt->IdleSt	206	Covered	T38,T78,T152

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T38
0	1	Covered	T2,T12,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T38,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T12
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T78,T152,T57
StableSt	-	-	-	-	-	-	0	Covered	T2,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	69	0	0
CntIncr_A	8285647	39715	0	0
CntNoWrap_A	8285647	7611846	0	0
DetectStDropOut_A	8285647	0	0	0
DetectedOut_A	8285647	85815	0	0
DetectedPulseOut_A	8285647	34	0	0
DisabledIdleSt_A	8285647	7270248	0	0
DisabledNoDetection_A	8285647	7272588	0	0
EnterDebounceSt_A	8285647	36	0	0
EnterDetectSt_A	8285647	34	0	0
EnterStableSt_A	8285647	34	0	0
PulseIsPulse_A	8285647	34	0	0
StayInStableSt	8285647	85762	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6760	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	69	0	0
T2	669	2	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T52	441	0	0	0
T57	0	2	0	0
T78	0	2	0	0
T152	0	2	0	0
T154	0	2	0	0
T160	0	2	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	39715	0	0
T2	669	34	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	59	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	55	0	0
T39	0	27401	0	0
T52	441	0	0	0
T57	0	16	0	0
T78	0	16	0	0
T152	0	79	0	0
T154	0	52	0	0
T160	0	32	0	0
T172	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611846	0	0
T1	990	589	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	85815	0	0
T2	669	39	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	40	0	0
T39	0	82202	0	0
T52	441	0	0	0
T57	0	13	0	0
T78	0	59	0	0
T152	0	44	0	0
T154	0	144	0	0
T160	0	40	0	0
T172	0	113	0	0
T202	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T78	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T172	0	2	0	0
T202	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7270248	0	0
T1	990	589	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7272588	0	0
T1	990	590	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	36	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T78	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T78	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T172	0	2	0	0
T202	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T78	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T172	0	2	0	0
T202	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T78	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T172	0	2	0	0
T202	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	85762	0	0
T2	669	37	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	38	0	0
T39	0	82200	0	0
T52	441	0	0	0
T57	0	12	0	0
T78	0	58	0	0
T152	0	43	0	0
T154	0	142	0	0
T160	0	39	0	0
T172	0	110	0	0
T202	0	170	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6760	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	8	0	0
T5	36896	0	0	0
T6	0	8	0	0
T7	0	12	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	5	0	0
T16	624	0	0	0
T17	4766	27	0	0
T18	422	2	0	0
T52	0	4	0	0
T53	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	13	0	0
T78	10598	1	0	0
T102	5425	0	0	0
T151	598	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T162	1007	0	0	0
T172	0	1	0	0
T178	429	0	0	0
T179	20441	0	0	0
T180	440	0	0	0
T181	502	0	0	0
T182	406	0	0	0
T183	526	0	0	0
T199	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T3,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T8,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T8,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T8,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T3,T15,T17
1	1	Covered	T1,T8,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T37
0	1	Covered	T90,T207,T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T37
0	1	Covered	T1,T37,T38
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T37
1	-	Covered	T1,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T37
DetectSt	168	Covered	T1,T8,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T8,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T37
DebounceSt->IdleSt	163	Covered	T39,T77,T107
DetectSt->IdleSt	186	Covered	T90,T207,T208
DetectSt->StableSt	191	Covered	T1,T8,T37
IdleSt->DebounceSt	148	Covered	T1,T8,T37
StableSt->IdleSt	206	Covered	T1,T8,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T37
0	1	Covered	T1,T8,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T77,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T37
DetectSt	-	-	-	-	1	-	-	Covered	T90,T207,T208
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	143	0	0
CntIncr_A	8285647	135219	0	0
CntNoWrap_A	8285647	7611772	0	0
DetectStDropOut_A	8285647	3	0	0
DetectedOut_A	8285647	197583	0	0
DetectedPulseOut_A	8285647	67	0	0
DisabledIdleSt_A	8285647	7156319	0	0
DisabledNoDetection_A	8285647	7158645	0	0
EnterDebounceSt_A	8285647	73	0	0
EnterDetectSt_A	8285647	70	0	0
EnterStableSt_A	8285647	67	0	0
PulseIsPulse_A	8285647	67	0	0
StayInStableSt	8285647	197486	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	143	0	0
T1	990	2	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	3	0	0
T40	0	2	0	0
T77	0	1	0	0
T151	0	2	0	0
T152	0	4	0	0
T154	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	135219	0	0
T1	990	59	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	28	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T38	0	23	0	0
T39	0	54802	0	0
T40	0	41	0	0
T77	0	43	0	0
T151	0	23	0	0
T152	0	158	0	0
T154	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611772	0	0
T1	990	587	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	3	0	0
T90	706	1	0	0
T129	1117	0	0	0
T199	196120	0	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	523	0	0	0
T210	596	0	0	0
T211	422	0	0	0
T212	36984	0	0	0
T213	521	0	0	0
T214	873	0	0	0
T215	739	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	197583	0	0
T1	990	128	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	76	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	3	0	0
T38	0	14	0	0
T39	0	27316	0	0
T40	0	193	0	0
T151	0	166	0	0
T152	0	232	0	0
T154	0	243	0	0
T189	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	67	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T154	0	2	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7156319	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7158645	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	73	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T77	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T154	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	70	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T154	0	2	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	67	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T154	0	2	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	67	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T154	0	2	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	197486	0	0
T1	990	127	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	74	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T38	0	13	0	0
T39	0	27315	0	0
T40	0	191	0	0
T151	0	164	0	0
T152	0	229	0	0
T154	0	240	0	0
T189	0	92	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	35	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T95	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T202	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T37,T38
1	0	Covered	T1,T3,T15
1	1	Covered	T12,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T38
0	1	Covered	T216
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T38
0	1	Covered	T12,T39,T78
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T38
1	-	Covered	T12,T39,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T37,T38
DetectSt	168	Covered	T12,T37,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T37,T38
DebounceSt->IdleSt	163	Covered	T149
DetectSt->IdleSt	186	Covered	T216
DetectSt->StableSt	191	Covered	T12,T37,T38
IdleSt->DebounceSt	148	Covered	T12,T37,T38
StableSt->IdleSt	206	Covered	T12,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T37,T38
0	1	Covered	T12,T37,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T37,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T37,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T216
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T39,T78
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	92	0	0
CntIncr_A	8285647	78272	0	0
CntNoWrap_A	8285647	7611823	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	87159	0	0
DetectedPulseOut_A	8285647	45	0	0
DisabledIdleSt_A	8285647	7229714	0	0
DisabledNoDetection_A	8285647	7232039	0	0
EnterDebounceSt_A	8285647	47	0	0
EnterDetectSt_A	8285647	46	0	0
EnterStableSt_A	8285647	45	0	0
PulseIsPulse_A	8285647	45	0	0
StayInStableSt	8285647	87090	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6137	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	92	0	0
T12	2687	2	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	2	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	2	0	0
T152	0	2	0	0
T162	0	2	0	0
T175	0	2	0	0
T177	428	0	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	78272	0	0
T12	2687	28	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	23	0	0
T38	0	78	0	0
T39	0	54802	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	16	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	16	0	0
T149	0	7	0	0
T152	0	79	0	0
T162	0	74	0	0
T175	0	65	0	0
T177	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611823	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T216	14102	1	0	0
T218	544	0	0	0
T219	745	0	0	0
T220	495	0	0	0
T221	514	0	0	0
T222	526	0	0	0
T223	10374	0	0	0
T224	693	0	0	0
T225	756	0	0	0
T226	5325	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	87159	0	0
T12	2687	118	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	149	0	0
T38	0	88	0	0
T39	0	72199	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	12	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	60	0	0
T152	0	66	0	0
T162	0	136	0	0
T175	0	44	0	0
T177	428	0	0	0
T217	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	45	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T175	0	1	0	0
T177	428	0	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7229714	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7232039	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	47	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T175	0	1	0	0
T177	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	46	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T175	0	1	0	0
T177	428	0	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	45	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T175	0	1	0	0
T177	428	0	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	45	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	1	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T175	0	1	0	0
T177	428	0	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	87090	0	0
T12	2687	117	0	0
T27	477	0	0	0
T28	5116	0	0	0
T37	0	147	0	0
T38	0	84	0	0
T39	0	72196	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T57	0	11	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	59	0	0
T152	0	65	0	0
T162	0	135	0	0
T175	0	42	0	0
T177	428	0	0	0
T217	0	123	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6137	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	5	0	0
T5	36896	0	0	0
T7	0	14	0	0
T8	0	48	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	4	0	0
T16	624	0	0	0
T17	4766	24	0	0
T18	422	3	0	0
T26	0	25	0	0
T52	0	4	0	0
T53	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	19	0	0
T12	2687	1	0	0
T27	477	0	0	0
T28	5116	0	0	0
T39	0	1	0	0
T44	10958	0	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T78	0	1	0	0
T90	0	2	0	0
T152	0	1	0	0
T156	0	1	0	0
T162	0	1	0	0
T172	0	1	0	0
T177	428	0	0	0
T202	0	1	0	0
T227	0	2	0	0