Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T12
1	0	Covered	T1,T3,T15
1	1	Covered	T2,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T12
0	1	Covered	T228
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T12
0	1	Covered	T2,T8,T38
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T12
1	-	Covered	T2,T8,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T12
DetectSt	168	Covered	T2,T8,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T12
DebounceSt->IdleSt	163	Covered	T12,T156,T202
DetectSt->IdleSt	186	Covered	T228
DetectSt->StableSt	191	Covered	T2,T8,T12
IdleSt->DebounceSt	148	Covered	T2,T8,T12
StableSt->IdleSt	206	Covered	T2,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T12
0	1	Covered	T2,T8,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T156,T202
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T228
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	124	0	0
CntIncr_A	8285647	53832	0	0
CntNoWrap_A	8285647	7611791	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	28286	0	0
DetectedPulseOut_A	8285647	59	0	0
DisabledIdleSt_A	8285647	7364211	0	0
DisabledNoDetection_A	8285647	7366547	0	0
EnterDebounceSt_A	8285647	65	0	0
EnterDetectSt_A	8285647	60	0	0
EnterStableSt_A	8285647	59	0	0
PulseIsPulse_A	8285647	59	0	0
StayInStableSt	8285647	28193	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124	0	0
T2	669	2	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	2	0	0
T12	0	5	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T52	441	0	0	0
T77	0	2	0	0
T78	0	4	0	0
T151	0	2	0	0
T153	0	2	0	0
T175	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53832	0	0
T2	669	34	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	28	0	0
T12	0	115	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	55	0	0
T52	441	0	0	0
T77	0	43	0	0
T78	0	32	0	0
T151	0	23	0	0
T153	0	47	0	0
T175	0	65	0	0
T201	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611791	0	0
T1	990	589	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T228	735	1	0	0
T229	18078	0	0	0
T230	492	0	0	0
T231	536	0	0	0
T232	1321	0	0	0
T233	446	0	0	0
T234	1864	0	0	0
T235	15199	0	0	0
T236	681	0	0	0
T237	444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	28286	0	0
T2	669	85	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	7	0	0
T12	0	254	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	43	0	0
T52	441	0	0	0
T77	0	43	0	0
T78	0	96	0	0
T151	0	119	0	0
T153	0	127	0	0
T175	0	44	0	0
T201	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7364211	0	0
T1	990	589	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7366547	0	0
T1	990	590	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	65	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T12	0	3	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	60	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T175	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	28193	0	0
T2	669	84	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	6	0	0
T12	0	250	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	42	0	0
T52	441	0	0	0
T77	0	41	0	0
T78	0	94	0	0
T151	0	117	0	0
T153	0	125	0	0
T175	0	42	0	0
T201	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	23	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T8	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T52	441	0	0	0
T78	0	2	0	0
T90	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T203	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T12,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T12,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T12,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T37
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T12,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T37
0	1	Covered	T78,T216
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T37
0	1	Covered	T1,T12,T154
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T37
1	-	Covered	T1,T12,T154

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T37
DetectSt	168	Covered	T1,T12,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T12,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T37
DebounceSt->IdleSt	163	Covered	T149,T172,T235
DetectSt->IdleSt	186	Covered	T78,T216
DetectSt->StableSt	191	Covered	T1,T12,T37
IdleSt->DebounceSt	148	Covered	T1,T12,T37
StableSt->IdleSt	206	Covered	T1,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T37
0	1	Covered	T1,T12,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T37
DetectSt	-	-	-	-	1	-	-	Covered	T78,T216
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T154
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	74	0	0
CntIncr_A	8285647	29280	0	0
CntNoWrap_A	8285647	7611841	0	0
DetectStDropOut_A	8285647	2	0	0
DetectedOut_A	8285647	129768	0	0
DetectedPulseOut_A	8285647	34	0	0
DisabledIdleSt_A	8285647	7321984	0	0
DisabledNoDetection_A	8285647	7324317	0	0
EnterDebounceSt_A	8285647	39	0	0
EnterDetectSt_A	8285647	36	0	0
EnterStableSt_A	8285647	34	0	0
PulseIsPulse_A	8285647	34	0	0
StayInStableSt	8285647	129716	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6246	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	74	0	0
T1	990	2	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T57	0	2	0	0
T78	0	4	0	0
T154	0	4	0	0
T160	0	2	0	0
T172	0	3	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	29280	0	0
T1	990	59	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	28	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T39	0	27401	0	0
T57	0	16	0	0
T78	0	32	0	0
T149	0	8	0	0
T154	0	104	0	0
T160	0	32	0	0
T217	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611841	0	0
T1	990	587	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2	0	0
T78	10598	1	0	0
T102	5425	0	0	0
T151	598	0	0	0
T162	1007	0	0	0
T178	429	0	0	0
T179	20441	0	0	0
T180	440	0	0	0
T181	502	0	0	0
T182	406	0	0	0
T183	526	0	0	0
T216	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	129768	0	0
T1	990	24	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	43	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	41	0	0
T39	0	126874	0	0
T57	0	13	0	0
T78	0	66	0	0
T154	0	240	0	0
T160	0	74	0	0
T172	0	182	0	0
T217	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T78	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T172	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7321984	0	0
T1	990	3	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7324317	0	0
T1	990	3	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	39	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T78	0	2	0	0
T149	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	36	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T78	0	2	0	0
T154	0	2	0	0
T160	0	1	0	0
T172	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T78	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T172	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	34	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T78	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T172	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	129716	0	0
T1	990	23	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	42	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	39	0	0
T39	0	126872	0	0
T57	0	12	0	0
T78	0	64	0	0
T154	0	237	0	0
T160	0	73	0	0
T172	0	180	0	0
T217	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6246	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	4	0	0
T5	36896	0	0	0
T7	0	11	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	4	0	0
T16	624	0	0	0
T17	4766	22	0	0
T18	422	2	0	0
T26	0	25	0	0
T52	0	7	0	0
T53	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	14	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T185	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T217	0	1	0	0
T240	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T3,T15,T17
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T241
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T37
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T200,T217,T156
DetectSt->IdleSt	186	Covered	T241
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T200,T217,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T241
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T37
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	115	0	0
CntIncr_A	8285647	57976	0	0
CntNoWrap_A	8285647	7611800	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	82103	0	0
DetectedPulseOut_A	8285647	55	0	0
DisabledIdleSt_A	8285647	7418795	0	0
DisabledNoDetection_A	8285647	7421134	0	0
EnterDebounceSt_A	8285647	59	0	0
EnterDetectSt_A	8285647	56	0	0
EnterStableSt_A	8285647	55	0	0
PulseIsPulse_A	8285647	55	0	0
StayInStableSt	8285647	82021	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	115	0	0
T1	990	4	0	0
T2	669	2	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	2	0	0
T12	0	4	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	57976	0	0
T1	990	118	0	0
T2	669	34	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	28	0	0
T12	0	87	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T38	0	46	0	0
T151	0	23	0	0
T152	0	158	0	0
T153	0	47	0	0
T155	0	15448	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611800	0	0
T1	990	585	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T204	684	0	0	0
T241	578	1	0	0
T242	405	0	0	0
T243	4170	0	0	0
T244	711	0	0	0
T245	719	0	0	0
T246	963	0	0	0
T247	15632	0	0	0
T248	431	0	0	0
T249	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	82103	0	0
T1	990	72	0	0
T2	669	86	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	39	0	0
T12	0	313	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	86	0	0
T38	0	195	0	0
T151	0	166	0	0
T152	0	82	0	0
T153	0	127	0	0
T155	0	15489	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	55	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7418795	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7421134	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	59	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	55	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	55	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	1	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	82021	0	0
T1	990	69	0	0
T2	669	85	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T8	0	37	0	0
T12	0	309	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	85	0	0
T38	0	192	0	0
T151	0	164	0	0
T152	0	79	0	0
T153	0	125	0	0
T155	0	15488	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	26	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T95	0	1	0	0
T152	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T3,T15,T17
1	1	Covered	T1,T2,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T37
0	1	Covered	T216
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T37
0	1	Covered	T1,T38,T39
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T37
1	-	Covered	T1,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T37
DetectSt	168	Covered	T1,T2,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T37
DebounceSt->IdleSt	163	Covered	T172,T150
DetectSt->IdleSt	186	Covered	T216
DetectSt->StableSt	191	Covered	T1,T2,T37
IdleSt->DebounceSt	148	Covered	T1,T2,T37
StableSt->IdleSt	206	Covered	T1,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T37
0	1	Covered	T1,T2,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T37
DetectSt	-	-	-	-	1	-	-	Covered	T216
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	69	0	0
CntIncr_A	8285647	66899	0	0
CntNoWrap_A	8285647	7611846	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	124441	0	0
DetectedPulseOut_A	8285647	32	0	0
DisabledIdleSt_A	8285647	7269229	0	0
DisabledNoDetection_A	8285647	7271562	0	0
EnterDebounceSt_A	8285647	36	0	0
EnterDetectSt_A	8285647	33	0	0
EnterStableSt_A	8285647	32	0	0
PulseIsPulse_A	8285647	32	0	0
StayInStableSt	8285647	124395	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6147	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	69	0	0
T1	990	2	0	0
T2	669	2	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T57	0	2	0	0
T154	0	4	0	0
T160	0	2	0	0
T162	0	4	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	66899	0	0
T1	990	59	0	0
T2	669	34	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T38	0	23	0	0
T39	0	54802	0	0
T57	0	16	0	0
T154	0	104	0	0
T160	0	32	0	0
T162	0	148	0	0
T176	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611846	0	0
T1	990	587	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T216	14102	1	0	0
T218	544	0	0	0
T219	745	0	0	0
T220	495	0	0	0
T221	514	0	0	0
T222	526	0	0	0
T223	10374	0	0	0
T224	693	0	0	0
T225	756	0	0	0
T226	5325	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124441	0	0
T1	990	134	0	0
T2	669	105	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	40	0	0
T38	0	15	0	0
T39	0	99473	0	0
T57	0	13	0	0
T154	0	281	0	0
T160	0	71	0	0
T162	0	277	0	0
T176	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	32	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T57	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7269229	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7271562	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	36	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T57	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	33	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T57	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	32	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T57	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	32	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T57	0	1	0	0
T154	0	2	0	0
T160	0	1	0	0
T162	0	2	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	124395	0	0
T1	990	133	0	0
T2	669	103	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	38	0	0
T38	0	14	0	0
T39	0	99470	0	0
T57	0	12	0	0
T154	0	278	0	0
T160	0	69	0	0
T162	0	274	0	0
T176	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6147	0	0
T1	990	1	0	0
T2	669	1	0	0
T3	2393	4	0	0
T5	36896	0	0	0
T7	0	12	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	6	0	0
T16	624	0	0	0
T17	4766	27	0	0
T18	422	2	0	0
T26	0	22	0	0
T52	0	2	0	0
T53	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	16	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T90	0	1	0	0
T154	0	1	0	0
T162	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0
T227	0	2	0	0
T250	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T12,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T12,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T37
1	0	Covered	T1,T5,T3
1	1	Covered	T2,T12,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T37
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T37
0	1	Covered	T2,T37,T39
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T37
1	-	Covered	T2,T37,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T12,T37
DetectSt	168	Covered	T2,T12,T37
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T12,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T12,T37
DebounceSt->IdleSt	163	Covered	T77,T199,T241
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T2,T12,T37
IdleSt->DebounceSt	148	Covered	T2,T12,T37
StableSt->IdleSt	206	Covered	T2,T37,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T12,T37
0	1	Covered	T2,T12,T37
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T37
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T12,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T12,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T199,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T12,T37
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T12,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T37,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	115	0	0
CntIncr_A	8285647	97455	0	0
CntNoWrap_A	8285647	7611800	0	0
DetectStDropOut_A	8285647	1	0	0
DetectedOut_A	8285647	46317	0	0
DetectedPulseOut_A	8285647	53	0	0
DisabledIdleSt_A	8285647	7299389	0	0
DisabledNoDetection_A	8285647	7301723	0	0
EnterDebounceSt_A	8285647	61	0	0
EnterDetectSt_A	8285647	54	0	0
EnterStableSt_A	8285647	53	0	0
PulseIsPulse_A	8285647	53	0	0
StayInStableSt	8285647	46245	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	115	0	0
T2	669	2	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T52	441	0	0	0
T57	0	2	0	0
T77	0	1	0	0
T163	0	4	0	0
T189	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	97455	0	0
T2	669	34	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	59	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T39	0	54802	0	0
T40	0	41	0	0
T52	441	0	0	0
T57	0	16	0	0
T77	0	43	0	0
T163	0	20	0	0
T189	0	51	0	0
T201	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611800	0	0
T1	990	589	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1	0	0
T91	501	1	0	0
T138	1404	0	0	0
T164	416	0	0	0
T165	522	0	0	0
T166	498	0	0	0
T167	504	0	0	0
T168	89134	0	0	0
T169	149485	0	0	0
T170	428	0	0	0
T171	688	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	46317	0	0
T2	669	107	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	88	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	70	0	0
T39	0	41542	0	0
T40	0	40	0	0
T52	441	0	0	0
T57	0	13	0	0
T163	0	97	0	0
T176	0	22	0	0
T189	0	1	0	0
T201	0	137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0
T189	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7299389	0	0
T1	990	589	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7301723	0	0
T1	990	590	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	61	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T77	0	1	0	0
T163	0	2	0	0
T189	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	54	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0
T189	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0
T189	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	53	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T57	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0
T189	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	46245	0	0
T2	669	106	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T12	0	86	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	69	0	0
T39	0	41540	0	0
T40	0	39	0	0
T52	441	0	0	0
T57	0	12	0	0
T163	0	94	0	0
T176	0	21	0	0
T184	0	4	0	0
T201	0	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	32	0	0
T2	669	1	0	0
T3	2393	0	0	0
T6	1307	0	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	441	0	0	0
T163	0	1	0	0
T176	0	1	0	0
T184	0	1	0	0
T189	0	1	0	0
T202	0	3	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T5,T3,T15
1	1	Covered	T1,T2,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T12,T38
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T12
1	-	Covered	T1,T12,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T12
DetectSt	168	Covered	T1,T2,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T12
DebounceSt->IdleSt	163	Covered	T151,T202,T251
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T2,T12
IdleSt->DebounceSt	148	Covered	T1,T2,T12
StableSt->IdleSt	206	Covered	T1,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T202,T251
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	88	0	0
CntIncr_A	8285647	56770	0	0
CntNoWrap_A	8285647	7611827	0	0
DetectStDropOut_A	8285647	0	0	0
DetectedOut_A	8285647	47537	0	0
DetectedPulseOut_A	8285647	42	0	0
DisabledIdleSt_A	8285647	7233532	0	0
DisabledNoDetection_A	8285647	7235865	0	0
EnterDebounceSt_A	8285647	46	0	0
EnterDetectSt_A	8285647	42	0	0
EnterStableSt_A	8285647	42	0	0
PulseIsPulse_A	8285647	42	0	0
StayInStableSt	8285647	47473	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8285647	6881	0	0
gen_low_level_sva.LowLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	88	0	0
T1	990	4	0	0
T2	669	2	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	2	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T78	0	4	0	0
T151	0	1	0	0
T152	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	56770	0	0
T1	990	118	0	0
T2	669	34	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	28	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	23	0	0
T38	0	46	0	0
T39	0	54802	0	0
T40	0	41	0	0
T78	0	32	0	0
T151	0	23	0	0
T152	0	158	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611827	0	0
T1	990	585	0	0
T2	669	266	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	47537	0	0
T1	990	276	0	0
T2	669	38	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	44	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	82	0	0
T38	0	122	0	0
T39	0	44754	0	0
T40	0	51	0	0
T78	0	85	0	0
T152	0	82	0	0
T163	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	42	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	2	0	0
T152	0	2	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7233532	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7235865	0	0
T1	990	3	0	0
T2	669	3	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	46	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	42	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	2	0	0
T152	0	2	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	42	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	2	0	0
T152	0	2	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	42	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	2	0	0
T152	0	2	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	47473	0	0
T1	990	273	0	0
T2	669	36	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	43	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T37	0	80	0	0
T38	0	120	0	0
T39	0	44751	0	0
T40	0	49	0	0
T78	0	83	0	0
T152	0	79	0	0
T163	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	6881	0	0
T1	990	2	0	0
T2	669	1	0	0
T3	2393	10	0	0
T5	36896	3	0	0
T6	0	8	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	5	0	0
T16	624	3	0	0
T17	4766	21	0	0
T18	422	3	0	0
T52	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	18	0	0
T1	990	1	0	0
T2	669	0	0	0
T3	2393	0	0	0
T5	36896	0	0	0
T12	0	1	0	0
T13	941	0	0	0
T14	408	0	0	0
T15	525	0	0	0
T16	624	0	0	0
T17	4766	0	0	0
T18	422	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T78	0	2	0	0
T152	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T202	0	1	0	0
T227	0	1	0	0