Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T26,T28
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T41,T42
1	1	Covered	T17,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T26,T27
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T97,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T41,T42
0	1	Covered	T41,T42,T35
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T41,T42
1	-	Covered	T41,T42,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T26,T27
DetectSt	168	Covered	T17,T26,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T26,T27
DebounceSt->IdleSt	163	Covered	T57,T116,T58
DetectSt->IdleSt	186	Covered	T17,T26,T28
DetectSt->StableSt	191	Covered	T27,T41,T42
IdleSt->DebounceSt	148	Covered	T17,T26,T27
StableSt->IdleSt	206	Covered	T41,T42,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T26,T27
0	1	Covered	T17,T26,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T26,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T17,T26,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T116,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	0	1	-	Covered	T27,T41,T42
DetectSt	-	-	-	-	0	0	-	Covered	T17,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T35
StableSt	-	-	-	-	-	-	0	Covered	T27,T41,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	2797	0	0
CntIncr_A	8285647	102080	0	0
CntNoWrap_A	8285647	7609118	0	0
DetectStDropOut_A	8285647	409	0	0
DetectedOut_A	8285647	113334	0	0
DetectedPulseOut_A	8285647	913	0	0
DisabledIdleSt_A	8285647	7120875	0	0
DisabledNoDetection_A	8285647	7123015	0	0
EnterDebounceSt_A	8285647	1403	0	0
EnterDetectSt_A	8285647	1394	0	0
EnterStableSt_A	8285647	913	0	0
PulseIsPulse_A	8285647	913	0	0
StayInStableSt	8285647	112254	0	0
gen_high_event_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	745	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2797	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	54	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	50	0	0
T27	0	2	0	0
T28	0	28	0	0
T35	0	36	0	0
T41	0	64	0	0
T42	0	26	0	0
T44	0	12	0	0
T45	0	52	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	102080	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	1156	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	1276	0	0
T27	0	21	0	0
T28	0	693	0	0
T35	0	1134	0	0
T41	0	2656	0	0
T42	0	767	0	0
T44	0	335	0	0
T45	0	1560	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	476	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7609118	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4311	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	409	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	27	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	14	0	0
T44	0	3	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	12	0	0
T97	0	2	0	0
T101	0	14	0	0
T103	0	12	0	0
T147	0	30	0	0
T252	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	113334	0	0
T27	477	51	0	0
T28	5116	0	0	0
T33	0	785	0	0
T35	0	2309	0	0
T36	0	1246	0	0
T37	2453	0	0	0
T41	0	1594	0	0
T42	0	1802	0	0
T44	10958	0	0	0
T45	0	2379	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T123	0	30	0	0
T125	0	526	0	0
T177	428	0	0	0
T253	0	1540	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	913	0	0
T27	477	1	0	0
T28	5116	0	0	0
T33	0	11	0	0
T35	0	18	0	0
T36	0	10	0	0
T37	2453	0	0	0
T41	0	32	0	0
T42	0	13	0	0
T44	10958	0	0	0
T45	0	26	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T123	0	1	0	0
T125	0	15	0	0
T177	428	0	0	0
T253	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7120875	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7123015	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1403	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	27	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T27	0	1	0	0
T28	0	14	0	0
T35	0	18	0	0
T41	0	32	0	0
T42	0	13	0	0
T44	0	6	0	0
T45	0	26	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1394	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	27	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T27	0	1	0	0
T28	0	14	0	0
T35	0	18	0	0
T41	0	32	0	0
T42	0	13	0	0
T44	0	6	0	0
T45	0	26	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	913	0	0
T27	477	1	0	0
T28	5116	0	0	0
T33	0	11	0	0
T35	0	18	0	0
T36	0	10	0	0
T37	2453	0	0	0
T41	0	32	0	0
T42	0	13	0	0
T44	10958	0	0	0
T45	0	26	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T123	0	1	0	0
T125	0	15	0	0
T177	428	0	0	0
T253	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	913	0	0
T27	477	1	0	0
T28	5116	0	0	0
T33	0	11	0	0
T35	0	18	0	0
T36	0	10	0	0
T37	2453	0	0	0
T41	0	32	0	0
T42	0	13	0	0
T44	10958	0	0	0
T45	0	26	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T123	0	1	0	0
T125	0	15	0	0
T177	428	0	0	0
T253	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	112254	0	0
T27	477	49	0	0
T28	5116	0	0	0
T33	0	772	0	0
T35	0	2286	0	0
T36	0	1234	0	0
T37	2453	0	0	0
T41	0	1562	0	0
T42	0	1786	0	0
T44	10958	0	0	0
T45	0	2346	0	0
T46	637	0	0	0
T47	601	0	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T123	0	28	0	0
T125	0	510	0	0
T177	428	0	0	0
T253	0	1516	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	745	0	0
T32	9130	0	0	0
T33	0	9	0	0
T35	22832	13	0	0
T36	0	8	0	0
T41	8503	32	0	0
T42	14810	10	0	0
T45	0	19	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	14	0	0
T253	0	24	0	0
T254	0	14	0	0
T255	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T7,T26
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T7,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T10
1	0	Covered	T3,T17,T7
1	1	Covered	T7,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T32,T34,T98
1	0	Covered	T57,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T10
1	-	Covered	T7,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T10
DetectSt	168	Covered	T7,T8,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T10
DebounceSt->IdleSt	163	Covered	T12,T27,T43
DetectSt->IdleSt	186	Covered	T32,T34,T98
DetectSt->StableSt	191	Covered	T7,T8,T10
IdleSt->DebounceSt	148	Covered	T7,T8,T10
StableSt->IdleSt	206	Covered	T7,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T27,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T32,T34,T98
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	1135	0	0
CntIncr_A	8285647	60214	0	0
CntNoWrap_A	8285647	7610780	0	0
DetectStDropOut_A	8285647	65	0	0
DetectedOut_A	8285647	20037	0	0
DetectedPulseOut_A	8285647	454	0	0
DisabledIdleSt_A	8285647	7179327	0	0
DisabledNoDetection_A	8285647	7180927	0	0
EnterDebounceSt_A	8285647	616	0	0
EnterDetectSt_A	8285647	524	0	0
EnterStableSt_A	8285647	454	0	0
PulseIsPulse_A	8285647	454	0	0
StayInStableSt	8285647	19534	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	404	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1135	0	0
T7	20110	2	0	0
T8	15300	4	0	0
T10	0	2	0	0
T12	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T27	0	1	0	0
T32	0	16	0	0
T35	0	9	0	0
T41	0	2	0	0
T42	0	6	0	0
T43	0	5	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	60214	0	0
T7	20110	105	0	0
T8	15300	50	0	0
T10	0	25	0	0
T12	0	20	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T27	0	20	0	0
T32	0	741	0	0
T35	0	424	0	0
T41	0	72	0	0
T42	0	243	0	0
T43	0	316	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7610780	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	65	0	0
T32	9130	8	0	0
T34	0	1	0	0
T57	0	1	0	0
T67	492	0	0	0
T76	523	0	0	0
T98	0	5	0	0
T99	0	9	0	0
T100	0	1	0	0
T102	0	1	0	0
T104	0	9	0	0
T105	0	1	0	0
T106	0	5	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T111	522	0	0	0
T112	503	0	0	0
T113	402	0	0	0
T114	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	20037	0	0
T7	20110	34	0	0
T8	15300	6	0	0
T10	0	3	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	89	0	0
T35	0	222	0	0
T36	0	166	0	0
T41	0	62	0	0
T42	0	263	0	0
T43	0	10	0	0
T45	0	313	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	454	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7179327	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7180927	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	616	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T12	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T27	0	1	0	0
T32	0	8	0	0
T35	0	5	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	524	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	8	0	0
T34	0	1	0	0
T35	0	4	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	454	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	454	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	19534	0	0
T7	20110	33	0	0
T8	15300	4	0	0
T10	0	2	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	88	0	0
T35	0	218	0	0
T36	0	162	0	0
T41	0	61	0	0
T42	0	260	0	0
T43	0	8	0	0
T45	0	307	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	404	0	0
T7	20110	1	0	0
T8	15300	2	0	0
T10	0	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T33	0	1	0	0
T35	0	4	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T26,T28
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T41,T42
1	1	Covered	T17,T26,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T41,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T36,T33
0	1	Covered	T42,T36,T33
1	0	Covered	T41,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T42,T36
1	-	Covered	T42,T36,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T26,T28
DetectSt	168	Covered	T17,T26,T28
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T41,T42,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T26,T28
DebounceSt->IdleSt	163	Covered	T57,T116,T58
DetectSt->IdleSt	186	Covered	T17,T26,T28
DetectSt->StableSt	191	Covered	T41,T42,T36
IdleSt->DebounceSt	148	Covered	T17,T26,T28
StableSt->IdleSt	206	Covered	T41,T42,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T26,T28
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T26,T28
IdleSt	0	-	-	-	-	-	-	Covered	T17,T26,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T26,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T116,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T36
DetectSt	-	-	-	-	0	0	-	Covered	T17,T26,T28
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T36
StableSt	-	-	-	-	-	-	0	Covered	T42,T36,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	2883	0	0
CntIncr_A	8285647	111880	0	0
CntNoWrap_A	8285647	7609032	0	0
DetectStDropOut_A	8285647	471	0	0
DetectedOut_A	8285647	77848	0	0
DetectedPulseOut_A	8285647	677	0	0
DisabledIdleSt_A	8285647	7154567	0	0
DisabledNoDetection_A	8285647	7156770	0	0
EnterDebounceSt_A	8285647	1447	0	0
EnterDetectSt_A	8285647	1436	0	0
EnterStableSt_A	8285647	677	0	0
PulseIsPulse_A	8285647	677	0	0
StayInStableSt	8285647	77067	0	0
gen_high_event_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	561	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2883	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	8	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	50	0	0
T28	0	28	0	0
T35	0	56	0	0
T36	0	56	0	0
T41	0	56	0	0
T42	0	46	0	0
T44	0	28	0	0
T45	0	22	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	111880	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	170	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	1275	0	0
T28	0	692	0	0
T35	0	1858	0	0
T36	0	1316	0	0
T41	0	2462	0	0
T42	0	1518	0	0
T44	0	784	0	0
T45	0	790	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	876	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7609032	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4357	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	471	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	4	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	14	0	0
T35	0	14	0	0
T44	0	9	0	0
T45	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	22	0	0
T147	0	8	0	0
T252	0	14	0	0
T256	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77848	0	0
T32	9130	0	0	0
T33	0	3426	0	0
T35	22832	0	0	0
T36	0	925	0	0
T41	8503	11	0	0
T42	14810	2353	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	285	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	2353	0	0
T179	0	2205	0	0
T253	0	178	0	0
T255	0	3366	0	0
T257	0	1064	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	677	0	0
T32	9130	0	0	0
T33	0	23	0	0
T35	22832	0	0	0
T36	0	28	0	0
T41	8503	11	0	0
T42	14810	23	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	5	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	29	0	0
T179	0	14	0	0
T253	0	6	0	0
T255	0	28	0	0
T257	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7154567	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7156770	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1447	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	4	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	14	0	0
T35	0	28	0	0
T36	0	28	0	0
T41	0	28	0	0
T42	0	23	0	0
T44	0	14	0	0
T45	0	11	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1436	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	4	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	14	0	0
T35	0	28	0	0
T36	0	28	0	0
T41	0	28	0	0
T42	0	23	0	0
T44	0	14	0	0
T45	0	11	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	677	0	0
T32	9130	0	0	0
T33	0	23	0	0
T35	22832	0	0	0
T36	0	28	0	0
T41	8503	11	0	0
T42	14810	23	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	5	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	29	0	0
T179	0	14	0	0
T253	0	6	0	0
T255	0	28	0	0
T257	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	677	0	0
T32	9130	0	0	0
T33	0	23	0	0
T35	22832	0	0	0
T36	0	28	0	0
T41	8503	11	0	0
T42	14810	23	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	5	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	29	0	0
T179	0	14	0	0
T253	0	6	0	0
T255	0	28	0	0
T257	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77067	0	0
T32	9130	0	0	0
T33	0	3396	0	0
T35	22832	0	0	0
T36	0	897	0	0
T42	14810	2327	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	279	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T111	522	0	0	0
T112	503	0	0	0
T125	0	2321	0	0
T179	0	2185	0	0
T253	0	172	0	0
T255	0	3337	0	0
T257	0	1052	0	0
T258	0	2105	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	561	0	0
T32	9130	0	0	0
T33	0	16	0	0
T35	22832	0	0	0
T36	0	28	0	0
T42	14810	20	0	0
T75	2721	0	0	0
T76	523	0	0	0
T101	0	4	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T111	522	0	0	0
T112	503	0	0	0
T125	0	26	0	0
T179	0	8	0	0
T253	0	6	0	0
T255	0	27	0	0
T257	0	8	0	0
T258	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T7,T26
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T7,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T43

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T43
1	0	Covered	T3,T17,T7
1	1	Covered	T7,T8,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T43
0	1	Covered	T43,T34,T259
1	0	Covered	T57,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T42
0	1	Covered	T7,T8,T42
1	0	Covered	T57,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T42
1	-	Covered	T7,T8,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T43
DetectSt	168	Covered	T7,T8,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T43
DebounceSt->IdleSt	163	Covered	T8,T43,T42
DetectSt->IdleSt	186	Covered	T43,T34,T259
DetectSt->StableSt	191	Covered	T7,T8,T42
IdleSt->DebounceSt	148	Covered	T7,T8,T43
StableSt->IdleSt	206	Covered	T7,T8,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T43
0	1	Covered	T7,T8,T43
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T43,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T43
DetectSt	-	-	-	-	1	-	-	Covered	T43,T34,T259
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T42
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T43
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	820	0	0
CntIncr_A	8285647	44518	0	0
CntNoWrap_A	8285647	7611095	0	0
DetectStDropOut_A	8285647	86	0	0
DetectedOut_A	8285647	17270	0	0
DetectedPulseOut_A	8285647	298	0	0
DisabledIdleSt_A	8285647	7221980	0	0
DisabledNoDetection_A	8285647	7223713	0	0
EnterDebounceSt_A	8285647	432	0	0
EnterDetectSt_A	8285647	389	0	0
EnterStableSt_A	8285647	298	0	0
PulseIsPulse_A	8285647	298	0	0
StayInStableSt	8285647	16959	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	820	0	0
T7	20110	12	0	0
T8	15300	3	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	4	0	0
T33	0	12	0	0
T34	0	5	0	0
T42	0	9	0	0
T43	0	3	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T125	0	8	0	0
T260	0	20	0	0
T261	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	44518	0	0
T7	20110	804	0	0
T8	15300	129	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	156	0	0
T33	0	372	0	0
T34	0	343	0	0
T42	0	336	0	0
T43	0	200	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T125	0	248	0	0
T260	0	830	0	0
T261	0	1040	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611095	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	86	0	0
T32	9130	0	0	0
T34	0	2	0	0
T35	22832	0	0	0
T41	8503	0	0	0
T42	14810	0	0	0
T43	13986	1	0	0
T74	525	0	0	0
T75	2721	0	0	0
T95	0	11	0	0
T105	0	1	0	0
T106	0	7	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T202	0	6	0	0
T259	0	2	0	0
T262	0	9	0	0
T263	0	11	0	0
T264	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	17270	0	0
T7	20110	33	0	0
T8	15300	31	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	28	0	0
T33	0	573	0	0
T42	0	382	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	95	0	0
T70	502	0	0	0
T98	0	77	0	0
T125	0	254	0	0
T260	0	595	0	0
T261	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	298	0	0
T7	20110	6	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T42	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	1	0	0
T70	502	0	0	0
T98	0	3	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7221980	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7223713	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	432	0	0
T7	20110	6	0	0
T8	15300	2	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	3	0	0
T42	0	5	0	0
T43	0	2	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	389	0	0
T7	20110	6	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	3	0	0
T42	0	4	0	0
T43	0	1	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	298	0	0
T7	20110	6	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T42	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	1	0	0
T70	502	0	0	0
T98	0	3	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	298	0	0
T7	20110	6	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T42	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	1	0	0
T70	502	0	0	0
T98	0	3	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	16959	0	0
T7	20110	27	0	0
T8	15300	30	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	26	0	0
T33	0	567	0	0
T42	0	378	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	94	0	0
T70	502	0	0	0
T98	0	74	0	0
T125	0	250	0	0
T260	0	585	0	0
T261	0	112	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	283	0	0
T7	20110	6	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T42	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	1	0	0
T70	502	0	0	0
T98	0	3	0	0
T125	0	4	0	0
T260	0	10	0	0
T261	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T26,T28
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T41,T42
1	1	Covered	T17,T26,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
1	0	Covered	T35,T265,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T41,T42
0	1	Covered	T44,T41,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T41,T42
1	-	Covered	T44,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T26,T28
DetectSt	168	Covered	T17,T26,T28
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T44,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T26,T28
DebounceSt->IdleSt	163	Covered	T57,T116,T58
DetectSt->IdleSt	186	Covered	T17,T26,T28
DetectSt->StableSt	191	Covered	T44,T41,T42
IdleSt->DebounceSt	148	Covered	T17,T26,T28
StableSt->IdleSt	206	Covered	T44,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T26,T28
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T26,T28
IdleSt	0	-	-	-	-	-	-	Covered	T17,T26,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T26,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T116,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	0	1	-	Covered	T44,T41,T42
DetectSt	-	-	-	-	0	0	-	Covered	T17,T26,T28
StableSt	-	-	-	-	-	-	1	Covered	T44,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T44,T41,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	2718	0	0
CntIncr_A	8285647	104208	0	0
CntNoWrap_A	8285647	7609197	0	0
DetectStDropOut_A	8285647	428	0	0
DetectedOut_A	8285647	77898	0	0
DetectedPulseOut_A	8285647	783	0	0
DisabledIdleSt_A	8285647	7154750	0	0
DisabledNoDetection_A	8285647	7156961	0	0
EnterDebounceSt_A	8285647	1365	0	0
EnterDetectSt_A	8285647	1353	0	0
EnterStableSt_A	8285647	783	0	0
PulseIsPulse_A	8285647	783	0	0
StayInStableSt	8285647	77020	0	0
gen_high_event_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	688	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2718	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	44	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	50	0	0
T28	0	12	0	0
T35	0	16	0	0
T36	0	28	0	0
T41	0	18	0	0
T42	0	60	0	0
T44	0	18	0	0
T45	0	48	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	104208	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	955	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	1276	0	0
T28	0	294	0	0
T35	0	532	0	0
T36	0	952	0	0
T41	0	639	0	0
T42	0	2220	0	0
T44	0	468	0	0
T45	0	960	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	475	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7609197	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4321	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	428	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	22	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	6	0	0
T35	0	1	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T57	0	1	0	0
T79	0	12	0	0
T86	0	5	0	0
T147	0	25	0	0
T252	0	5	0	0
T265	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77898	0	0
T33	0	2058	0	0
T36	0	295	0	0
T37	2453	0	0	0
T41	8503	302	0	0
T42	14810	984	0	0
T43	13986	0	0	0
T44	10958	1533	0	0
T45	0	2182	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	1764	0	0
T125	0	1737	0	0
T177	428	0	0	0
T253	0	1063	0	0
T254	0	2176	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	783	0	0
T33	0	24	0	0
T36	0	14	0	0
T37	2453	0	0	0
T41	8503	9	0	0
T42	14810	30	0	0
T43	13986	0	0	0
T44	10958	9	0	0
T45	0	24	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	28	0	0
T125	0	29	0	0
T177	428	0	0	0
T253	0	23	0	0
T254	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7154750	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7156961	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1365	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	22	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	6	0	0
T35	0	8	0	0
T36	0	14	0	0
T41	0	9	0	0
T42	0	30	0	0
T44	0	9	0	0
T45	0	24	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1353	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	22	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	6	0	0
T35	0	8	0	0
T36	0	14	0	0
T41	0	9	0	0
T42	0	30	0	0
T44	0	9	0	0
T45	0	24	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	783	0	0
T33	0	24	0	0
T36	0	14	0	0
T37	2453	0	0	0
T41	8503	9	0	0
T42	14810	30	0	0
T43	13986	0	0	0
T44	10958	9	0	0
T45	0	24	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	28	0	0
T125	0	29	0	0
T177	428	0	0	0
T253	0	23	0	0
T254	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	783	0	0
T33	0	24	0	0
T36	0	14	0	0
T37	2453	0	0	0
T41	8503	9	0	0
T42	14810	30	0	0
T43	13986	0	0	0
T44	10958	9	0	0
T45	0	24	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	28	0	0
T125	0	29	0	0
T177	428	0	0	0
T253	0	23	0	0
T254	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77020	0	0
T33	0	2030	0	0
T36	0	280	0	0
T37	2453	0	0	0
T41	8503	293	0	0
T42	14810	953	0	0
T43	13986	0	0	0
T44	10958	1522	0	0
T45	0	2151	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	1736	0	0
T125	0	1705	0	0
T177	428	0	0	0
T253	0	1040	0	0
T254	0	2161	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	688	0	0
T33	0	20	0	0
T36	0	13	0	0
T37	2453	0	0	0
T41	8503	9	0	0
T42	14810	29	0	0
T43	13986	0	0	0
T44	10958	7	0	0
T45	0	17	0	0
T62	1551	0	0	0
T72	521	0	0	0
T73	502	0	0	0
T74	525	0	0	0
T97	0	28	0	0
T125	0	26	0	0
T177	428	0	0	0
T253	0	23	0	0
T254	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T7,T26
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T7,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T44
1	0	Covered	T3,T17,T7
1	1	Covered	T7,T8,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T44
0	1	Covered	T7,T32,T266
1	0	Covered	T57,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T44,T43
0	1	Covered	T8,T43,T45
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T44,T43
1	-	Covered	T8,T43,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T44
DetectSt	168	Covered	T7,T8,T44
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T44,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T44
DebounceSt->IdleSt	163	Covered	T8,T32,T45
DetectSt->IdleSt	186	Covered	T7,T32,T266
DetectSt->StableSt	191	Covered	T8,T44,T43
IdleSt->DebounceSt	148	Covered	T7,T8,T44
StableSt->IdleSt	206	Covered	T8,T44,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T44
0	1	Covered	T7,T8,T44
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T44
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T32,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T44
DetectSt	-	-	-	-	1	-	-	Covered	T7,T32,T266
DetectSt	-	-	-	-	0	1	-	Covered	T8,T44,T43
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T44
StableSt	-	-	-	-	-	-	1	Covered	T8,T43,T45
StableSt	-	-	-	-	-	-	0	Covered	T8,T44,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	850	0	0
CntIncr_A	8285647	47463	0	0
CntNoWrap_A	8285647	7611065	0	0
DetectStDropOut_A	8285647	96	0	0
DetectedOut_A	8285647	13582	0	0
DetectedPulseOut_A	8285647	297	0	0
DisabledIdleSt_A	8285647	7218903	0	0
DisabledNoDetection_A	8285647	7220649	0	0
EnterDebounceSt_A	8285647	453	0	0
EnterDetectSt_A	8285647	398	0	0
EnterStableSt_A	8285647	297	0	0
PulseIsPulse_A	8285647	297	0	0
StayInStableSt	8285647	13264	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	270	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	850	0	0
T7	20110	4	0	0
T8	15300	3	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	27	0	0
T33	0	6	0	0
T34	0	2	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	11	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T97	0	14	0	0
T261	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	47463	0	0
T7	20110	278	0	0
T8	15300	96	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1257	0	0
T33	0	306	0	0
T34	0	98	0	0
T43	0	168	0	0
T44	0	162	0	0
T45	0	293	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T97	0	434	0	0
T261	0	2814	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611065	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	96	0	0
T7	20110	2	0	0
T8	15300	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	13	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T81	0	4	0	0
T95	0	7	0	0
T99	0	1	0	0
T105	0	4	0	0
T263	0	1	0	0
T266	0	3	0	0
T267	0	10	0	0
T268	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	13582	0	0
T8	15300	63	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	167	0	0
T34	0	16	0	0
T43	0	84	0	0
T44	0	77	0	0
T45	0	334	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	673	0	0
T125	0	135	0	0
T253	0	78	0	0
T261	0	351	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	297	0	0
T8	15300	1	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	7	0	0
T125	0	3	0	0
T253	0	1	0	0
T261	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7218903	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7220649	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	453	0	0
T7	20110	2	0	0
T8	15300	2	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	14	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	6	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T97	0	7	0	0
T261	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	398	0	0
T7	20110	2	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	13	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T97	0	7	0	0
T261	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	297	0	0
T8	15300	1	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	7	0	0
T125	0	3	0	0
T253	0	1	0	0
T261	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	297	0	0
T8	15300	1	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	7	0	0
T125	0	3	0	0
T253	0	1	0	0
T261	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	13264	0	0
T8	15300	62	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	164	0	0
T34	0	15	0	0
T43	0	82	0	0
T44	0	73	0	0
T45	0	325	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	666	0	0
T125	0	131	0	0
T253	0	77	0	0
T261	0	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	270	0	0
T8	15300	1	0	0
T9	884	0	0	0
T24	488	0	0	0
T25	503	0	0	0
T31	1502	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T64	0	4	0	0
T70	502	0	0	0
T71	422	0	0	0
T97	0	7	0	0
T125	0	2	0	0
T253	0	1	0	0
T261	0	9	0	0