Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T26,T28
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T17,T26,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T41,T42
1	1	Covered	T17,T26,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
1	0	Covered	T44,T42,T179

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T35,T45
0	1	Covered	T41,T35,T45
1	0	Covered	T86,T269,T193

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T35,T45
1	-	Covered	T41,T35,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T26,T28
DetectSt	168	Covered	T17,T26,T28
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T41,T35,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T26,T28
DebounceSt->IdleSt	163	Covered	T57,T116,T58
DetectSt->IdleSt	186	Covered	T17,T26,T28
DetectSt->StableSt	191	Covered	T41,T35,T45
IdleSt->DebounceSt	148	Covered	T17,T26,T28
StableSt->IdleSt	206	Covered	T41,T35,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T26,T28
0	1	Covered	T17,T26,T28
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T26,T28
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T26,T28
IdleSt	0	-	-	-	-	-	-	Covered	T17,T26,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T26,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T57,T116,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T28
DetectSt	-	-	-	-	0	1	-	Covered	T41,T35,T45
DetectSt	-	-	-	-	0	0	-	Covered	T17,T26,T28
StableSt	-	-	-	-	-	-	1	Covered	T41,T35,T45
StableSt	-	-	-	-	-	-	0	Covered	T41,T35,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	2873	0	0
CntIncr_A	8285647	109616	0	0
CntNoWrap_A	8285647	7609042	0	0
DetectStDropOut_A	8285647	447	0	0
DetectedOut_A	8285647	78069	0	0
DetectedPulseOut_A	8285647	840	0	0
DisabledIdleSt_A	8285647	7164415	0	0
DisabledNoDetection_A	8285647	7166614	0	0
EnterDebounceSt_A	8285647	1444	0	0
EnterDetectSt_A	8285647	1429	0	0
EnterStableSt_A	8285647	840	0	0
PulseIsPulse_A	8285647	840	0	0
StayInStableSt	8285647	77121	0	0
gen_high_event_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	683	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	2873	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	22	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	50	0	0
T28	0	24	0	0
T35	0	26	0	0
T36	0	28	0	0
T41	0	56	0	0
T42	0	12	0	0
T44	0	26	0	0
T45	0	6	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	109616	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	468	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	1275	0	0
T28	0	595	0	0
T35	0	663	0	0
T36	0	896	0	0
T41	0	1988	0	0
T42	0	454	0	0
T44	0	729	0	0
T45	0	141	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	1036	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7609042	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4343	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	447	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	11	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	12	0	0
T44	0	8	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T57	0	1	0	0
T79	0	26	0	0
T147	0	14	0	0
T252	0	11	0	0
T270	0	2	0	0
T271	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	78069	0	0
T32	9130	0	0	0
T33	0	584	0	0
T35	22832	1667	0	0
T36	0	351	0	0
T41	8503	533	0	0
T42	14810	0	0	0
T45	0	79	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	392	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	2733	0	0
T253	0	511	0	0
T254	0	1840	0	0
T255	0	1684	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	840	0	0
T32	9130	0	0	0
T33	0	9	0	0
T35	22832	13	0	0
T36	0	14	0	0
T41	8503	28	0	0
T42	14810	0	0	0
T45	0	3	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	27	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	25	0	0
T253	0	23	0	0
T254	0	16	0	0
T255	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7164415	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	2014	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7166614	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	2014	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1444	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	11	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	12	0	0
T35	0	13	0	0
T36	0	14	0	0
T41	0	28	0	0
T42	0	6	0	0
T44	0	13	0	0
T45	0	3	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	1429	0	0
T6	1307	0	0	0
T7	20110	0	0	0
T8	15300	0	0	0
T17	4766	11	0	0
T18	422	0	0	0
T24	488	0	0	0
T26	5166	25	0	0
T28	0	12	0	0
T35	0	13	0	0
T36	0	14	0	0
T41	0	28	0	0
T42	0	6	0	0
T44	0	13	0	0
T45	0	3	0	0
T52	441	0	0	0
T53	415	0	0	0
T54	403	0	0	0
T79	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	840	0	0
T32	9130	0	0	0
T33	0	9	0	0
T35	22832	13	0	0
T36	0	14	0	0
T41	8503	28	0	0
T42	14810	0	0	0
T45	0	3	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	27	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	25	0	0
T253	0	23	0	0
T254	0	16	0	0
T255	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	840	0	0
T32	9130	0	0	0
T33	0	9	0	0
T35	22832	13	0	0
T36	0	14	0	0
T41	8503	28	0	0
T42	14810	0	0	0
T45	0	3	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	27	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	25	0	0
T253	0	23	0	0
T254	0	16	0	0
T255	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	77121	0	0
T32	9130	0	0	0
T33	0	574	0	0
T35	22832	1649	0	0
T36	0	336	0	0
T41	8503	505	0	0
T42	14810	0	0	0
T45	0	76	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	365	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	2705	0	0
T253	0	488	0	0
T254	0	1820	0	0
T255	0	1674	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	683	0	0
T32	9130	0	0	0
T33	0	8	0	0
T35	22832	8	0	0
T36	0	13	0	0
T41	8503	28	0	0
T42	14810	0	0	0
T45	0	3	0	0
T74	525	0	0	0
T75	2721	0	0	0
T76	523	0	0	0
T97	0	27	0	0
T108	680	0	0	0
T109	410	0	0	0
T110	422	0	0	0
T125	0	22	0	0
T253	0	23	0	0
T254	0	12	0	0
T255	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T7,T26
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T7,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T8,T43

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T8,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T43
1	0	Covered	T3,T17,T7
1	1	Covered	T7,T8,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T43
0	1	Covered	T260,T64,T266
1	0	Covered	T57,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T43
0	1	Covered	T7,T8,T43
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T43
1	-	Covered	T7,T8,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T43
DetectSt	168	Covered	T7,T8,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T8,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T43
DebounceSt->IdleSt	163	Covered	T7,T43,T260
DetectSt->IdleSt	186	Covered	T260,T64,T266
DetectSt->StableSt	191	Covered	T7,T8,T43
IdleSt->DebounceSt	148	Covered	T7,T8,T43
StableSt->IdleSt	206	Covered	T7,T8,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T43
0	1	Covered	T7,T8,T43
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T57,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T43,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T43
DetectSt	-	-	-	-	1	-	-	Covered	T260,T64,T266
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T43
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T43
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T43
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8285647	783	0	0
CntIncr_A	8285647	45124	0	0
CntNoWrap_A	8285647	7611132	0	0
DetectStDropOut_A	8285647	19	0	0
DetectedOut_A	8285647	13071	0	0
DetectedPulseOut_A	8285647	346	0	0
DisabledIdleSt_A	8285647	7228306	0	0
DisabledNoDetection_A	8285647	7230041	0	0
EnterDebounceSt_A	8285647	414	0	0
EnterDetectSt_A	8285647	369	0	0
EnterStableSt_A	8285647	346	0	0
PulseIsPulse_A	8285647	346	0	0
StayInStableSt	8285647	12706	0	0
gen_high_level_sva.HighLevelEvent_A	8285647	7614305	0	0
gen_not_sticky_sva.StableStDropOut_A	8285647	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	783	0	0
T7	20110	7	0	0
T8	15300	2	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	10	0	0
T36	0	2	0	0
T43	0	9	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	4	0	0
T260	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	45124	0	0
T7	20110	441	0	0
T8	15300	100	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	66	0	0
T33	0	70	0	0
T34	0	101	0	0
T35	0	280	0	0
T36	0	63	0	0
T43	0	434	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	220	0	0
T260	0	563	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7611132	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	19	0	0
T38	10847	0	0	0
T51	756	0	0	0
T64	0	1	0	0
T97	7889	0	0	0
T125	17573	0	0	0
T131	0	1	0	0
T134	0	2	0	0
T260	32519	3	0	0
T261	32807	0	0	0
T262	0	1	0	0
T266	0	2	0	0
T272	0	1	0	0
T273	0	4	0	0
T274	0	4	0	0
T275	616	0	0	0
T276	533	0	0	0
T277	427	0	0	0
T278	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	13071	0	0
T7	20110	71	0	0
T8	15300	42	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	26	0	0
T33	0	86	0	0
T34	0	14	0	0
T35	0	480	0	0
T36	0	58	0	0
T43	0	145	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	146	0	0
T261	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	346	0	0
T7	20110	3	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	2	0	0
T261	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7228306	0	0
T1	990	589	0	0
T2	669	268	0	0
T3	2393	790	0	0
T4	427	26	0	0
T5	36896	36495	0	0
T13	941	540	0	0
T14	408	7	0	0
T15	525	124	0	0
T16	624	223	0	0
T17	4766	4365	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7230041	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	414	0	0
T7	20110	4	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	5	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	2	0	0
T260	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	369	0	0
T7	20110	3	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	2	0	0
T260	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	346	0	0
T7	20110	3	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	2	0	0
T261	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	346	0	0
T7	20110	3	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	4	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	2	0	0
T261	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	12706	0	0
T7	20110	68	0	0
T8	15300	41	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	25	0	0
T33	0	84	0	0
T34	0	12	0	0
T35	0	475	0	0
T36	0	57	0	0
T43	0	141	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T124	0	144	0	0
T261	0	119	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	7614305	0	0
T1	990	590	0	0
T2	669	269	0	0
T3	2393	793	0	0
T4	427	27	0	0
T5	36896	36496	0	0
T13	941	541	0	0
T14	408	8	0	0
T15	525	125	0	0
T16	624	224	0	0
T17	4766	4366	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8285647	323	0	0
T7	20110	3	0	0
T8	15300	1	0	0
T24	488	0	0	0
T25	503	0	0	0
T26	5166	0	0	0
T32	0	1	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	3	0	0
T53	415	0	0	0
T54	403	0	0	0
T55	775	0	0	0
T56	425	0	0	0
T70	502	0	0	0
T98	0	6	0	0
T124	0	2	0	0
T125	0	3	0	0
T261	0	3	0	0