Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1229906750	10154	0	0
auto_block_debounce_ctl_rd_A	1229906750	2498	0	0
auto_block_out_ctl_rd_A	1229906750	3577	0	0
com_det_ctl_0_rd_A	1229906750	4349	0	0
com_det_ctl_1_rd_A	1229906750	4413	0	0
com_det_ctl_2_rd_A	1229906750	4546	0	0
com_det_ctl_3_rd_A	1229906750	4451	0	0
com_out_ctl_0_rd_A	1229906750	5271	0	0
com_out_ctl_1_rd_A	1229906750	5271	0	0
com_out_ctl_2_rd_A	1229906750	5176	0	0
com_out_ctl_3_rd_A	1229906750	5193	0	0
com_pre_det_ctl_0_rd_A	1229906750	1861	0	0
com_pre_det_ctl_1_rd_A	1229906750	1929	0	0
com_pre_det_ctl_2_rd_A	1229906750	1923	0	0
com_pre_det_ctl_3_rd_A	1229906750	1901	0	0
com_pre_sel_ctl_0_rd_A	1229906750	5235	0	0
com_pre_sel_ctl_1_rd_A	1229906750	5309	0	0
com_pre_sel_ctl_2_rd_A	1229906750	5330	0	0
com_pre_sel_ctl_3_rd_A	1229906750	5521	0	0
com_sel_ctl_0_rd_A	1229906750	5550	0	0
com_sel_ctl_1_rd_A	1229906750	5384	0	0
com_sel_ctl_2_rd_A	1229906750	5349	0	0
com_sel_ctl_3_rd_A	1229906750	5598	0	0
ec_rst_ctl_rd_A	1229906750	3041	0	0
intr_enable_rd_A	1229906750	2485	0	0
key_intr_ctl_rd_A	1229906750	5295	0	0
key_intr_debounce_ctl_rd_A	1229906750	1826	0	0
key_invert_ctl_rd_A	1229906750	6298	0	0
pin_allowed_ctl_rd_A	1229906750	8551	0	0
pin_out_ctl_rd_A	1229906750	5861	0	0
pin_out_value_rd_A	1229906750	5886	0	0
regwen_rd_A	1229906750	2115	0	0
ulp_ac_debounce_ctl_rd_A	1229906750	1921	0	0
ulp_ctl_rd_A	1229906750	2026	0	0
ulp_lid_debounce_ctl_rd_A	1229906750	2128	0	0
ulp_pwrb_debounce_ctl_rd_A	1229906750	2112	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	10154	0	0
T8	175954	21	0	0
T9	55648	0	0	0
T24	244486	0	0	0
T25	35237	0	0	0
T31	100183	0	0	0
T38	0	7	0	0
T54	100682	0	0	0
T55	93089	0	0	0
T56	48980	0	0	0
T70	251414	0	0	0
T71	209155	0	0	0
T78	0	5	0	0
T80	0	13	0	0
T81	0	18	0	0
T87	0	6	0	0
T95	0	21	0	0
T149	0	2	0	0
T200	0	21	0	0
T302	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2498	0	0
T6	121331	0	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T16	306303	3	0	0
T17	209726	0	0	0
T18	211067	0	0	0
T26	250579	0	0	0
T50	0	15	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T78	0	24	0	0
T127	0	16	0	0
T303	0	11	0	0
T304	0	12	0	0
T305	0	21	0	0
T306	0	7	0	0
T307	0	11	0	0
T308	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	3577	0	0
T33	368470	0	0	0
T50	340895	13	0	0
T63	51614	0	0	0
T78	0	39	0	0
T124	537290	0	0	0
T127	0	15	0	0
T260	156088	0	0	0
T275	295826	0	0	0
T276	29390	0	0	0
T277	53371	0	0	0
T303	0	13	0	0
T304	0	16	0	0
T305	0	17	0	0
T306	0	8	0	0
T307	0	15	0	0
T308	0	9	0	0
T309	0	17	0	0
T310	191052	0	0	0
T311	645528	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	4349	0	0
T32	123263	0	0	0
T33	0	79	0	0
T35	273978	59	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	38	0	0
T64	0	24	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	29	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	40	0	0
T253	0	29	0	0
T260	0	55	0	0
T261	0	59	0	0
T266	0	54	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	4413	0	0
T32	123263	0	0	0
T33	0	89	0	0
T35	273978	56	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	30	0	0
T64	0	24	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	42	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	46	0	0
T253	0	30	0	0
T260	0	65	0	0
T261	0	52	0	0
T266	0	36	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	4546	0	0
T32	123263	0	0	0
T33	0	71	0	0
T35	273978	57	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	55	0	0
T64	0	61	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	27	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	56	0	0
T253	0	49	0	0
T260	0	57	0	0
T261	0	86	0	0
T266	0	48	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	4451	0	0
T32	123263	0	0	0
T33	0	52	0	0
T35	273978	44	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	71	0	0
T64	0	22	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	55	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	58	0	0
T253	0	28	0	0
T260	0	81	0	0
T261	0	59	0	0
T266	0	55	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5271	0	0
T32	123263	0	0	0
T33	0	101	0	0
T35	273978	70	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	40	0	0
T64	0	36	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	57	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	56	0	0
T253	0	27	0	0
T260	0	61	0	0
T261	0	69	0	0
T266	0	45	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5271	0	0
T32	123263	0	0	0
T33	0	66	0	0
T35	273978	77	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	44	0	0
T64	0	40	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	29	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	44	0	0
T253	0	36	0	0
T260	0	94	0	0
T261	0	67	0	0
T266	0	53	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5176	0	0
T32	123263	0	0	0
T33	0	69	0	0
T35	273978	72	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	57	0	0
T64	0	44	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	49	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	52	0	0
T253	0	30	0	0
T260	0	66	0	0
T261	0	65	0	0
T266	0	76	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5193	0	0
T32	123263	0	0	0
T33	0	69	0	0
T35	273978	88	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	53	0	0
T64	0	47	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	39	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	67	0	0
T253	0	31	0	0
T260	0	71	0	0
T261	0	75	0	0
T266	0	57	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1861	0	0
T78	515334	26	0	0
T102	263132	0	0	0
T140	0	11	0	0
T151	124314	0	0	0
T161	0	25	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	18	0	0
T247	0	10	0	0
T307	0	2	0	0
T308	0	11	0	0
T312	0	13	0	0
T313	0	30	0	0
T314	0	30	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1929	0	0
T78	515334	27	0	0
T102	263132	0	0	0
T140	0	4	0	0
T151	124314	0	0	0
T161	0	19	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	30	0	0
T247	0	15	0	0
T307	0	19	0	0
T308	0	17	0	0
T312	0	9	0	0
T313	0	21	0	0
T314	0	26	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1923	0	0
T78	515334	28	0	0
T102	263132	0	0	0
T140	0	8	0	0
T151	124314	0	0	0
T161	0	24	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	29	0	0
T247	0	13	0	0
T307	0	29	0	0
T308	0	2	0	0
T312	0	9	0	0
T313	0	14	0	0
T314	0	28	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1901	0	0
T78	515334	28	0	0
T102	263132	0	0	0
T140	0	6	0	0
T151	124314	0	0	0
T161	0	19	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	29	0	0
T247	0	4	0	0
T307	0	18	0	0
T308	0	7	0	0
T312	0	2	0	0
T313	0	30	0	0
T314	0	24	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5235	0	0
T32	123263	0	0	0
T33	0	72	0	0
T35	273978	55	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	48	0	0
T64	0	50	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	62	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	62	0	0
T253	0	28	0	0
T260	0	80	0	0
T261	0	69	0	0
T266	0	25	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5309	0	0
T32	123263	0	0	0
T33	0	64	0	0
T35	273978	53	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	43	0	0
T64	0	43	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	39	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	49	0	0
T253	0	42	0	0
T260	0	59	0	0
T261	0	70	0	0
T266	0	34	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5330	0	0
T32	123263	0	0	0
T33	0	91	0	0
T35	273978	87	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	51	0	0
T64	0	31	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	42	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	41	0	0
T253	0	22	0	0
T260	0	68	0	0
T261	0	73	0	0
T266	0	49	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5521	0	0
T32	123263	0	0	0
T33	0	63	0	0
T35	273978	79	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	36	0	0
T64	0	54	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	55	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	68	0	0
T253	0	29	0	0
T260	0	58	0	0
T261	0	65	0	0
T266	0	17	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5550	0	0
T32	123263	0	0	0
T33	0	48	0	0
T35	273978	58	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	34	0	0
T64	0	49	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	46	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	43	0	0
T253	0	27	0	0
T260	0	83	0	0
T261	0	73	0	0
T266	0	61	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5384	0	0
T32	123263	0	0	0
T33	0	67	0	0
T35	273978	63	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	38	0	0
T64	0	45	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	45	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	29	0	0
T253	0	28	0	0
T260	0	50	0	0
T261	0	63	0	0
T266	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5349	0	0
T32	123263	0	0	0
T33	0	88	0	0
T35	273978	89	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	50	0	0
T64	0	47	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	46	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	46	0	0
T253	0	37	0	0
T260	0	69	0	0
T261	0	71	0	0
T266	0	45	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5598	0	0
T32	123263	0	0	0
T33	0	66	0	0
T35	273978	72	0	0
T41	106296	0	0	0
T42	199943	0	0	0
T43	377616	19	0	0
T64	0	29	0	0
T74	63013	0	0	0
T75	130605	0	0	0
T99	0	37	0	0
T108	336747	0	0	0
T109	125233	0	0	0
T110	202344	0	0	0
T125	0	35	0	0
T253	0	42	0	0
T260	0	59	0	0
T261	0	61	0	0
T266	0	41	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	3041	0	0
T6	121331	0	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T17	209726	9	0	0
T18	211067	0	0	0
T24	244486	0	0	0
T26	250579	0	0	0
T33	0	36	0	0
T35	0	24	0	0
T43	0	15	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T55	0	4	0	0
T60	0	2	0	0
T108	0	1	0	0
T260	0	44	0	0
T261	0	48	0	0
T315	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2485	0	0
T78	515334	23	0	0
T102	263132	0	0	0
T151	124314	0	0	0
T161	0	42	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	66	0	0
T247	0	14	0	0
T307	0	31	0	0
T308	0	22	0	0
T312	0	13	0	0
T313	0	47	0	0
T316	0	30	0	0
T317	0	6	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5295	0	0
T57	0	94	0	0
T78	515334	43	0	0
T102	263132	0	0	0
T151	124314	1	0	0
T156	0	1	0	0
T162	28272	0	0	0
T173	0	3	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T189	0	10	0	0
T201	0	3	0	0
T307	0	24	0	0
T308	0	17	0	0
T312	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1826	0	0
T78	515334	20	0	0
T102	263132	0	0	0
T140	0	16	0	0
T151	124314	0	0	0
T161	0	20	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	10	0	0
T247	0	13	0	0
T307	0	6	0	0
T308	0	3	0	0
T312	0	19	0	0
T313	0	19	0	0
T314	0	27	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	6298	0	0
T9	55648	0	0	0
T10	57992	0	0	0
T25	35237	68	0	0
T31	100183	0	0	0
T55	93089	0	0	0
T56	48980	0	0	0
T59	92115	0	0	0
T60	79760	0	0	0
T64	0	117	0	0
T70	251414	0	0	0
T71	209155	0	0	0
T78	0	30	0	0
T122	0	65	0	0
T307	0	13	0	0
T308	0	111	0	0
T318	0	65	0	0
T319	0	60	0	0
T320	0	26	0	0
T321	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	8551	0	0
T45	139120	0	0	0
T67	120620	0	0	0
T68	61845	0	0	0
T78	0	15	0	0
T79	303836	0	0	0
T112	165911	43	0	0
T113	192914	0	0	0
T114	246221	0	0	0
T307	0	7	0	0
T308	0	53	0	0
T322	0	30	0	0
T323	0	71	0	0
T324	0	79	0	0
T325	0	57	0	0
T326	0	68	0	0
T327	0	60	0	0
T328	210771	0	0	0
T329	40607	0	0	0
T330	200405	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5861	0	0
T45	139120	0	0	0
T67	120620	0	0	0
T68	61845	0	0	0
T78	0	29	0	0
T79	303836	0	0	0
T112	165911	69	0	0
T113	192914	0	0	0
T114	246221	0	0	0
T307	0	7	0	0
T308	0	75	0	0
T322	0	31	0	0
T323	0	44	0	0
T324	0	63	0	0
T325	0	51	0	0
T326	0	80	0	0
T327	0	47	0	0
T328	210771	0	0	0
T329	40607	0	0	0
T330	200405	0	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	5886	0	0
T45	139120	0	0	0
T67	120620	0	0	0
T68	61845	0	0	0
T78	0	21	0	0
T79	303836	0	0	0
T112	165911	37	0	0
T113	192914	0	0	0
T114	246221	0	0	0
T307	0	7	0	0
T308	0	58	0	0
T322	0	31	0	0
T323	0	61	0	0
T324	0	65	0	0
T325	0	48	0	0
T326	0	72	0	0
T327	0	22	0	0
T328	210771	0	0	0
T329	40607	0	0	0
T330	200405	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2115	0	0
T78	515334	18	0	0
T102	263132	0	0	0
T140	0	4	0	0
T151	124314	0	0	0
T161	0	15	0	0
T162	28272	0	0	0
T178	201844	0	0	0
T179	255520	0	0	0
T180	24208	0	0	0
T181	246251	0	0	0
T182	95504	0	0	0
T183	50017	0	0	0
T240	0	7	0	0
T247	0	13	0	0
T307	0	17	0	0
T308	0	6	0	0
T312	0	15	0	0
T313	0	29	0	0
T314	0	25	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	1921	0	0
T6	121331	6	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T9	0	3	0	0
T24	244486	0	0	0
T25	35237	0	0	0
T26	250579	0	0	0
T31	0	10	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T55	93089	0	0	0
T61	0	6	0	0
T64	0	5	0	0
T78	0	12	0	0
T126	0	9	0	0
T136	0	12	0	0
T307	0	14	0	0
T308	0	19	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2026	0	0
T6	121331	10	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T24	244486	0	0	0
T25	35237	0	0	0
T26	250579	0	0	0
T31	0	10	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T55	93089	0	0	0
T61	0	4	0	0
T78	0	22	0	0
T126	0	9	0	0
T136	0	6	0	0
T137	0	9	0	0
T307	0	24	0	0
T308	0	6	0	0
T312	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2128	0	0
T6	121331	6	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T9	0	13	0	0
T24	244486	0	0	0
T25	35237	0	0	0
T26	250579	0	0	0
T31	0	14	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T55	93089	0	0	0
T61	0	8	0	0
T64	0	6	0	0
T78	0	12	0	0
T126	0	10	0	0
T307	0	16	0	0
T308	0	5	0	0
T331	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229906750	2112	0	0
T6	121331	6	0	0
T7	844652	0	0	0
T8	175954	0	0	0
T9	0	8	0	0
T24	244486	0	0	0
T25	35237	0	0	0
T26	250579	0	0	0
T31	0	6	0	0
T52	214547	0	0	0
T53	53924	0	0	0
T54	100682	0	0	0
T55	93089	0	0	0
T61	0	10	0	0
T64	0	2	0	0
T78	0	28	0	0
T126	0	6	0	0
T136	0	5	0	0
T307	0	19	0	0
T332	0	8	0	0