Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1898

1

T7

40

T10

52

T11

12

auto[1]

443

1

T2

4

T9

9

T11

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1685

1

T7

18

T9

9

T10

34

auto[1]

656

1

T2

4

T7

22

T10

18

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T2

4

T7

40

T9

9

auto[1]

561

1

T11

3

T31

4

T32

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1714

1

T2

4

T7

23

T9

4

auto[1]

627

1

T7

17

T9

5

T10

21

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971

1

T2

4

T7

17

T9

9

auto[1]

370

1

T7

23

T10

18

T31

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2115

1

T2

4

T7

40

T9

9

auto[1]

226

1

T10

12

T11

2

T31

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2141

1

T2

4

T7

10

T9

9

auto[1]

200

1

T7

30

T10

3

T31

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2199

1

T2

4

T7

27

T9

9

auto[1]

142

1

T7

13

T11

1

T31

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121

1

T2

4

T7

32

T9

9

auto[1]

220

1

T7

8

T10

18

T11

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1708

1

T2

4

T7

24

T9

5

auto[1]

633

1

T7

16

T9

4

T10

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	763	1			T2	4		T9	9		T32	15
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	134	1			T41	4		T204	5		T208	18
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	71	1			T11	3		T204	16		T176	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	42	1			T10	18		T31	2		T94	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	32	1			T11	1		T113	4		T330	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	19	1			T203	6		T325	5		T331	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T326	3		T315	5		T332	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	8	1			T328	8		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	32	1			T330	8		T315	4		T333	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	44	1			T7	3		T313	4		T334	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T330	2		T335	1		T336	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T7	3		T337	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	22	1			T7	3		T208	6		T338	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T7	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	54	1			T10	9		T11	2		T41	6
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	62	1			T31	2		T113	3		T321	8
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T328	6		T339	2		T340	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T341	2		T76	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	7	1			T113	3		T338	1		T342	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T94	4		T327	6		T343	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	20	1			T10	3		T344	4		T345	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T346	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T347	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T348	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

62

1

T37

2

T95

2

T330

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

111

1

T10

9

T238

9

T204

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

48

1

T9

4

T92

3

T209

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

138

1

T7

3

T21

2

T214

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

46

1

T9

5

T95

2

T330

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

76

1

T10

3

T11

2

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T349

3

T235

3

T79

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

85

1

T31

2

T266

16

T94

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T11

3

T204

8

T330

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T32

6

T113

4

T156

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T188

3

T113

3

T350

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

80

1

T31

2

T41

6

T113

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T230

3

T210

3

T318

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T211

2

T176

9

T328

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T214

1

T172

1

T232

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

110

1

T7

2

T208

9

T214

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

40

1

T2

4

T38

3

T91

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

88

1

T7

3

T114

3

T188

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T11

1

T32

2

T311

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

84

1

T10

18

T41

4

T212

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T210

2

T315

4

T336

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T7

3

T211

2

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T311

1

T97

2

T314

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T32

7

T94

4

T313

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T114

3

T188

2

T212

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T208

9

T214

2

T156

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T38

1

T190

1

T352

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T114

1

T204

8

T311

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T312

1

T310

1

T318

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T95

1

T190

2

T327

16

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T353

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded