Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T14

10

T59

9

T66

10

auto[1]

1031

1

T14

10

T59

11

T66

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T14

6

T59

4

T66

5

from_0to1

496

1

T14

6

T59

4

T66

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T14

11

T59

8

T66

13

auto[1]

1003

1

T14

9

T59

12

T66

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T14

11

T59

13

T66

10

auto[1]

1030

1

T14

9

T59

7

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T14

2

T66

1

T38

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T66

1

T39

1

T38

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T14

3

T59

2

T39

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T59

1

T38

1

T117

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T59

1

T66

1

T135

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T14

1

T66

1

T39

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T14

1

T59

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T66

1

T39

2

T131

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T66

1

T131

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T14

1

T66

1

T39

3

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T38

2

T135

1

T143

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T59

1

T66

1

T131

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T14

1

T59

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T14

2

T39

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T38

3

T135

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T59

1

T131

1

T135

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T14

12

T59

5

T66

12

auto[1]

1012

1

T14

8

T59

15

T66

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T14

3

T59

5

T66

5

from_0to1

494

1

T14

3

T59

5

T66

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T14

12

T59

9

T66

12

auto[1]

1029

1

T14

8

T59

11

T66

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T14

11

T59

13

T66

11

auto[1]

1012

1

T14

9

T59

7

T66

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T66

2

T38

2

T135

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T14

1

T66

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T38

2

T111

1

T182

3

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T39

1

T38

1

T135

2

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T59

1

T38

1

T143

3

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T39

1

T38

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T14

1

T66

1

T135

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T66

1

T39

2

T38

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T14

1

T39

1

T131

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T14

1

T59

1

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T59

3

T66

1

T39

2

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T59

1

T39

1

T131

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T59

1

T39

1

T131

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T59

2

T66

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T14

1

T59

1

T66

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T39

1

T131

2

T38

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T14

11

T59

13

T66

14

auto[1]

1051

1

T14

9

T59

7

T66

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

486

1

T14

4

T59

5

T66

5

from_0to1

487

1

T14

5

T59

4

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T14

12

T59

10

T66

10

auto[1]

1043

1

T14

8

T59

10

T66

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T14

11

T59

13

T66

9

auto[1]

1025

1

T14

9

T59

7

T66

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T59

1

T66

2

T131

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T14

1

T39

2

T117

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T14

1

T59

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T59

1

T66

2

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T59

1

T66

2

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T39

1

T38

2

T135

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T59

1

T66

2

T131

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T14

1

T59

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T59

1

T66

1

T38

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T14

2

T59

1

T135

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T39

1

T38

2

T117

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T38

2

T135

1

T117

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T14

1

T66

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T14

1

T39

2

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T14

1

T59

1

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T14

1

T120

1

T143

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1017

1

T14

11

T59

12

T66

10

auto[1]

1030

1

T14

9

T59

8

T66

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T14

5

T59

4

T66

6

from_0to1

475

1

T14

5

T59

4

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

997

1

T14

11

T59

7

T66

11

auto[1]

1050

1

T14

9

T59

13

T66

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T14

10

T59

12

T66

10

auto[1]

1014

1

T14

10

T59

8

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T131

1

T38

3

T182

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T14

2

T66

2

T39

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T59

2

T66

1

T39

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T14

1

T66

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T38

2

T182

1

T371

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T39

2

T38

1

T135

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T14

1

T59

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T59

1

T135

2

T182

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T14

2

T59

2

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T66

1

T135

2

T117

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T131

1

T38

2

T117

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T39

1

T131

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T14

2

T66

1

T38

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T14

2

T66

1

T131

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T59

2

T66

1

T131

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T66

2

T38

2

T117

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

997

1

T14

11

T59

10

T66

7

auto[1]

1050

1

T14

9

T59

10

T66

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T14

5

T59

6

T66

5

from_0to1

486

1

T14

5

T59

6

T66

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T14

6

T59

13

T66

12

auto[1]

1002

1

T14

14

T59

7

T66

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T14

13

T59

9

T66

11

auto[1]

996

1

T14

7

T59

11

T66

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T14

1

T59

1

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T59

1

T371

1

T372

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T14

2

T39

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T14

1

T59

2

T66

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T14

1

T39

1

T38

3

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T59

3

T38

1

T111

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T14

1

T117

1

T371

3

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T14

1

T39

2

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T66

1

T117

1

T120

2

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T59

1

T66

2

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T39

3

T38

2

T120

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T14

1

T59

1

T143

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T59

1

T66

3

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T66

1

T39

1

T131

3

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T14

1

T59

2

T66

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T14

1

T131

1

T120

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T14

11

T59

12

T66

9

auto[1]

1057

1

T14

9

T59

8

T66

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T14

3

T59

4

T66

6

from_0to1

482

1

T14

3

T59

5

T66

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T14

14

T59

10

T66

10

auto[1]

991

1

T14

6

T59

10

T66

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T14

10

T59

9

T66

10

auto[1]

1024

1

T14

10

T59

11

T66

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T14

1

T38

1

T135

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T59

2

T66

1

T131

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T14

1

T39

1

T131

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T59

1

T39

2

T38

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T59

1

T135

1

T143

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T14

1

T66

1

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T59

2

T66

3

T117

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T135

1

T117

1

T37

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T14

1

T66

1

T135

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T59

1

T66

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T66

1

T39

1

T131

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T66

2

T131

1

T135

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T66

1

T39

1

T131

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T59

1

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T39

2

T131

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T59

1

T66

1

T39

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T14

9

T59

14

T66

9

auto[1]

1006

1

T14

11

T59

6

T66

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

485

1

T14

4

T59

4

T66

5

from_0to1

490

1

T14

4

T59

5

T66

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T14

10

T59

12

T66

8

auto[1]

1044

1

T14

10

T59

8

T66

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T14

13

T59

8

T66

11

auto[1]

992

1

T14

7

T59

12

T66

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T59

1

T131

1

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T59

2

T120

2

T372

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T131

1

T38

1

T135

2

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T59

1

T66

2

T38

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T14

1

T39

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T59

1

T66

1

T38

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T59

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T14

2

T39

2

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T14

1

T66

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T66

1

T39

2

T131

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T14

3

T39

2

T131

2

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T66

1

T39

1

T135

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T59

1

T66

2

T131

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T59

1

T66

1

T39

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T59

1

T66

1

T131

3

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T39

1

T38

3

T120

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T14

11

T59

12

T66

12

auto[1]

1027

1

T14

9

T59

8

T66

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T14

6

T59

3

T66

3

from_0to1

504

1

T14

5

T59

3

T66

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T14

13

T59

12

T66

9

auto[1]

1027

1

T14

7

T59

8

T66

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1046

1

T14

10

T59

7

T66

12

auto[1]

1001

1

T14

10

T59

13

T66

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T14

2

T66

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T14

1

T59

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T120

1

T143

1

T371

2

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T59

1

T66

1

T38

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T14

2

T59

1

T131

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T66

1

T38

2

T120

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T14

1

T39

1

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T14

1

T59

1

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T131

1

T38

2

T120

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T14

2

T59

1

T131

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T14

1

T66

1

T131

2

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T39

1

T38

2

T135

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T39

1

T131

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T131

1

T38

1

T135

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T14

1

T38

2

T135

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T59

1

T66

2

T38

2