Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
54.55	54.55	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_wkup_event_cg	54.55	1	100	1	64	64

---

Group Instance : sysrst_ctrl_wkup_event_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
54.55	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	23	15	8	34.78

Variables for Group Instance sysrst_ctrl_wkup_event_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_h2l_pwrb	2	0	2	100.00	100	1	1	2
cp_h_ac_present	2	0	2	100.00	100	1	1	2
cp_interrupt_gen	2	0	2	100.00	100	1	1	2
cp_l2h_lid_open	2	0	2	100.00	100	1	1	2
cp_wakeup_sts	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_wkup_event_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_wkup_sts	23	15	8	34.78	100	1	1	0

Summary for Variable cp_h2l_pwrb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h2l_pwrb

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

889

1

T6

1

T14

2

T22

4

auto[1]

811

1

T14

1

T22

1

T23

5

---

Summary for Variable cp_h_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T6

1

T14

2

T22

1

auto[1]

682

1

T14

1

T22

4

T23

5

---

Summary for Variable cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt_gen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1699	1			T6	1		T14	3		T22	5
auto[1]	1	1			T297	1		-	-		-	-

---

Summary for Variable cp_l2h_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_l2h_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T6

1

T14

2

T22

3

auto[1]

645

1

T14

1

T22

2

T23

4

---

Summary for Variable cp_wakeup_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wakeup_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1627

1

T6

1

T14

3

T22

5

auto[1]

73

1

T19

3

T20

1

T21

2

---

Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	23	15	8	34.78	15
Automatically Generated Cross Bins	23	15	8	34.78	15
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_wkup_sts

Element holes

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Uncovered bins

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_wakeup_sts

cp_h2l_pwrb

cp_l2h_lid_open

cp_h_ac_present

cp_interrupt_gen

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

376

1

T6

1

T14

1

T22

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

182

1

T22

2

T24

1

T50

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

159

1

T24

1

T25

1

T60

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

171

1

T14

1

T22

1

T23

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

264

1

T14

1

T23

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

159

1

T23

1

T44

2

T133

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

145

1

T50

1

T64

2

T44

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

170

1

T22

1

T23

3

T50

1

User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded