Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113367

1

T1

9

T5

2

T6

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133128	1			T1	14		T5	3		T6	2
values[0x0]	65031	1			T1	3		T5	2		T6	32
values[0x1]	66204	1			T1	5		T5	1		T6	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141976

1

T1

14

T5

4

T6

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	800	1			T13	2		T7	5		T14	3
valid_sources[0x01]	841	1			T6	1		T13	3		T7	4
valid_sources[0x02]	900	1			T13	2		T7	2		T9	4
valid_sources[0x03]	973	1			T7	3		T10	1		T11	4
valid_sources[0x04]	1334	1			T13	1		T7	1		T10	1
valid_sources[0x05]	859	1			T1	1		T13	1		T7	4
valid_sources[0x06]	882	1			T13	1		T7	2		T14	1
valid_sources[0x07]	1006	1			T6	3		T7	2		T10	5
valid_sources[0x08]	1136	1			T13	7		T7	3		T14	1
valid_sources[0x09]	1350	1			T13	1		T7	10		T23	12
valid_sources[0x0a]	925	1			T13	3		T7	2		T9	2
valid_sources[0x0b]	2097	1			T13	6		T7	5		T14	1
valid_sources[0x0c]	905	1			T13	2		T7	2		T10	3
valid_sources[0x0d]	939	1			T13	9		T7	6		T29	1
valid_sources[0x0e]	868	1			T13	2		T7	1		T14	1
valid_sources[0x0f]	1253	1			T7	4		T10	1		T25	1
valid_sources[0x10]	1050	1			T6	4		T13	2		T7	6
valid_sources[0x11]	883	1			T13	2		T7	3		T48	1
valid_sources[0x12]	989	1			T1	1		T7	10		T26	1
valid_sources[0x13]	1055	1			T13	2		T7	1		T10	4
valid_sources[0x14]	2151	1			T7	1		T31	1		T41	2
valid_sources[0x15]	1073	1			T13	5		T7	3		T4	1
valid_sources[0x16]	920	1			T7	8		T4	1		T9	8
valid_sources[0x17]	960	1			T1	1		T7	4		T14	1
valid_sources[0x18]	846	1			T13	3		T7	4		T10	2
valid_sources[0x19]	961	1			T7	6		T8	2		T10	4
valid_sources[0x1a]	895	1			T13	3		T7	3		T26	1
valid_sources[0x1b]	845	1			T13	2		T7	3		T9	1
valid_sources[0x1c]	871	1			T13	1		T7	4		T10	4
valid_sources[0x1d]	862	1			T1	1		T13	1		T9	3
valid_sources[0x1e]	855	1			T13	2		T7	7		T10	3
valid_sources[0x1f]	1253	1			T9	1		T10	1		T50	2
valid_sources[0x20]	870	1			T13	4		T7	4		T9	4
valid_sources[0x21]	807	1			T13	1		T7	1		T10	2
valid_sources[0x22]	1153	1			T13	3		T7	2		T29	1
valid_sources[0x23]	1283	1			T13	3		T7	1		T9	1
valid_sources[0x24]	895	1			T7	8		T9	1		T10	5
valid_sources[0x25]	1057	1			T1	3		T7	2		T14	1
valid_sources[0x26]	864	1			T6	2		T7	5		T4	2
valid_sources[0x27]	1283	1			T7	2		T10	5		T50	1
valid_sources[0x28]	796	1			T13	3		T7	1		T10	2
valid_sources[0x29]	808	1			T13	1		T7	5		T9	2
valid_sources[0x2a]	945	1			T13	1		T7	11		T14	2
valid_sources[0x2b]	1074	1			T6	4		T13	1		T7	2
valid_sources[0x2c]	1015	1			T13	5		T7	3		T10	1
valid_sources[0x2d]	1455	1			T13	1		T7	5		T10	4
valid_sources[0x2e]	1547	1			T13	8		T7	1		T14	1
valid_sources[0x2f]	1317	1			T13	7		T7	8		T14	1
valid_sources[0x30]	856	1			T6	1		T7	3		T10	2
valid_sources[0x31]	815	1			T13	2		T7	3		T14	1
valid_sources[0x32]	1136	1			T13	2		T7	2		T47	1
valid_sources[0x33]	975	1			T13	12		T7	1		T9	2
valid_sources[0x34]	988	1			T13	2		T7	5		T14	1
valid_sources[0x35]	929	1			T13	1		T7	2		T9	1
valid_sources[0x36]	874	1			T13	5		T7	2		T14	1
valid_sources[0x37]	850	1			T13	6		T7	3		T10	2
valid_sources[0x38]	882	1			T13	5		T7	7		T48	1
valid_sources[0x39]	1033	1			T13	2		T7	8		T10	5
valid_sources[0x3a]	1043	1			T7	5		T10	5		T31	7
valid_sources[0x3b]	1084	1			T7	2		T14	1		T10	2
valid_sources[0x3c]	1023	1			T7	4		T29	3		T10	4
valid_sources[0x3d]	1226	1			T7	1		T9	1		T10	9
valid_sources[0x3e]	899	1			T6	3		T13	3		T7	3
valid_sources[0x3f]	1206	1			T6	7		T13	4		T7	1
valid_sources[0x40]	847	1			T7	2		T9	1		T10	5
valid_sources[0x41]	1154	1			T7	3		T14	2		T10	6
valid_sources[0x42]	876	1			T13	2		T7	2		T14	2
valid_sources[0x43]	852	1			T6	3		T13	4		T7	5
valid_sources[0x44]	845	1			T6	1		T7	1		T4	3
valid_sources[0x45]	706	1			T13	2		T7	2		T9	8
valid_sources[0x46]	1806	1			T13	1		T7	7		T26	1
valid_sources[0x47]	997	1			T13	2		T7	6		T9	9
valid_sources[0x48]	853	1			T13	1		T7	9		T9	2
valid_sources[0x49]	884	1			T13	1		T7	3		T9	3
valid_sources[0x4a]	912	1			T5	1		T7	6		T14	2
valid_sources[0x4b]	899	1			T7	8		T14	1		T26	1
valid_sources[0x4c]	940	1			T13	1		T7	1		T10	4
valid_sources[0x4d]	1178	1			T13	2		T7	2		T14	6
valid_sources[0x4e]	1144	1			T1	1		T6	1		T7	2
valid_sources[0x4f]	824	1			T13	4		T7	8		T10	6
valid_sources[0x50]	862	1			T7	1		T14	1		T10	4
valid_sources[0x51]	927	1			T7	4		T9	1		T10	5
valid_sources[0x52]	1071	1			T13	4		T7	5		T14	1
valid_sources[0x53]	846	1			T13	2		T7	2		T10	6
valid_sources[0x54]	1372	1			T13	2		T7	5		T14	1
valid_sources[0x55]	916	1			T13	3		T7	4		T14	1
valid_sources[0x56]	1129	1			T13	3		T7	8		T8	7
valid_sources[0x57]	880	1			T3	1		T7	1		T10	3
valid_sources[0x58]	813	1			T13	6		T7	5		T9	2
valid_sources[0x59]	844	1			T6	3		T7	6		T9	1
valid_sources[0x5a]	1895	1			T13	3		T7	3		T14	1
valid_sources[0x5b]	829	1			T13	2		T7	9		T9	3
valid_sources[0x5c]	922	1			T6	3		T13	10		T7	3
valid_sources[0x5d]	1722	1			T13	2		T7	2		T26	1
valid_sources[0x5e]	876	1			T7	5		T9	2		T10	6
valid_sources[0x5f]	985	1			T7	4		T10	3		T31	3
valid_sources[0x60]	897	1			T3	3		T13	1		T7	4
valid_sources[0x61]	907	1			T1	1		T13	1		T7	3
valid_sources[0x62]	1282	1			T7	3		T14	1		T48	1
valid_sources[0x63]	880	1			T13	6		T7	8		T9	6
valid_sources[0x64]	947	1			T13	1		T7	1		T26	1
valid_sources[0x65]	1045	1			T7	3		T10	3		T11	1
valid_sources[0x66]	906	1			T3	3		T13	2		T7	4
valid_sources[0x67]	909	1			T7	4		T15	2		T10	2
valid_sources[0x68]	800	1			T3	1		T7	3		T10	8
valid_sources[0x69]	758	1			T7	5		T14	1		T47	1
valid_sources[0x6a]	934	1			T7	2		T10	4		T11	12
valid_sources[0x6b]	749	1			T13	1		T7	2		T48	1
valid_sources[0x6c]	856	1			T10	1		T11	12		T25	1
valid_sources[0x6d]	1010	1			T13	2		T9	1		T10	4
valid_sources[0x6e]	936	1			T6	1		T13	2		T7	3
valid_sources[0x6f]	1149	1			T13	9		T7	2		T4	1
valid_sources[0x70]	1050	1			T7	3		T9	9		T10	5
valid_sources[0x71]	936	1			T3	1		T7	4		T14	2
valid_sources[0x72]	960	1			T13	1		T7	6		T14	2
valid_sources[0x73]	847	1			T6	1		T7	1		T9	5
valid_sources[0x74]	971	1			T13	1		T7	4		T14	2
valid_sources[0x75]	985	1			T13	1		T7	6		T14	1
valid_sources[0x76]	875	1			T13	3		T7	3		T23	6
valid_sources[0x77]	1070	1			T13	3		T7	1		T47	1
valid_sources[0x78]	1014	1			T6	2		T13	5		T7	4
valid_sources[0x79]	1074	1			T13	1		T7	3		T9	12
valid_sources[0x7a]	1923	1			T13	1		T7	4		T14	2
valid_sources[0x7b]	962	1			T7	4		T14	1		T10	4
valid_sources[0x7c]	804	1			T7	9		T10	6		T50	1
valid_sources[0x7d]	923	1			T7	2		T26	1		T9	4
valid_sources[0x7e]	1077	1			T3	1		T13	5		T7	3
valid_sources[0x7f]	865	1			T7	2		T14	1		T9	1
valid_sources[0x80]	961	1			T7	3		T10	7		T31	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59631

1

T1

7

T5

1

T6

1

values[0x0]

all_enables

biggest_size

31458

1

T1

1

T5

1

T6

14

values[0x1]

all_enables

biggest_size

22278

1

T1

1

T6

5

T2

16