Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T27,T28,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T27,T28,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T27,T28,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T40
1	0	Covered	T1,T6,T2
1	1	Covered	T27,T28,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T40
0	1	Covered	T77,T100,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T40
0	1	Covered	T27,T28,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T40
1	-	Covered	T27,T28,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T40
DetectSt	168	Covered	T27,T28,T40
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T27,T28,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T40
DebounceSt->IdleSt	163	Covered	T43,T44,T122
DetectSt->IdleSt	186	Covered	T77,T100,T101
DetectSt->StableSt	191	Covered	T27,T28,T40
IdleSt->DebounceSt	148	Covered	T27,T28,T40
StableSt->IdleSt	206	Covered	T27,T28,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T28,T40
0	1	Covered	T27,T28,T40
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T40
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T44,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T40
DetectSt	-	-	-	-	1	-	-	Covered	T77,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T40
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	315	0	0
CntIncr_A	8272513	139257	0	0
CntNoWrap_A	8272513	7602839	0	0
DetectStDropOut_A	8272513	3	0	0
DetectedOut_A	8272513	951	0	0
DetectedPulseOut_A	8272513	144	0	0
DisabledIdleSt_A	8272513	7456389	0	0
DisabledNoDetection_A	8272513	7458632	0	0
EnterDebounceSt_A	8272513	169	0	0
EnterDetectSt_A	8272513	147	0	0
EnterStableSt_A	8272513	144	0	0
PulseIsPulse_A	8272513	144	0	0
StayInStableSt	8272513	807	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	7145	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	144	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	315	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	8	0	0
T27	61982	2	0	0
T28	21366	4	0	0
T31	11371	0	0	0
T33	0	2	0	0
T40	2520	4	0	0
T43	0	1	0	0
T44	0	7	0	0
T45	0	2	0	0
T46	0	2	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	139257	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	192	0	0
T27	61982	47	0	0
T28	21366	20754	0	0
T31	11371	0	0	0
T33	0	59	0	0
T40	2520	142	0	0
T43	0	88	0	0
T44	0	229	0	0
T45	0	34	0	0
T46	0	68	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7602839	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3	0	0
T77	50447	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	4054	0	0	0
T103	729	0	0	0
T104	748	0	0	0
T105	521	0	0	0
T106	65191	0	0	0
T107	1203	0	0	0
T108	422	0	0	0
T109	403	0	0	0
T110	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	951	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	16	0	0
T27	61982	6	0	0
T28	21366	15	0	0
T31	11371	0	0	0
T33	0	4	0	0
T40	2520	10	0	0
T44	0	17	0	0
T45	0	6	0	0
T46	0	2	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	9	0	0
T111	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	144	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7456389	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7458632	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	169	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T43	0	1	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	147	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	144	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	144	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	807	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	12	0	0
T27	61982	5	0	0
T28	21366	13	0	0
T31	11371	0	0	0
T33	0	3	0	0
T40	2520	8	0	0
T44	0	14	0	0
T45	0	5	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	8	0	0
T111	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7145	0	0
T1	1033	1	0	0
T2	14513	16	0	0
T3	958	0	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	3	0	0
T7	16409	35	0	0
T13	4971	29	0	0
T14	507	6	0	0
T15	408	0	0	0
T22	0	9	0	0
T23	0	19	0	0
T24	0	8	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	144	0	0
T12	682	0	0	0
T19	813634	0	0	0
T21	0	4	0	0
T27	61982	1	0	0
T28	21366	2	0	0
T31	11371	0	0	0
T33	0	1	0	0
T40	2520	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T88	0	1	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T6,T2
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T21,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T21,T55,T84
DetectSt->IdleSt	186	Covered	T21,T86,T87
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T55,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T21,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	190	0	0
CntIncr_A	8272513	420696	0	0
CntNoWrap_A	8272513	7602964	0	0
DetectStDropOut_A	8272513	13	0	0
DetectedOut_A	8272513	648558	0	0
DetectedPulseOut_A	8272513	60	0	0
DisabledIdleSt_A	8272513	6104633	0	0
DisabledNoDetection_A	8272513	6106923	0	0
EnterDebounceSt_A	8272513	118	0	0
EnterDetectSt_A	8272513	73	0	0
EnterStableSt_A	8272513	60	0	0
PulseIsPulse_A	8272513	60	0	0
StayInStableSt	8272513	648498	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	7145	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_sticky_sva.StableStDropOut_A	8272513	396795	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	190	0	0
T19	813634	6	0	0
T20	0	2	0	0
T21	0	7	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	2	0	0
T54	0	4	0	0
T55	0	4	0	0
T56	0	6	0	0
T57	0	2	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	2	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	420696	0	0
T19	813634	174993	0	0
T20	0	82	0	0
T21	0	226	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	34	0	0
T54	0	50	0	0
T55	0	192	0	0
T56	0	105	0	0
T57	0	31	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	64	0	0
T73	0	146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7602964	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	13	0	0
T21	26081	2	0	0
T51	2454	0	0	0
T52	65711	0	0	0
T53	842	0	0	0
T70	5266	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T106	0	1	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0
T123	0	1	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	648558	0	0
T19	813634	637726	0	0
T20	0	152	0	0
T21	0	185	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	290	0	0
T54	0	237	0	0
T56	0	200	0	0
T57	0	17	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	249	0	0
T73	0	409	0	0
T115	0	71	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	60	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6104633	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6106923	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	118	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	4	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	73	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	3	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	60	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	60	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	648498	0	0
T19	813634	637723	0	0
T20	0	151	0	0
T21	0	184	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	289	0	0
T54	0	235	0	0
T56	0	197	0	0
T57	0	16	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	248	0	0
T73	0	407	0	0
T115	0	70	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7145	0	0
T1	1033	1	0	0
T2	14513	16	0	0
T3	958	0	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	3	0	0
T7	16409	35	0	0
T13	4971	29	0	0
T14	507	6	0	0
T15	408	0	0	0
T22	0	9	0	0
T23	0	19	0	0
T24	0	8	0	0
T26	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	396795	0	0
T19	813634	368	0	0
T20	0	56	0	0
T21	0	492	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	443	0	0
T54	0	548	0	0
T56	0	384	0	0
T57	0	132	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	83	0	0
T73	0	260	0	0
T115	0	155562	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T20,T21,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T6,T3
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T51,T54
0	1	Covered	T20,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T51,T54
0	1	Unreachable
1	0	Covered	T21,T51,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T20,T21,T51
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T21,T51,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T51
DebounceSt->IdleSt	163	Covered	T19,T21,T55
DetectSt->IdleSt	186	Covered	T20,T84,T85
DetectSt->StableSt	191	Covered	T21,T51,T54
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T21,T51,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T51
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T21,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T20,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T21,T51,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T51,T54
StableSt	-	-	-	-	-	-	0	Covered	T21,T51,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	191	0	0
CntIncr_A	8272513	142558	0	0
CntNoWrap_A	8272513	7602963	0	0
DetectStDropOut_A	8272513	15	0	0
DetectedOut_A	8272513	130523	0	0
DetectedPulseOut_A	8272513	52	0	0
DisabledIdleSt_A	8272513	6104633	0	0
DisabledNoDetection_A	8272513	6106923	0	0
EnterDebounceSt_A	8272513	125	0	0
EnterDetectSt_A	8272513	67	0	0
EnterStableSt_A	8272513	52	0	0
PulseIsPulse_A	8272513	52	0	0
StayInStableSt	8272513	130471	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_sticky_sva.StableStDropOut_A	8272513	210648	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	191	0	0
T19	813634	10	0	0
T20	0	4	0	0
T21	0	5	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	2	0	0
T54	0	4	0	0
T55	0	4	0	0
T56	0	4	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	2	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	142558	0	0
T19	813634	330	0	0
T20	0	116	0	0
T21	0	332	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	48	0	0
T54	0	146	0	0
T55	0	212	0	0
T56	0	48	0	0
T57	0	36	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	15	0	0
T73	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7602963	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	15	0	0
T20	724	2	0	0
T34	1679	0	0	0
T38	38665	0	0	0
T45	751	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T126	0	1	0	0
T127	0	5	0	0
T128	0	4	0	0
T129	0	1	0	0
T130	741	0	0	0
T131	505	0	0	0
T132	408	0	0	0
T133	2881	0	0	0
T134	422	0	0	0
T135	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	130523	0	0
T21	26081	562	0	0
T51	2454	197	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	550	0	0
T70	5266	0	0	0
T72	0	79	0	0
T73	0	82	0	0
T80	0	707	0	0
T84	0	98	0	0
T86	0	364	0	0
T115	0	223	0	0
T116	0	103	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	52	0	0
T21	26081	1	0	0
T51	2454	1	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	2	0	0
T70	5266	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T80	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6104633	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6106923	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	125	0	0
T19	813634	10	0	0
T20	0	2	0	0
T21	0	4	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	4	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	67	0	0
T20	724	2	0	0
T21	0	1	0	0
T34	1679	0	0	0
T38	38665	0	0	0
T45	751	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T84	0	2	0	0
T86	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T130	741	0	0	0
T131	505	0	0	0
T132	408	0	0	0
T133	2881	0	0	0
T134	422	0	0	0
T135	502	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	52	0	0
T21	26081	1	0	0
T51	2454	1	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	2	0	0
T70	5266	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T80	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	52	0	0
T21	26081	1	0	0
T51	2454	1	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	2	0	0
T70	5266	0	0	0
T72	0	1	0	0
T73	0	2	0	0
T80	0	2	0	0
T84	0	1	0	0
T86	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	130471	0	0
T21	26081	561	0	0
T51	2454	196	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	548	0	0
T70	5266	0	0	0
T72	0	78	0	0
T73	0	80	0	0
T80	0	705	0	0
T84	0	97	0	0
T86	0	363	0	0
T115	0	222	0	0
T116	0	102	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	210648	0	0
T21	26081	81	0	0
T51	2454	518	0	0
T52	65711	0	0	0
T53	842	0	0	0
T54	0	136	0	0
T70	5266	0	0	0
T72	0	304	0	0
T73	0	675	0	0
T80	0	128	0	0
T84	0	265	0	0
T86	0	59	0	0
T115	0	155380	0	0
T116	0	41	0	0
T117	502	0	0	0
T118	402	0	0	0
T119	1015	0	0	0
T120	506	0	0	0
T121	452	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T6,T2
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T54,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T55,T56,T73
DetectSt->IdleSt	186	Covered	T54,T80,T81
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T56,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T54,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	197	0	0
CntIncr_A	8272513	64183	0	0
CntNoWrap_A	8272513	7602957	0	0
DetectStDropOut_A	8272513	16	0	0
DetectedOut_A	8272513	109560	0	0
DetectedPulseOut_A	8272513	44	0	0
DisabledIdleSt_A	8272513	6104633	0	0
DisabledNoDetection_A	8272513	6106923	0	0
EnterDebounceSt_A	8272513	138	0	0
EnterDetectSt_A	8272513	60	0	0
EnterStableSt_A	8272513	44	0	0
PulseIsPulse_A	8272513	44	0	0
StayInStableSt	8272513	109516	0	0
gen_high_event_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_sticky_sva.StableStDropOut_A	8272513	881849	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	197	0	0
T19	813634	6	0	0
T20	0	2	0	0
T21	0	4	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	2	0	0
T54	0	6	0	0
T55	0	4	0	0
T56	0	8	0	0
T57	0	2	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	2	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64183	0	0
T19	813634	279	0	0
T20	0	38	0	0
T21	0	91	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	96	0	0
T54	0	255	0	0
T55	0	316	0	0
T56	0	256	0	0
T57	0	71	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	37	0	0
T73	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7602957	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	16	0	0
T54	1649	1	0	0
T55	996	0	0	0
T56	1228	0	0	0
T71	5170	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T88	3036	0	0	0
T114	13198	0	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	502	0	0	0
T144	737	0	0	0
T145	423	0	0	0
T146	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	109560	0	0
T19	813634	916	0	0
T20	0	93	0	0
T21	0	581	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	629	0	0
T54	0	431	0	0
T57	0	66	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	150	0	0
T84	0	467	0	0
T115	0	99960	0	0
T116	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	44	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6104633	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6106923	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	138	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	3	0	0
T55	0	4	0	0
T56	0	8	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T73	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	60	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	3	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	44	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	44	0	0
T19	813634	3	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	109516	0	0
T19	813634	913	0	0
T20	0	92	0	0
T21	0	579	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	628	0	0
T54	0	429	0	0
T57	0	65	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	149	0	0
T84	0	466	0	0
T115	0	99959	0	0
T116	0	17	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	881849	0	0
T19	813634	811936	0	0
T20	0	161	0	0
T21	0	556	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T40	2520	0	0	0
T51	0	56	0	0
T54	0	154	0	0
T57	0	58	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T62	423	0	0	0
T63	402	0	0	0
T72	0	217	0	0
T84	0	110	0	0
T115	0	40	0	0
T116	0	169	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T33,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T33,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T33,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T4,T33,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T38
0	1	Covered	T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T38
0	1	Covered	T33,T38,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T33,T38
1	-	Covered	T33,T38,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T33,T38
DetectSt	168	Covered	T4,T33,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T33,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T33,T38
DebounceSt->IdleSt	163	Covered	T74,T147,T75
DetectSt->IdleSt	186	Covered	T102
DetectSt->StableSt	191	Covered	T4,T33,T38
IdleSt->DebounceSt	148	Covered	T4,T33,T38
StableSt->IdleSt	206	Covered	T33,T38,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T33,T38
0	1	Covered	T4,T33,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T33,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T33,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T33,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T147
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T33,T38
DetectSt	-	-	-	-	1	-	-	Covered	T102
DetectSt	-	-	-	-	0	1	-	Covered	T4,T33,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T38,T34
StableSt	-	-	-	-	-	-	0	Covered	T4,T33,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	64	0	0
CntIncr_A	8272513	2000	0	0
CntNoWrap_A	8272513	7603090	0	0
DetectStDropOut_A	8272513	1	0	0
DetectedOut_A	8272513	3281	0	0
DetectedPulseOut_A	8272513	29	0	0
DisabledIdleSt_A	8272513	7587352	0	0
DisabledNoDetection_A	8272513	7589607	0	0
EnterDebounceSt_A	8272513	34	0	0
EnterDetectSt_A	8272513	30	0	0
EnterStableSt_A	8272513	29	0	0
PulseIsPulse_A	8272513	29	0	0
StayInStableSt	8272513	3240	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T4	930	2	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	6	0	0
T34	0	4	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T47	403	0	0	0
T48	419	0	0	0
T74	0	1	0	0
T82	0	2	0	0
T102	0	4	0	0
T119	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2000	0	0
T4	930	81	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	168	0	0
T34	0	144	0	0
T36	0	61	0	0
T37	0	250	0	0
T38	0	35	0	0
T47	403	0	0	0
T48	419	0	0	0
T74	0	22	0	0
T82	0	90	0	0
T102	0	140	0	0
T119	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603090	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	527	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1	0	0
T102	4054	1	0	0
T103	729	0	0	0
T104	748	0	0	0
T105	521	0	0	0
T106	65191	0	0	0
T107	1203	0	0	0
T108	422	0	0	0
T109	403	0	0	0
T110	407	0	0	0
T148	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3281	0	0
T4	930	40	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	425	0	0
T34	0	81	0	0
T36	0	464	0	0
T37	0	473	0	0
T38	0	109	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	263	0	0
T102	0	63	0	0
T119	0	145	0	0
T149	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	29	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	1	0	0
T102	0	1	0	0
T119	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7587352	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7589607	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	34	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T74	0	1	0	0
T82	0	1	0	0
T102	0	2	0	0
T119	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	30	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	1	0	0
T102	0	2	0	0
T119	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	29	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	1	0	0
T102	0	1	0	0
T119	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	29	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	1	0	0
T102	0	1	0	0
T119	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3240	0	0
T4	930	38	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	421	0	0
T34	0	78	0	0
T36	0	462	0	0
T37	0	468	0	0
T38	0	108	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	262	0	0
T102	0	62	0	0
T119	0	144	0	0
T149	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	17	0	0
T33	3832	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	26333	0	0	0
T42	5716	0	0	0
T43	705	0	0	0
T44	11819	0	0	0
T64	492	0	0	0
T66	503	0	0	0
T67	522	0	0	0
T82	0	1	0	0
T102	0	1	0	0
T119	0	1	0	0
T124	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	539	0	0	0
T152	427	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T12,T33,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T12,T33,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T12,T33,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T33,T44
1	0	Covered	T1,T6,T2
1	1	Covered	T12,T33,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T33,T39
0	1	Covered	T33,T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T33,T39
0	1	Covered	T38,T34,T119
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T33,T39
1	-	Covered	T38,T34,T119

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T33,T39
DetectSt	168	Covered	T12,T33,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T12,T33,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T33,T39
DebounceSt->IdleSt	163	Covered	T34,T37,T74
DetectSt->IdleSt	186	Covered	T33,T153
DetectSt->StableSt	191	Covered	T12,T33,T39
IdleSt->DebounceSt	148	Covered	T12,T33,T39
StableSt->IdleSt	206	Covered	T33,T39,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T33,T39
0	1	Covered	T12,T33,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T33,T39
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T33,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T33,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T37,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T33,T39
DetectSt	-	-	-	-	1	-	-	Covered	T33,T153
DetectSt	-	-	-	-	0	1	-	Covered	T12,T33,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T34,T119
StableSt	-	-	-	-	-	-	0	Covered	T12,T33,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	121	0	0
CntIncr_A	8272513	3690	0	0
CntNoWrap_A	8272513	7603033	0	0
DetectStDropOut_A	8272513	2	0	0
DetectedOut_A	8272513	3993	0	0
DetectedPulseOut_A	8272513	55	0	0
DisabledIdleSt_A	8272513	7586624	0	0
DisabledNoDetection_A	8272513	7588872	0	0
EnterDebounceSt_A	8272513	64	0	0
EnterDetectSt_A	8272513	57	0	0
EnterStableSt_A	8272513	55	0	0
PulseIsPulse_A	8272513	55	0	0
StayInStableSt	8272513	3911	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	2668	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	121	0	0
T12	682	2	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T37	0	3	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	4	0	0
T119	0	4	0	0
T155	0	4	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3690	0	0
T12	682	79	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	150	0	0
T34	0	144	0	0
T37	0	184	0	0
T38	0	70	0	0
T39	0	85	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	180	0	0
T119	0	124	0	0
T155	0	136	0	0
T156	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603033	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2	0	0
T33	3832	1	0	0
T41	26333	0	0	0
T42	5716	0	0	0
T43	705	0	0	0
T44	11819	0	0	0
T64	492	0	0	0
T66	503	0	0	0
T67	522	0	0	0
T151	539	0	0	0
T152	427	0	0	0
T153	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3993	0	0
T12	682	42	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	132	0	0
T34	0	1	0	0
T37	0	43	0	0
T38	0	70	0	0
T39	0	78	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	88	0	0
T119	0	273	0	0
T155	0	87	0	0
T156	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	55	0	0
T12	682	1	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	2	0	0
T119	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7586624	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7588872	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T12	682	1	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	2	0	0
T119	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	57	0	0
T12	682	1	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	2	0	0
T119	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	55	0	0
T12	682	1	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	2	0	0
T119	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	55	0	0
T12	682	1	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	2	0	0
T119	0	2	0	0
T155	0	2	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3911	0	0
T12	682	40	0	0
T19	813634	0	0	0
T28	21366	0	0	0
T31	11371	0	0	0
T32	28014	0	0	0
T33	0	130	0	0
T37	0	42	0	0
T38	0	67	0	0
T39	0	76	0	0
T40	2520	0	0	0
T58	425	0	0	0
T59	518	0	0	0
T60	526	0	0	0
T61	426	0	0	0
T82	0	85	0	0
T102	0	208	0	0
T119	0	270	0	0
T155	0	84	0	0
T156	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2668	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	1	0	0
T5	735	0	0	0
T6	523	4	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	5	0	0
T15	408	0	0	0
T22	0	4	0	0
T23	0	11	0	0
T24	0	6	0	0
T48	0	2	0	0
T49	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	28	0	0
T34	1679	1	0	0
T35	674	0	0	0
T37	0	1	0	0
T38	38665	1	0	0
T45	751	0	0	0
T69	6400	0	0	0
T82	0	1	0	0
T102	0	2	0	0
T119	0	1	0	0
T132	408	0	0	0
T133	2881	0	0	0
T134	422	0	0	0
T135	502	0	0	0
T149	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	402	0	0	0