Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T8,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T8,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T8,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T33
0	1	Covered	T34
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T33
0	1	Covered	T33,T37,T82
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T33
1	-	Covered	T33,T37,T82

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T33
DetectSt	168	Covered	T3,T8,T33
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T8,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T33
DebounceSt->IdleSt	163	Covered	T74,T75,T159
DetectSt->IdleSt	186	Covered	T34
DetectSt->StableSt	191	Covered	T3,T8,T33
IdleSt->DebounceSt	148	Covered	T3,T8,T33
StableSt->IdleSt	206	Covered	T33,T44,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T33
0	1	Covered	T3,T8,T33
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T33
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T33
DetectSt	-	-	-	-	1	-	-	Covered	T34
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T37,T82
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	84	0	0
CntIncr_A	8272513	22863	0	0
CntNoWrap_A	8272513	7603070	0	0
DetectStDropOut_A	8272513	1	0	0
DetectedOut_A	8272513	13875	0	0
DetectedPulseOut_A	8272513	40	0	0
DisabledIdleSt_A	8272513	7338245	0	0
DisabledNoDetection_A	8272513	7340486	0	0
EnterDebounceSt_A	8272513	44	0	0
EnterDetectSt_A	8272513	41	0	0
EnterStableSt_A	8272513	40	0	0
PulseIsPulse_A	8272513	40	0	0
StayInStableSt	8272513	13810	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	84	0	0
T3	958	2	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	2	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T44	0	2	0	0
T82	0	2	0	0
T155	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	22863	0	0
T3	958	97	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	32	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	68	0	0
T34	0	72	0	0
T36	0	61	0	0
T37	0	132	0	0
T44	0	99	0	0
T82	0	90	0	0
T155	0	68	0	0
T160	0	19783	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603070	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	555	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1	0	0
T21	26081	0	0	0
T34	1679	1	0	0
T35	674	0	0	0
T46	677	0	0	0
T51	2454	0	0	0
T65	491	0	0	0
T69	6400	0	0	0
T70	5266	0	0	0
T158	402	0	0	0
T161	595	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	13875	0	0
T3	958	42	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	41	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	99	0	0
T36	0	41	0	0
T37	0	87	0	0
T44	0	44	0	0
T82	0	263	0	0
T155	0	39	0	0
T156	0	41	0	0
T160	0	10547	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	40	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7338245	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7340486	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	44	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	41	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	40	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	40	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	13810	0	0
T3	958	40	0	0
T4	930	0	0	0
T7	16409	0	0	0
T8	0	39	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	98	0	0
T36	0	39	0	0
T37	0	84	0	0
T44	0	42	0	0
T82	0	262	0	0
T155	0	37	0	0
T156	0	39	0	0
T160	0	10546	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	15	0	0
T33	3832	1	0	0
T37	0	1	0	0
T41	26333	0	0	0
T42	5716	0	0	0
T43	705	0	0	0
T44	11819	0	0	0
T64	492	0	0	0
T66	503	0	0	0
T67	522	0	0	0
T82	0	1	0	0
T102	0	1	0	0
T124	0	1	0	0
T151	539	0	0	0
T152	427	0	0	0
T153	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T4,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T5,T6,T2
1	1	Covered	T1,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T33
0	1	Covered	T1,T4,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T33
1	-	Covered	T1,T4,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T8
DetectSt	168	Covered	T1,T4,T33
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T4,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T33
DebounceSt->IdleSt	163	Covered	T8,T44,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T4,T33
IdleSt->DebounceSt	148	Covered	T1,T4,T8
StableSt->IdleSt	206	Covered	T1,T4,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T8
0	1	Covered	T1,T4,T8
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T33
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T44,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	117	0	0
CntIncr_A	8272513	55347	0	0
CntNoWrap_A	8272513	7603037	0	0
DetectStDropOut_A	8272513	0	0	0
DetectedOut_A	8272513	87012	0	0
DetectedPulseOut_A	8272513	53	0	0
DisabledIdleSt_A	8272513	7395089	0	0
DisabledNoDetection_A	8272513	7397330	0	0
EnterDebounceSt_A	8272513	64	0	0
EnterDetectSt_A	8272513	53	0	0
EnterStableSt_A	8272513	53	0	0
PulseIsPulse_A	8272513	53	0	0
StayInStableSt	8272513	86935	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	3112	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	117	0	0
T1	1033	4	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	4	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T44	0	1	0	0
T84	0	2	0	0
T119	0	4	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	55347	0	0
T1	1033	154	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	162	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T8	0	32	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	75	0	0
T35	0	46	0	0
T37	0	35	0	0
T44	0	99	0	0
T84	0	34	0	0
T119	0	124	0	0
T166	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603037	0	0
T1	1033	628	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	525	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	87012	0	0
T1	1033	150	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	111	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	210	0	0
T35	0	161	0	0
T37	0	40	0	0
T82	0	88	0	0
T84	0	99	0	0
T119	0	87	0	0
T160	0	60167	0	0
T166	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	53	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7395089	0	0
T1	1033	4	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	4	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7397330	0	0
T1	1033	4	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	4	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T8	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T44	0	1	0	0
T84	0	1	0	0
T119	0	2	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	53	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	53	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	53	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T82	0	2	0	0
T84	0	1	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	86935	0	0
T1	1033	147	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	109	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	209	0	0
T35	0	159	0	0
T37	0	38	0	0
T82	0	85	0	0
T84	0	98	0	0
T119	0	84	0	0
T160	0	60164	0	0
T166	0	104	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	3112	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	2	0	0
T5	735	4	0	0
T6	523	4	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	7	0	0
T15	408	0	0	0
T22	0	5	0	0
T23	0	10	0	0
T24	0	4	0	0
T48	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	29	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	0	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T102	0	1	0	0
T119	0	1	0	0
T160	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T3,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T6,T2,T13
1	1	Covered	T1,T3,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T12
0	1	Covered	T1,T3,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T12
1	-	Covered	T1,T3,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T12
DetectSt	168	Covered	T1,T3,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T12
DebounceSt->IdleSt	163	Covered	T21,T166,T74
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T1,T3,T12
IdleSt->DebounceSt	148	Covered	T1,T3,T12
StableSt->IdleSt	206	Covered	T1,T3,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T12
0	1	Covered	T1,T3,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T166,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	139	0	0
CntIncr_A	8272513	43696	0	0
CntNoWrap_A	8272513	7603015	0	0
DetectStDropOut_A	8272513	1	0	0
DetectedOut_A	8272513	36302	0	0
DetectedPulseOut_A	8272513	64	0	0
DisabledIdleSt_A	8272513	7454368	0	0
DisabledNoDetection_A	8272513	7456609	0	0
EnterDebounceSt_A	8272513	74	0	0
EnterDetectSt_A	8272513	65	0	0
EnterStableSt_A	8272513	64	0	0
PulseIsPulse_A	8272513	64	0	0
StayInStableSt	8272513	36204	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	139	0	0
T1	1033	2	0	0
T2	14513	0	0	0
T3	958	2	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	2	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T33	0	4	0	0
T34	0	4	0	0
T36	0	2	0	0
T38	0	4	0	0
T84	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	43696	0	0
T1	1033	77	0	0
T2	14513	0	0	0
T3	958	97	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	79	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	55	0	0
T33	0	100	0	0
T34	0	144	0	0
T36	0	61	0	0
T38	0	70	0	0
T84	0	34	0	0
T155	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603015	0	0
T1	1033	630	0	0
T2	14513	14104	0	0
T3	958	555	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1	0	0
T77	50447	0	0	0
T83	4056	1	0	0
T102	4054	0	0	0
T103	729	0	0	0
T104	748	0	0	0
T105	521	0	0	0
T106	65191	0	0	0
T107	1203	0	0	0
T108	422	0	0	0
T169	17161	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	36302	0	0
T1	1033	29	0	0
T2	14513	0	0	0
T3	958	215	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	193	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	112	0	0
T34	0	39	0	0
T36	0	254	0	0
T38	0	69	0	0
T84	0	229	0	0
T155	0	123	0	0
T170	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	2	0	0
T84	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7454368	0	0
T1	1033	4	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7456609	0	0
T1	1033	4	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	74	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	2	0	0
T84	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	65	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	2	0	0
T84	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	2	0	0
T84	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T36	0	1	0	0
T38	0	2	0	0
T84	0	1	0	0
T155	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	36204	0	0
T1	1033	28	0	0
T2	14513	0	0	0
T3	958	214	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T12	0	191	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T33	0	108	0	0
T34	0	36	0	0
T36	0	253	0	0
T38	0	66	0	0
T84	0	227	0	0
T155	0	122	0	0
T170	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	30	0	0
T1	1033	1	0	0
T2	14513	0	0	0
T3	958	1	0	0
T4	930	0	0	0
T5	735	0	0	0
T6	523	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T102	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T171	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T4,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T33
1	0	Covered	T1,T6,T2
1	1	Covered	T3,T4,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T33
0	1	Covered	T4,T33,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T33
1	-	Covered	T4,T33,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T33
DetectSt	168	Covered	T3,T4,T33
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T4,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T33
DebounceSt->IdleSt	163	Covered	T74,T75
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T4,T33
IdleSt->DebounceSt	148	Covered	T3,T4,T33
StableSt->IdleSt	206	Covered	T4,T33,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T33
0	1	Covered	T3,T4,T33
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T33
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T33,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	58	0	0
CntIncr_A	8272513	1547	0	0
CntNoWrap_A	8272513	7603096	0	0
DetectStDropOut_A	8272513	0	0	0
DetectedOut_A	8272513	2259	0	0
DetectedPulseOut_A	8272513	28	0	0
DisabledIdleSt_A	8272513	7530166	0	0
DisabledNoDetection_A	8272513	7532413	0	0
EnterDebounceSt_A	8272513	30	0	0
EnterDetectSt_A	8272513	28	0	0
EnterStableSt_A	8272513	28	0	0
PulseIsPulse_A	8272513	28	0	0
StayInStableSt	8272513	2216	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	6619	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	58	0	0
T3	958	2	0	0
T4	930	4	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	2	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T74	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1547	0	0
T3	958	97	0	0
T4	930	162	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	55	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	136	0	0
T34	0	72	0	0
T37	0	158	0	0
T38	0	35	0	0
T74	0	21	0	0
T82	0	90	0	0
T83	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603096	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	555	0	0
T4	930	525	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2259	0	0
T3	958	41	0	0
T4	930	83	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	50	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	271	0	0
T34	0	116	0	0
T37	0	110	0	0
T38	0	110	0	0
T82	0	309	0	0
T83	0	44	0	0
T172	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	28	0	0
T3	958	1	0	0
T4	930	2	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7530166	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7532413	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	30	0	0
T3	958	1	0	0
T4	930	2	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T74	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	28	0	0
T3	958	1	0	0
T4	930	2	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	28	0	0
T3	958	1	0	0
T4	930	2	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	28	0	0
T3	958	1	0	0
T4	930	2	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2216	0	0
T3	958	39	0	0
T4	930	80	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	48	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	268	0	0
T34	0	115	0	0
T37	0	107	0	0
T38	0	109	0	0
T82	0	307	0	0
T83	0	42	0	0
T172	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6619	0	0
T1	1033	1	0	0
T2	14513	9	0	0
T3	958	1	0	0
T4	930	2	0	0
T5	735	0	0	0
T6	523	3	0	0
T7	16409	29	0	0
T13	4971	28	0	0
T14	507	3	0	0
T15	408	0	0	0
T22	0	6	0	0
T23	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	13	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T124	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T33,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T33,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T33,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T44
1	0	Covered	T1,T6,T2
1	1	Covered	T3,T33,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T38
0	1	Covered	T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T33,T38
0	1	Covered	T33,T38,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T33,T38
1	-	Covered	T33,T38,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T33,T39
DetectSt	168	Covered	T3,T33,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T33,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T33,T38
DebounceSt->IdleSt	163	Covered	T39,T74,T150
DetectSt->IdleSt	186	Covered	T82
DetectSt->StableSt	191	Covered	T3,T33,T38
IdleSt->DebounceSt	148	Covered	T3,T33,T39
StableSt->IdleSt	206	Covered	T33,T38,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T33,T39
0	1	Covered	T3,T33,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T33,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T33,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T33,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T150,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T33,T39
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T33,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T38,T34
StableSt	-	-	-	-	-	-	0	Covered	T3,T33,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	138	0	0
CntIncr_A	8272513	96476	0	0
CntNoWrap_A	8272513	7603016	0	0
DetectStDropOut_A	8272513	1	0	0
DetectedOut_A	8272513	36266	0	0
DetectedPulseOut_A	8272513	64	0	0
DisabledIdleSt_A	8272513	7338055	0	0
DisabledNoDetection_A	8272513	7340296	0	0
EnterDebounceSt_A	8272513	73	0	0
EnterDetectSt_A	8272513	65	0	0
EnterStableSt_A	8272513	64	0	0
PulseIsPulse_A	8272513	64	0	0
StayInStableSt	8272513	36172	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	138	0	0
T3	958	2	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T38	0	2	0	0
T39	0	1	0	0
T82	0	4	0	0
T84	0	4	0	0
T119	0	4	0	0
T160	0	4	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	96476	0	0
T3	958	97	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	75	0	0
T34	0	144	0	0
T38	0	35	0	0
T39	0	85	0	0
T82	0	180	0	0
T84	0	68	0	0
T119	0	124	0	0
T160	0	39566	0	0
T166	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603016	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	555	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1	0	0
T80	1487	0	0	0
T82	1124	1	0	0
T87	704	0	0	0
T94	18267	0	0	0
T123	6171	0	0	0
T160	130474	0	0	0
T175	412	0	0	0
T176	18054	0	0	0
T177	423	0	0	0
T178	9778	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	36266	0	0
T3	958	216	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	41	0	0
T34	0	155	0	0
T38	0	110	0	0
T82	0	37	0	0
T84	0	115	0	0
T102	0	80	0	0
T119	0	269	0	0
T160	0	30412	0	0
T166	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T84	0	2	0	0
T102	0	2	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7338055	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7340296	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	73	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T82	0	2	0	0
T84	0	2	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	65	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T82	0	2	0	0
T84	0	2	0	0
T102	0	2	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T84	0	2	0	0
T102	0	2	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	64	0	0
T3	958	1	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T82	0	1	0	0
T84	0	2	0	0
T102	0	2	0	0
T119	0	2	0	0
T160	0	2	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	36172	0	0
T3	958	214	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	40	0	0
T34	0	152	0	0
T38	0	109	0	0
T82	0	36	0	0
T84	0	112	0	0
T102	0	77	0	0
T119	0	267	0	0
T160	0	30409	0	0
T166	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	34	0	0
T33	3832	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	26333	0	0	0
T42	5716	0	0	0
T43	705	0	0	0
T44	11819	0	0	0
T64	492	0	0	0
T66	503	0	0	0
T67	522	0	0	0
T82	0	1	0	0
T84	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0
T119	0	2	0	0
T149	0	2	0	0
T151	539	0	0	0
T152	427	0	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T33,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T33,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T33,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T6,T2,T13
1	1	Covered	T4,T33,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T39
0	1	Covered	T34,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T33,T39
0	1	Covered	T36,T82,T160
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T33,T39
1	-	Covered	T36,T82,T160

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T33,T39
DetectSt	168	Covered	T4,T33,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T33,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T33,T39
DebounceSt->IdleSt	163	Covered	T74,T154,T147
DetectSt->IdleSt	186	Covered	T34,T179
DetectSt->StableSt	191	Covered	T4,T33,T39
IdleSt->DebounceSt	148	Covered	T4,T33,T39
StableSt->IdleSt	206	Covered	T33,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T33,T39
0	1	Covered	T4,T33,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T33,T39
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T33,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T33,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T147,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T33,T39
DetectSt	-	-	-	-	1	-	-	Covered	T34,T179
DetectSt	-	-	-	-	0	1	-	Covered	T4,T33,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T82,T160
StableSt	-	-	-	-	-	-	0	Covered	T4,T33,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	91	0	0
CntIncr_A	8272513	34789	0	0
CntNoWrap_A	8272513	7603063	0	0
DetectStDropOut_A	8272513	2	0	0
DetectedOut_A	8272513	14878	0	0
DetectedPulseOut_A	8272513	41	0	0
DisabledIdleSt_A	8272513	7395651	0	0
DisabledNoDetection_A	8272513	7397894	0	0
EnterDebounceSt_A	8272513	48	0	0
EnterDetectSt_A	8272513	43	0	0
EnterStableSt_A	8272513	41	0	0
PulseIsPulse_A	8272513	41	0	0
StayInStableSt	8272513	14813	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8272513	6256	0	0
gen_low_level_sva.LowLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	91	0	0
T4	930	2	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T39	0	2	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	4	0	0
T104	0	2	0	0
T160	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	34789	0	0
T4	930	81	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	143	0	0
T34	0	72	0	0
T36	0	122	0	0
T37	0	35	0	0
T39	0	85	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	180	0	0
T104	0	59	0	0
T160	0	19783	0	0
T180	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7603063	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	527	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2	0	0
T21	26081	0	0	0
T34	1679	1	0	0
T35	674	0	0	0
T46	677	0	0	0
T51	2454	0	0	0
T65	491	0	0	0
T69	6400	0	0	0
T70	5266	0	0	0
T158	402	0	0	0
T161	595	0	0	0
T179	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	14878	0	0
T4	930	192	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	470	0	0
T36	0	196	0	0
T37	0	39	0	0
T39	0	38	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	314	0	0
T104	0	131	0	0
T160	0	690	0	0
T171	0	197	0	0
T180	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	41	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	2	0	0
T104	0	1	0	0
T160	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7395651	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	16000	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7397894	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	3	0	0
T4	930	4	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	48	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	2	0	0
T104	0	1	0	0
T160	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	43	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	2	0	0
T104	0	1	0	0
T160	0	1	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	41	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	2	0	0
T104	0	1	0	0
T160	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	41	0	0
T4	930	1	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	2	0	0
T104	0	1	0	0
T160	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	14813	0	0
T4	930	190	0	0
T8	492	0	0	0
T9	18685	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T33	0	466	0	0
T36	0	194	0	0
T37	0	37	0	0
T39	0	36	0	0
T47	403	0	0	0
T48	419	0	0	0
T82	0	311	0	0
T104	0	129	0	0
T160	0	689	0	0
T171	0	195	0	0
T180	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	6256	0	0
T2	14513	14	0	0
T3	958	0	0	0
T4	930	1	0	0
T6	523	4	0	0
T7	16409	32	0	0
T13	4971	19	0	0
T14	507	6	0	0
T15	408	0	0	0
T22	496	6	0	0
T23	0	11	0	0
T24	0	6	0	0
T29	469	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	17	0	0
T36	988	2	0	0
T78	6836	0	0	0
T82	0	1	0	0
T112	7853	0	0	0
T124	0	1	0	0
T147	0	1	0	0
T150	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T181	0	1	0	0
T182	507	0	0	0
T183	2394	0	0	0
T184	422	0	0	0
T185	434	0	0	0
T186	703	0	0	0
T187	442	0	0	0
T188	13768	0	0	0